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1 | /** @file\r | |
2 | Local APIC Library.\r | |
3 | \r | |
4 | This local APIC library instance supports xAPIC mode only.\r | |
5 | \r | |
6 | Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>\r | |
7 | Copyright (c) 2017 - 2020, AMD Inc. All rights reserved.<BR>\r | |
8 | \r | |
9 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
10 | \r | |
11 | **/\r | |
12 | \r | |
13 | #include <Register/Intel/Cpuid.h>\r | |
14 | #include <Register/Amd/Cpuid.h>\r | |
15 | #include <Register/Intel/Msr.h>\r | |
16 | #include <Register/Intel/LocalApic.h>\r | |
17 | \r | |
18 | #include <Library/BaseLib.h>\r | |
19 | #include <Library/DebugLib.h>\r | |
20 | #include <Library/LocalApicLib.h>\r | |
21 | #include <Library/IoLib.h>\r | |
22 | #include <Library/TimerLib.h>\r | |
23 | #include <Library/PcdLib.h>\r | |
24 | #include <Library/CpuLib.h>\r | |
25 | #include <Library/UefiCpuLib.h>\r | |
26 | \r | |
27 | //\r | |
28 | // Library internal functions\r | |
29 | //\r | |
30 | \r | |
31 | /**\r | |
32 | Determine if the CPU supports the Local APIC Base Address MSR.\r | |
33 | \r | |
34 | @retval TRUE The CPU supports the Local APIC Base Address MSR.\r | |
35 | @retval FALSE The CPU does not support the Local APIC Base Address MSR.\r | |
36 | \r | |
37 | **/\r | |
38 | BOOLEAN\r | |
39 | LocalApicBaseAddressMsrSupported (\r | |
40 | VOID\r | |
41 | )\r | |
42 | {\r | |
43 | UINT32 RegEax;\r | |
44 | UINTN FamilyId;\r | |
45 | \r | |
46 | AsmCpuid (1, &RegEax, NULL, NULL, NULL);\r | |
47 | FamilyId = BitFieldRead32 (RegEax, 8, 11);\r | |
48 | if ((FamilyId == 0x04) || (FamilyId == 0x05)) {\r | |
49 | //\r | |
50 | // CPUs with a FamilyId of 0x04 or 0x05 do not support the\r | |
51 | // Local APIC Base Address MSR\r | |
52 | //\r | |
53 | return FALSE;\r | |
54 | }\r | |
55 | \r | |
56 | return TRUE;\r | |
57 | }\r | |
58 | \r | |
59 | /**\r | |
60 | Retrieve the base address of local APIC.\r | |
61 | \r | |
62 | @return The base address of local APIC.\r | |
63 | \r | |
64 | **/\r | |
65 | UINTN\r | |
66 | EFIAPI\r | |
67 | GetLocalApicBaseAddress (\r | |
68 | VOID\r | |
69 | )\r | |
70 | {\r | |
71 | MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r | |
72 | \r | |
73 | if (!LocalApicBaseAddressMsrSupported ()) {\r | |
74 | //\r | |
75 | // If CPU does not support Local APIC Base Address MSR, then retrieve\r | |
76 | // Local APIC Base Address from PCD\r | |
77 | //\r | |
78 | return PcdGet32 (PcdCpuLocalApicBaseAddress);\r | |
79 | }\r | |
80 | \r | |
81 | ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r | |
82 | \r | |
83 | return (UINTN)(LShiftU64 ((UINT64)ApicBaseMsr.Bits.ApicBaseHi, 32)) +\r | |
84 | (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);\r | |
85 | }\r | |
86 | \r | |
87 | /**\r | |
88 | Set the base address of local APIC.\r | |
89 | \r | |
90 | If BaseAddress is not aligned on a 4KB boundary, then ASSERT().\r | |
91 | \r | |
92 | @param[in] BaseAddress Local APIC base address to be set.\r | |
93 | \r | |
94 | **/\r | |
95 | VOID\r | |
96 | EFIAPI\r | |
97 | SetLocalApicBaseAddress (\r | |
98 | IN UINTN BaseAddress\r | |
99 | )\r | |
100 | {\r | |
101 | MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r | |
102 | \r | |
103 | ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);\r | |
104 | \r | |
105 | if (!LocalApicBaseAddressMsrSupported ()) {\r | |
106 | //\r | |
107 | // Ignore set request if the CPU does not support APIC Base Address MSR\r | |
108 | //\r | |
109 | return;\r | |
110 | }\r | |
111 | \r | |
112 | ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r | |
113 | \r | |
114 | ApicBaseMsr.Bits.ApicBase = (UINT32)(BaseAddress >> 12);\r | |
115 | ApicBaseMsr.Bits.ApicBaseHi = (UINT32)(RShiftU64 ((UINT64)BaseAddress, 32));\r | |
116 | \r | |
117 | AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r | |
118 | }\r | |
119 | \r | |
120 | /**\r | |
121 | Read from a local APIC register.\r | |
122 | \r | |
123 | This function reads from a local APIC register either in xAPIC or x2APIC mode.\r | |
124 | It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be\r | |
125 | accessed using multiple 32-bit loads or stores, so this function only performs\r | |
126 | 32-bit read.\r | |
127 | \r | |
128 | @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.\r | |
129 | It must be 16-byte aligned.\r | |
130 | \r | |
131 | @return 32-bit Value read from the register.\r | |
132 | **/\r | |
133 | UINT32\r | |
134 | EFIAPI\r | |
135 | ReadLocalApicReg (\r | |
136 | IN UINTN MmioOffset\r | |
137 | )\r | |
138 | {\r | |
139 | ASSERT ((MmioOffset & 0xf) == 0);\r | |
140 | ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r | |
141 | \r | |
142 | return MmioRead32 (GetLocalApicBaseAddress () + MmioOffset);\r | |
143 | }\r | |
144 | \r | |
145 | /**\r | |
146 | Write to a local APIC register.\r | |
147 | \r | |
148 | This function writes to a local APIC register either in xAPIC or x2APIC mode.\r | |
149 | It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be\r | |
150 | accessed using multiple 32-bit loads or stores, so this function only performs\r | |
151 | 32-bit write.\r | |
152 | \r | |
153 | if the register index is invalid or unsupported in current APIC mode, then ASSERT.\r | |
154 | \r | |
155 | @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.\r | |
156 | It must be 16-byte aligned.\r | |
157 | @param Value Value to be written to the register.\r | |
158 | **/\r | |
159 | VOID\r | |
160 | EFIAPI\r | |
161 | WriteLocalApicReg (\r | |
162 | IN UINTN MmioOffset,\r | |
163 | IN UINT32 Value\r | |
164 | )\r | |
165 | {\r | |
166 | ASSERT ((MmioOffset & 0xf) == 0);\r | |
167 | ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r | |
168 | \r | |
169 | MmioWrite32 (GetLocalApicBaseAddress () + MmioOffset, Value);\r | |
170 | }\r | |
171 | \r | |
172 | /**\r | |
173 | Send an IPI by writing to ICR.\r | |
174 | \r | |
175 | This function returns after the IPI has been accepted by the target processor.\r | |
176 | \r | |
177 | @param IcrLow 32-bit value to be written to the low half of ICR.\r | |
178 | @param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.\r | |
179 | **/\r | |
180 | VOID\r | |
181 | SendIpi (\r | |
182 | IN UINT32 IcrLow,\r | |
183 | IN UINT32 ApicId\r | |
184 | )\r | |
185 | {\r | |
186 | LOCAL_APIC_ICR_LOW IcrLowReg;\r | |
187 | UINT32 IcrHigh;\r | |
188 | BOOLEAN InterruptState;\r | |
189 | \r | |
190 | ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r | |
191 | ASSERT (ApicId <= 0xff);\r | |
192 | \r | |
193 | InterruptState = SaveAndDisableInterrupts ();\r | |
194 | \r | |
195 | //\r | |
196 | // Save existing contents of ICR high 32 bits\r | |
197 | //\r | |
198 | IcrHigh = ReadLocalApicReg (XAPIC_ICR_HIGH_OFFSET);\r | |
199 | \r | |
200 | //\r | |
201 | // Wait for DeliveryStatus clear in case a previous IPI\r | |
202 | // is still being sent\r | |
203 | //\r | |
204 | do {\r | |
205 | IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);\r | |
206 | } while (IcrLowReg.Bits.DeliveryStatus != 0);\r | |
207 | \r | |
208 | //\r | |
209 | // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.\r | |
210 | //\r | |
211 | WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, ApicId << 24);\r | |
212 | WriteLocalApicReg (XAPIC_ICR_LOW_OFFSET, IcrLow);\r | |
213 | \r | |
214 | //\r | |
215 | // Wait for DeliveryStatus clear again\r | |
216 | //\r | |
217 | do {\r | |
218 | IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);\r | |
219 | } while (IcrLowReg.Bits.DeliveryStatus != 0);\r | |
220 | \r | |
221 | //\r | |
222 | // And restore old contents of ICR high\r | |
223 | //\r | |
224 | WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, IcrHigh);\r | |
225 | \r | |
226 | SetInterruptState (InterruptState);\r | |
227 | }\r | |
228 | \r | |
229 | //\r | |
230 | // Library API implementation functions\r | |
231 | //\r | |
232 | \r | |
233 | /**\r | |
234 | Get the current local APIC mode.\r | |
235 | \r | |
236 | If local APIC is disabled, then ASSERT.\r | |
237 | \r | |
238 | @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.\r | |
239 | @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.\r | |
240 | **/\r | |
241 | UINTN\r | |
242 | EFIAPI\r | |
243 | GetApicMode (\r | |
244 | VOID\r | |
245 | )\r | |
246 | {\r | |
247 | DEBUG_CODE_BEGIN ();\r | |
248 | {\r | |
249 | MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r | |
250 | \r | |
251 | //\r | |
252 | // Check to see if the CPU supports the APIC Base Address MSR\r | |
253 | //\r | |
254 | if (LocalApicBaseAddressMsrSupported ()) {\r | |
255 | ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r | |
256 | //\r | |
257 | // Local APIC should have been enabled\r | |
258 | //\r | |
259 | ASSERT (ApicBaseMsr.Bits.EN != 0);\r | |
260 | ASSERT (ApicBaseMsr.Bits.EXTD == 0);\r | |
261 | }\r | |
262 | }\r | |
263 | DEBUG_CODE_END ();\r | |
264 | return LOCAL_APIC_MODE_XAPIC;\r | |
265 | }\r | |
266 | \r | |
267 | /**\r | |
268 | Set the current local APIC mode.\r | |
269 | \r | |
270 | If the specified local APIC mode is not valid, then ASSERT.\r | |
271 | If the specified local APIC mode can't be set as current, then ASSERT.\r | |
272 | \r | |
273 | @param ApicMode APIC mode to be set.\r | |
274 | \r | |
275 | @note This API must not be called from an interrupt handler or SMI handler.\r | |
276 | It may result in unpredictable behavior.\r | |
277 | **/\r | |
278 | VOID\r | |
279 | EFIAPI\r | |
280 | SetApicMode (\r | |
281 | IN UINTN ApicMode\r | |
282 | )\r | |
283 | {\r | |
284 | ASSERT (ApicMode == LOCAL_APIC_MODE_XAPIC);\r | |
285 | ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r | |
286 | }\r | |
287 | \r | |
288 | /**\r | |
289 | Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.\r | |
290 | \r | |
291 | In xAPIC mode, the initial local APIC ID may be different from current APIC ID.\r | |
292 | In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,\r | |
293 | the 32-bit local APIC ID is returned as initial APIC ID.\r | |
294 | \r | |
295 | @return 32-bit initial local APIC ID of the executing processor.\r | |
296 | **/\r | |
297 | UINT32\r | |
298 | EFIAPI\r | |
299 | GetInitialApicId (\r | |
300 | VOID\r | |
301 | )\r | |
302 | {\r | |
303 | UINT32 ApicId;\r | |
304 | UINT32 MaxCpuIdIndex;\r | |
305 | UINT32 RegEbx;\r | |
306 | \r | |
307 | ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r | |
308 | \r | |
309 | //\r | |
310 | // Get the max index of basic CPUID\r | |
311 | //\r | |
312 | AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);\r | |
313 | \r | |
314 | //\r | |
315 | // If CPUID Leaf B is supported,\r | |
316 | // And CPUID.0BH:EBX[15:0] reports a non-zero value,\r | |
317 | // Then the initial 32-bit APIC ID = CPUID.0BH:EDX\r | |
318 | // Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]\r | |
319 | //\r | |
320 | if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r | |
321 | AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, NULL, &RegEbx, NULL, &ApicId);\r | |
322 | if ((RegEbx & (BIT16 - 1)) != 0) {\r | |
323 | return ApicId;\r | |
324 | }\r | |
325 | }\r | |
326 | \r | |
327 | AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);\r | |
328 | return RegEbx >> 24;\r | |
329 | }\r | |
330 | \r | |
331 | /**\r | |
332 | Get the local APIC ID of the executing processor.\r | |
333 | \r | |
334 | @return 32-bit local APIC ID of the executing processor.\r | |
335 | **/\r | |
336 | UINT32\r | |
337 | EFIAPI\r | |
338 | GetApicId (\r | |
339 | VOID\r | |
340 | )\r | |
341 | {\r | |
342 | UINT32 ApicId;\r | |
343 | \r | |
344 | ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r | |
345 | \r | |
346 | if ((ApicId = GetInitialApicId ()) < 0x100) {\r | |
347 | //\r | |
348 | // If the initial local APIC ID is less 0x100, read APIC ID from\r | |
349 | // XAPIC_ID_OFFSET, otherwise return the initial local APIC ID.\r | |
350 | //\r | |
351 | ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);\r | |
352 | ApicId >>= 24;\r | |
353 | }\r | |
354 | \r | |
355 | return ApicId;\r | |
356 | }\r | |
357 | \r | |
358 | /**\r | |
359 | Get the value of the local APIC version register.\r | |
360 | \r | |
361 | @return the value of the local APIC version register.\r | |
362 | **/\r | |
363 | UINT32\r | |
364 | EFIAPI\r | |
365 | GetApicVersion (\r | |
366 | VOID\r | |
367 | )\r | |
368 | {\r | |
369 | return ReadLocalApicReg (XAPIC_VERSION_OFFSET);\r | |
370 | }\r | |
371 | \r | |
372 | /**\r | |
373 | Send a Fixed IPI to a specified target processor.\r | |
374 | \r | |
375 | This function returns after the IPI has been accepted by the target processor.\r | |
376 | \r | |
377 | @param ApicId The local APIC ID of the target processor.\r | |
378 | @param Vector The vector number of the interrupt being sent.\r | |
379 | **/\r | |
380 | VOID\r | |
381 | EFIAPI\r | |
382 | SendFixedIpi (\r | |
383 | IN UINT32 ApicId,\r | |
384 | IN UINT8 Vector\r | |
385 | )\r | |
386 | {\r | |
387 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
388 | \r | |
389 | IcrLow.Uint32 = 0;\r | |
390 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;\r | |
391 | IcrLow.Bits.Level = 1;\r | |
392 | IcrLow.Bits.Vector = Vector;\r | |
393 | SendIpi (IcrLow.Uint32, ApicId);\r | |
394 | }\r | |
395 | \r | |
396 | /**\r | |
397 | Send a Fixed IPI to all processors excluding self.\r | |
398 | \r | |
399 | This function returns after the IPI has been accepted by the target processors.\r | |
400 | \r | |
401 | @param Vector The vector number of the interrupt being sent.\r | |
402 | **/\r | |
403 | VOID\r | |
404 | EFIAPI\r | |
405 | SendFixedIpiAllExcludingSelf (\r | |
406 | IN UINT8 Vector\r | |
407 | )\r | |
408 | {\r | |
409 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
410 | \r | |
411 | IcrLow.Uint32 = 0;\r | |
412 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;\r | |
413 | IcrLow.Bits.Level = 1;\r | |
414 | IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r | |
415 | IcrLow.Bits.Vector = Vector;\r | |
416 | SendIpi (IcrLow.Uint32, 0);\r | |
417 | }\r | |
418 | \r | |
419 | /**\r | |
420 | Send a SMI IPI to a specified target processor.\r | |
421 | \r | |
422 | This function returns after the IPI has been accepted by the target processor.\r | |
423 | \r | |
424 | @param ApicId Specify the local APIC ID of the target processor.\r | |
425 | **/\r | |
426 | VOID\r | |
427 | EFIAPI\r | |
428 | SendSmiIpi (\r | |
429 | IN UINT32 ApicId\r | |
430 | )\r | |
431 | {\r | |
432 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
433 | \r | |
434 | IcrLow.Uint32 = 0;\r | |
435 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;\r | |
436 | IcrLow.Bits.Level = 1;\r | |
437 | SendIpi (IcrLow.Uint32, ApicId);\r | |
438 | }\r | |
439 | \r | |
440 | /**\r | |
441 | Send a SMI IPI to all processors excluding self.\r | |
442 | \r | |
443 | This function returns after the IPI has been accepted by the target processors.\r | |
444 | **/\r | |
445 | VOID\r | |
446 | EFIAPI\r | |
447 | SendSmiIpiAllExcludingSelf (\r | |
448 | VOID\r | |
449 | )\r | |
450 | {\r | |
451 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
452 | \r | |
453 | IcrLow.Uint32 = 0;\r | |
454 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;\r | |
455 | IcrLow.Bits.Level = 1;\r | |
456 | IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r | |
457 | SendIpi (IcrLow.Uint32, 0);\r | |
458 | }\r | |
459 | \r | |
460 | /**\r | |
461 | Send an INIT IPI to a specified target processor.\r | |
462 | \r | |
463 | This function returns after the IPI has been accepted by the target processor.\r | |
464 | \r | |
465 | @param ApicId Specify the local APIC ID of the target processor.\r | |
466 | **/\r | |
467 | VOID\r | |
468 | EFIAPI\r | |
469 | SendInitIpi (\r | |
470 | IN UINT32 ApicId\r | |
471 | )\r | |
472 | {\r | |
473 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
474 | \r | |
475 | IcrLow.Uint32 = 0;\r | |
476 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;\r | |
477 | IcrLow.Bits.Level = 1;\r | |
478 | SendIpi (IcrLow.Uint32, ApicId);\r | |
479 | }\r | |
480 | \r | |
481 | /**\r | |
482 | Send an INIT IPI to all processors excluding self.\r | |
483 | \r | |
484 | This function returns after the IPI has been accepted by the target processors.\r | |
485 | **/\r | |
486 | VOID\r | |
487 | EFIAPI\r | |
488 | SendInitIpiAllExcludingSelf (\r | |
489 | VOID\r | |
490 | )\r | |
491 | {\r | |
492 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
493 | \r | |
494 | IcrLow.Uint32 = 0;\r | |
495 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;\r | |
496 | IcrLow.Bits.Level = 1;\r | |
497 | IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r | |
498 | SendIpi (IcrLow.Uint32, 0);\r | |
499 | }\r | |
500 | \r | |
501 | /**\r | |
502 | Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.\r | |
503 | \r | |
504 | This function returns after the IPI has been accepted by the target processor.\r | |
505 | \r | |
506 | if StartupRoutine >= 1M, then ASSERT.\r | |
507 | if StartupRoutine is not multiple of 4K, then ASSERT.\r | |
508 | \r | |
509 | @param ApicId Specify the local APIC ID of the target processor.\r | |
510 | @param StartupRoutine Points to a start-up routine which is below 1M physical\r | |
511 | address and 4K aligned.\r | |
512 | **/\r | |
513 | VOID\r | |
514 | EFIAPI\r | |
515 | SendInitSipiSipi (\r | |
516 | IN UINT32 ApicId,\r | |
517 | IN UINT32 StartupRoutine\r | |
518 | )\r | |
519 | {\r | |
520 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
521 | \r | |
522 | ASSERT (StartupRoutine < 0x100000);\r | |
523 | ASSERT ((StartupRoutine & 0xfff) == 0);\r | |
524 | \r | |
525 | SendInitIpi (ApicId);\r | |
526 | MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));\r | |
527 | IcrLow.Uint32 = 0;\r | |
528 | IcrLow.Bits.Vector = (StartupRoutine >> 12);\r | |
529 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r | |
530 | IcrLow.Bits.Level = 1;\r | |
531 | SendIpi (IcrLow.Uint32, ApicId);\r | |
532 | if (!StandardSignatureIsAuthenticAMD ()) {\r | |
533 | MicroSecondDelay (200);\r | |
534 | SendIpi (IcrLow.Uint32, ApicId);\r | |
535 | }\r | |
536 | }\r | |
537 | \r | |
538 | /**\r | |
539 | Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.\r | |
540 | \r | |
541 | This function returns after the IPI has been accepted by the target processors.\r | |
542 | \r | |
543 | if StartupRoutine >= 1M, then ASSERT.\r | |
544 | if StartupRoutine is not multiple of 4K, then ASSERT.\r | |
545 | \r | |
546 | @param StartupRoutine Points to a start-up routine which is below 1M physical\r | |
547 | address and 4K aligned.\r | |
548 | **/\r | |
549 | VOID\r | |
550 | EFIAPI\r | |
551 | SendInitSipiSipiAllExcludingSelf (\r | |
552 | IN UINT32 StartupRoutine\r | |
553 | )\r | |
554 | {\r | |
555 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
556 | \r | |
557 | ASSERT (StartupRoutine < 0x100000);\r | |
558 | ASSERT ((StartupRoutine & 0xfff) == 0);\r | |
559 | \r | |
560 | SendInitIpiAllExcludingSelf ();\r | |
561 | MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));\r | |
562 | IcrLow.Uint32 = 0;\r | |
563 | IcrLow.Bits.Vector = (StartupRoutine >> 12);\r | |
564 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r | |
565 | IcrLow.Bits.Level = 1;\r | |
566 | IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r | |
567 | SendIpi (IcrLow.Uint32, 0);\r | |
568 | if (!StandardSignatureIsAuthenticAMD ()) {\r | |
569 | MicroSecondDelay (200);\r | |
570 | SendIpi (IcrLow.Uint32, 0);\r | |
571 | }\r | |
572 | }\r | |
573 | \r | |
574 | /**\r | |
575 | Initialize the state of the SoftwareEnable bit in the Local APIC\r | |
576 | Spurious Interrupt Vector register.\r | |
577 | \r | |
578 | @param Enable If TRUE, then set SoftwareEnable to 1\r | |
579 | If FALSE, then set SoftwareEnable to 0.\r | |
580 | \r | |
581 | **/\r | |
582 | VOID\r | |
583 | EFIAPI\r | |
584 | InitializeLocalApicSoftwareEnable (\r | |
585 | IN BOOLEAN Enable\r | |
586 | )\r | |
587 | {\r | |
588 | LOCAL_APIC_SVR Svr;\r | |
589 | \r | |
590 | //\r | |
591 | // Set local APIC software-enabled bit.\r | |
592 | //\r | |
593 | Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r | |
594 | if (Enable) {\r | |
595 | if (Svr.Bits.SoftwareEnable == 0) {\r | |
596 | Svr.Bits.SoftwareEnable = 1;\r | |
597 | WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r | |
598 | }\r | |
599 | } else {\r | |
600 | if (Svr.Bits.SoftwareEnable == 1) {\r | |
601 | Svr.Bits.SoftwareEnable = 0;\r | |
602 | WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r | |
603 | }\r | |
604 | }\r | |
605 | }\r | |
606 | \r | |
607 | /**\r | |
608 | Programming Virtual Wire Mode.\r | |
609 | \r | |
610 | This function programs the local APIC for virtual wire mode following\r | |
611 | the example described in chapter A.3 of the MP 1.4 spec.\r | |
612 | \r | |
613 | IOxAPIC is not involved in this type of virtual wire mode.\r | |
614 | **/\r | |
615 | VOID\r | |
616 | EFIAPI\r | |
617 | ProgramVirtualWireMode (\r | |
618 | VOID\r | |
619 | )\r | |
620 | {\r | |
621 | LOCAL_APIC_SVR Svr;\r | |
622 | LOCAL_APIC_LVT_LINT Lint;\r | |
623 | \r | |
624 | //\r | |
625 | // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.\r | |
626 | //\r | |
627 | Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r | |
628 | Svr.Bits.SpuriousVector = 0xf;\r | |
629 | Svr.Bits.SoftwareEnable = 1;\r | |
630 | WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r | |
631 | \r | |
632 | //\r | |
633 | // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.\r | |
634 | //\r | |
635 | Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r | |
636 | Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;\r | |
637 | Lint.Bits.InputPinPolarity = 0;\r | |
638 | Lint.Bits.TriggerMode = 0;\r | |
639 | Lint.Bits.Mask = 0;\r | |
640 | WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);\r | |
641 | \r | |
642 | //\r | |
643 | // Program the LINT0 vector entry as NMI. Not masked, edge, active high.\r | |
644 | //\r | |
645 | Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r | |
646 | Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;\r | |
647 | Lint.Bits.InputPinPolarity = 0;\r | |
648 | Lint.Bits.TriggerMode = 0;\r | |
649 | Lint.Bits.Mask = 0;\r | |
650 | WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);\r | |
651 | }\r | |
652 | \r | |
653 | /**\r | |
654 | Disable LINT0 & LINT1 interrupts.\r | |
655 | \r | |
656 | This function sets the mask flag in the LVT LINT0 & LINT1 registers.\r | |
657 | **/\r | |
658 | VOID\r | |
659 | EFIAPI\r | |
660 | DisableLvtInterrupts (\r | |
661 | VOID\r | |
662 | )\r | |
663 | {\r | |
664 | LOCAL_APIC_LVT_LINT LvtLint;\r | |
665 | \r | |
666 | LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r | |
667 | LvtLint.Bits.Mask = 1;\r | |
668 | WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);\r | |
669 | \r | |
670 | LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r | |
671 | LvtLint.Bits.Mask = 1;\r | |
672 | WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);\r | |
673 | }\r | |
674 | \r | |
675 | /**\r | |
676 | Read the initial count value from the init-count register.\r | |
677 | \r | |
678 | @return The initial count value read from the init-count register.\r | |
679 | **/\r | |
680 | UINT32\r | |
681 | EFIAPI\r | |
682 | GetApicTimerInitCount (\r | |
683 | VOID\r | |
684 | )\r | |
685 | {\r | |
686 | return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET);\r | |
687 | }\r | |
688 | \r | |
689 | /**\r | |
690 | Read the current count value from the current-count register.\r | |
691 | \r | |
692 | @return The current count value read from the current-count register.\r | |
693 | **/\r | |
694 | UINT32\r | |
695 | EFIAPI\r | |
696 | GetApicTimerCurrentCount (\r | |
697 | VOID\r | |
698 | )\r | |
699 | {\r | |
700 | return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET);\r | |
701 | }\r | |
702 | \r | |
703 | /**\r | |
704 | Initialize the local APIC timer.\r | |
705 | \r | |
706 | The local APIC timer is initialized and enabled.\r | |
707 | \r | |
708 | @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r | |
709 | If it is 0, then use the current divide value in the DCR.\r | |
710 | @param InitCount The initial count value.\r | |
711 | @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r | |
712 | @param Vector The timer interrupt vector number.\r | |
713 | **/\r | |
714 | VOID\r | |
715 | EFIAPI\r | |
716 | InitializeApicTimer (\r | |
717 | IN UINTN DivideValue,\r | |
718 | IN UINT32 InitCount,\r | |
719 | IN BOOLEAN PeriodicMode,\r | |
720 | IN UINT8 Vector\r | |
721 | )\r | |
722 | {\r | |
723 | LOCAL_APIC_DCR Dcr;\r | |
724 | LOCAL_APIC_LVT_TIMER LvtTimer;\r | |
725 | UINT32 Divisor;\r | |
726 | \r | |
727 | //\r | |
728 | // Ensure local APIC is in software-enabled state.\r | |
729 | //\r | |
730 | InitializeLocalApicSoftwareEnable (TRUE);\r | |
731 | \r | |
732 | //\r | |
733 | // Program init-count register.\r | |
734 | //\r | |
735 | WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount);\r | |
736 | \r | |
737 | if (DivideValue != 0) {\r | |
738 | ASSERT (DivideValue <= 128);\r | |
739 | ASSERT (DivideValue == GetPowerOfTwo32 ((UINT32)DivideValue));\r | |
740 | Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);\r | |
741 | \r | |
742 | Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r | |
743 | Dcr.Bits.DivideValue1 = (Divisor & 0x3);\r | |
744 | Dcr.Bits.DivideValue2 = (Divisor >> 2);\r | |
745 | WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);\r | |
746 | }\r | |
747 | \r | |
748 | //\r | |
749 | // Enable APIC timer interrupt with specified timer mode.\r | |
750 | //\r | |
751 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r | |
752 | if (PeriodicMode) {\r | |
753 | LvtTimer.Bits.TimerMode = 1;\r | |
754 | } else {\r | |
755 | LvtTimer.Bits.TimerMode = 0;\r | |
756 | }\r | |
757 | \r | |
758 | LvtTimer.Bits.Mask = 0;\r | |
759 | LvtTimer.Bits.Vector = Vector;\r | |
760 | WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r | |
761 | }\r | |
762 | \r | |
763 | /**\r | |
764 | Get the state of the local APIC timer.\r | |
765 | \r | |
766 | This function will ASSERT if the local APIC is not software enabled.\r | |
767 | \r | |
768 | @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r | |
769 | @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r | |
770 | @param Vector Return the timer interrupt vector number.\r | |
771 | **/\r | |
772 | VOID\r | |
773 | EFIAPI\r | |
774 | GetApicTimerState (\r | |
775 | OUT UINTN *DivideValue OPTIONAL,\r | |
776 | OUT BOOLEAN *PeriodicMode OPTIONAL,\r | |
777 | OUT UINT8 *Vector OPTIONAL\r | |
778 | )\r | |
779 | {\r | |
780 | UINT32 Divisor;\r | |
781 | LOCAL_APIC_DCR Dcr;\r | |
782 | LOCAL_APIC_LVT_TIMER LvtTimer;\r | |
783 | \r | |
784 | //\r | |
785 | // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt\r | |
786 | // Vector Register.\r | |
787 | // This bit will be 1, if local APIC is software enabled.\r | |
788 | //\r | |
789 | ASSERT ((ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);\r | |
790 | \r | |
791 | if (DivideValue != NULL) {\r | |
792 | Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r | |
793 | Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);\r | |
794 | Divisor = (Divisor + 1) & 0x7;\r | |
795 | *DivideValue = ((UINTN)1) << Divisor;\r | |
796 | }\r | |
797 | \r | |
798 | if ((PeriodicMode != NULL) || (Vector != NULL)) {\r | |
799 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r | |
800 | if (PeriodicMode != NULL) {\r | |
801 | if (LvtTimer.Bits.TimerMode == 1) {\r | |
802 | *PeriodicMode = TRUE;\r | |
803 | } else {\r | |
804 | *PeriodicMode = FALSE;\r | |
805 | }\r | |
806 | }\r | |
807 | \r | |
808 | if (Vector != NULL) {\r | |
809 | *Vector = (UINT8)LvtTimer.Bits.Vector;\r | |
810 | }\r | |
811 | }\r | |
812 | }\r | |
813 | \r | |
814 | /**\r | |
815 | Enable the local APIC timer interrupt.\r | |
816 | **/\r | |
817 | VOID\r | |
818 | EFIAPI\r | |
819 | EnableApicTimerInterrupt (\r | |
820 | VOID\r | |
821 | )\r | |
822 | {\r | |
823 | LOCAL_APIC_LVT_TIMER LvtTimer;\r | |
824 | \r | |
825 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r | |
826 | LvtTimer.Bits.Mask = 0;\r | |
827 | WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r | |
828 | }\r | |
829 | \r | |
830 | /**\r | |
831 | Disable the local APIC timer interrupt.\r | |
832 | **/\r | |
833 | VOID\r | |
834 | EFIAPI\r | |
835 | DisableApicTimerInterrupt (\r | |
836 | VOID\r | |
837 | )\r | |
838 | {\r | |
839 | LOCAL_APIC_LVT_TIMER LvtTimer;\r | |
840 | \r | |
841 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r | |
842 | LvtTimer.Bits.Mask = 1;\r | |
843 | WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r | |
844 | }\r | |
845 | \r | |
846 | /**\r | |
847 | Get the local APIC timer interrupt state.\r | |
848 | \r | |
849 | @retval TRUE The local APIC timer interrupt is enabled.\r | |
850 | @retval FALSE The local APIC timer interrupt is disabled.\r | |
851 | **/\r | |
852 | BOOLEAN\r | |
853 | EFIAPI\r | |
854 | GetApicTimerInterruptState (\r | |
855 | VOID\r | |
856 | )\r | |
857 | {\r | |
858 | LOCAL_APIC_LVT_TIMER LvtTimer;\r | |
859 | \r | |
860 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r | |
861 | return (BOOLEAN)(LvtTimer.Bits.Mask == 0);\r | |
862 | }\r | |
863 | \r | |
864 | /**\r | |
865 | Send EOI to the local APIC.\r | |
866 | **/\r | |
867 | VOID\r | |
868 | EFIAPI\r | |
869 | SendApicEoi (\r | |
870 | VOID\r | |
871 | )\r | |
872 | {\r | |
873 | WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);\r | |
874 | }\r | |
875 | \r | |
876 | /**\r | |
877 | Get the 32-bit address that a device should use to send a Message Signaled\r | |
878 | Interrupt (MSI) to the Local APIC of the currently executing processor.\r | |
879 | \r | |
880 | @return 32-bit address used to send an MSI to the Local APIC.\r | |
881 | **/\r | |
882 | UINT32\r | |
883 | EFIAPI\r | |
884 | GetApicMsiAddress (\r | |
885 | VOID\r | |
886 | )\r | |
887 | {\r | |
888 | LOCAL_APIC_MSI_ADDRESS MsiAddress;\r | |
889 | \r | |
890 | //\r | |
891 | // Return address for an MSI interrupt to be delivered only to the APIC ID\r | |
892 | // of the currently executing processor.\r | |
893 | //\r | |
894 | MsiAddress.Uint32 = 0;\r | |
895 | MsiAddress.Bits.BaseAddress = 0xFEE;\r | |
896 | MsiAddress.Bits.DestinationId = GetApicId ();\r | |
897 | return MsiAddress.Uint32;\r | |
898 | }\r | |
899 | \r | |
900 | /**\r | |
901 | Get the 64-bit data value that a device should use to send a Message Signaled\r | |
902 | Interrupt (MSI) to the Local APIC of the currently executing processor.\r | |
903 | \r | |
904 | If Vector is not in range 0x10..0xFE, then ASSERT().\r | |
905 | If DeliveryMode is not supported, then ASSERT().\r | |
906 | \r | |
907 | @param Vector The 8-bit interrupt vector associated with the MSI.\r | |
908 | Must be in the range 0x10..0xFE\r | |
909 | @param DeliveryMode A 3-bit value that specifies how the recept of the MSI\r | |
910 | is handled. The only supported values are:\r | |
911 | 0: LOCAL_APIC_DELIVERY_MODE_FIXED\r | |
912 | 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r | |
913 | 2: LOCAL_APIC_DELIVERY_MODE_SMI\r | |
914 | 4: LOCAL_APIC_DELIVERY_MODE_NMI\r | |
915 | 5: LOCAL_APIC_DELIVERY_MODE_INIT\r | |
916 | 7: LOCAL_APIC_DELIVERY_MODE_EXTINT\r | |
917 | \r | |
918 | @param LevelTriggered TRUE specifies a level triggered interrupt.\r | |
919 | FALSE specifies an edge triggered interrupt.\r | |
920 | @param AssertionLevel Ignored if LevelTriggered is FALSE.\r | |
921 | TRUE specifies a level triggered interrupt that active\r | |
922 | when the interrupt line is asserted.\r | |
923 | FALSE specifies a level triggered interrupt that active\r | |
924 | when the interrupt line is deasserted.\r | |
925 | \r | |
926 | @return 64-bit data value used to send an MSI to the Local APIC.\r | |
927 | **/\r | |
928 | UINT64\r | |
929 | EFIAPI\r | |
930 | GetApicMsiValue (\r | |
931 | IN UINT8 Vector,\r | |
932 | IN UINTN DeliveryMode,\r | |
933 | IN BOOLEAN LevelTriggered,\r | |
934 | IN BOOLEAN AssertionLevel\r | |
935 | )\r | |
936 | {\r | |
937 | LOCAL_APIC_MSI_DATA MsiData;\r | |
938 | \r | |
939 | ASSERT (Vector >= 0x10 && Vector <= 0xFE);\r | |
940 | ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);\r | |
941 | \r | |
942 | MsiData.Uint64 = 0;\r | |
943 | MsiData.Bits.Vector = Vector;\r | |
944 | MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;\r | |
945 | if (LevelTriggered) {\r | |
946 | MsiData.Bits.TriggerMode = 1;\r | |
947 | if (AssertionLevel) {\r | |
948 | MsiData.Bits.Level = 1;\r | |
949 | }\r | |
950 | }\r | |
951 | \r | |
952 | return MsiData.Uint64;\r | |
953 | }\r | |
954 | \r | |
955 | /**\r | |
956 | Get Package ID/Core ID/Thread ID of a processor.\r | |
957 | \r | |
958 | The algorithm assumes the target system has symmetry across physical\r | |
959 | package boundaries with respect to the number of logical processors\r | |
960 | per package, number of cores per package.\r | |
961 | \r | |
962 | @param[in] InitialApicId Initial APIC ID of the target logical processor.\r | |
963 | @param[out] Package Returns the processor package ID.\r | |
964 | @param[out] Core Returns the processor core ID.\r | |
965 | @param[out] Thread Returns the processor thread ID.\r | |
966 | **/\r | |
967 | VOID\r | |
968 | EFIAPI\r | |
969 | GetProcessorLocationByApicId (\r | |
970 | IN UINT32 InitialApicId,\r | |
971 | OUT UINT32 *Package OPTIONAL,\r | |
972 | OUT UINT32 *Core OPTIONAL,\r | |
973 | OUT UINT32 *Thread OPTIONAL\r | |
974 | )\r | |
975 | {\r | |
976 | BOOLEAN TopologyLeafSupported;\r | |
977 | CPUID_VERSION_INFO_EBX VersionInfoEbx;\r | |
978 | CPUID_VERSION_INFO_EDX VersionInfoEdx;\r | |
979 | CPUID_CACHE_PARAMS_EAX CacheParamsEax;\r | |
980 | CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;\r | |
981 | CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;\r | |
982 | CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;\r | |
983 | CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;\r | |
984 | CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;\r | |
985 | CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;\r | |
986 | UINT32 MaxStandardCpuIdIndex;\r | |
987 | UINT32 MaxExtendedCpuIdIndex;\r | |
988 | UINT32 SubIndex;\r | |
989 | UINTN LevelType;\r | |
990 | UINT32 MaxLogicProcessorsPerPackage;\r | |
991 | UINT32 MaxCoresPerPackage;\r | |
992 | UINTN ThreadBits;\r | |
993 | UINTN CoreBits;\r | |
994 | \r | |
995 | //\r | |
996 | // Check if the processor is capable of supporting more than one logical processor.\r | |
997 | //\r | |
998 | AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);\r | |
999 | if (VersionInfoEdx.Bits.HTT == 0) {\r | |
1000 | if (Thread != NULL) {\r | |
1001 | *Thread = 0;\r | |
1002 | }\r | |
1003 | \r | |
1004 | if (Core != NULL) {\r | |
1005 | *Core = 0;\r | |
1006 | }\r | |
1007 | \r | |
1008 | if (Package != NULL) {\r | |
1009 | *Package = 0;\r | |
1010 | }\r | |
1011 | \r | |
1012 | return;\r | |
1013 | }\r | |
1014 | \r | |
1015 | //\r | |
1016 | // Assume three-level mapping of APIC ID: Package|Core|Thread.\r | |
1017 | //\r | |
1018 | ThreadBits = 0;\r | |
1019 | CoreBits = 0;\r | |
1020 | \r | |
1021 | //\r | |
1022 | // Get max index of CPUID\r | |
1023 | //\r | |
1024 | AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);\r | |
1025 | AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);\r | |
1026 | \r | |
1027 | //\r | |
1028 | // If the extended topology enumeration leaf is available, it\r | |
1029 | // is the preferred mechanism for enumerating topology.\r | |
1030 | //\r | |
1031 | TopologyLeafSupported = FALSE;\r | |
1032 | if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r | |
1033 | AsmCpuidEx (\r | |
1034 | CPUID_EXTENDED_TOPOLOGY,\r | |
1035 | 0,\r | |
1036 | &ExtendedTopologyEax.Uint32,\r | |
1037 | &ExtendedTopologyEbx.Uint32,\r | |
1038 | &ExtendedTopologyEcx.Uint32,\r | |
1039 | NULL\r | |
1040 | );\r | |
1041 | //\r | |
1042 | // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for\r | |
1043 | // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not\r | |
1044 | // supported on that processor.\r | |
1045 | //\r | |
1046 | if (ExtendedTopologyEbx.Uint32 != 0) {\r | |
1047 | TopologyLeafSupported = TRUE;\r | |
1048 | \r | |
1049 | //\r | |
1050 | // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract\r | |
1051 | // the SMT sub-field of x2APIC ID.\r | |
1052 | //\r | |
1053 | LevelType = ExtendedTopologyEcx.Bits.LevelType;\r | |
1054 | ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);\r | |
1055 | ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;\r | |
1056 | \r | |
1057 | //\r | |
1058 | // Software must not assume any "level type" encoding\r | |
1059 | // value to be related to any sub-leaf index, except sub-leaf 0.\r | |
1060 | //\r | |
1061 | SubIndex = 1;\r | |
1062 | do {\r | |
1063 | AsmCpuidEx (\r | |
1064 | CPUID_EXTENDED_TOPOLOGY,\r | |
1065 | SubIndex,\r | |
1066 | &ExtendedTopologyEax.Uint32,\r | |
1067 | NULL,\r | |
1068 | &ExtendedTopologyEcx.Uint32,\r | |
1069 | NULL\r | |
1070 | );\r | |
1071 | LevelType = ExtendedTopologyEcx.Bits.LevelType;\r | |
1072 | if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {\r | |
1073 | CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;\r | |
1074 | break;\r | |
1075 | }\r | |
1076 | \r | |
1077 | SubIndex++;\r | |
1078 | } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);\r | |
1079 | }\r | |
1080 | }\r | |
1081 | \r | |
1082 | if (!TopologyLeafSupported) {\r | |
1083 | //\r | |
1084 | // Get logical processor count\r | |
1085 | //\r | |
1086 | AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);\r | |
1087 | MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;\r | |
1088 | \r | |
1089 | //\r | |
1090 | // Assume single-core processor\r | |
1091 | //\r | |
1092 | MaxCoresPerPackage = 1;\r | |
1093 | \r | |
1094 | //\r | |
1095 | // Check for topology extensions on AMD processor\r | |
1096 | //\r | |
1097 | if (StandardSignatureIsAuthenticAMD ()) {\r | |
1098 | if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {\r | |
1099 | AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);\r | |
1100 | if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {\r | |
1101 | //\r | |
1102 | // Account for max possible thread count to decode ApicId\r | |
1103 | //\r | |
1104 | AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);\r | |
1105 | MaxLogicProcessorsPerPackage = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;\r | |
1106 | \r | |
1107 | //\r | |
1108 | // Get cores per processor package\r | |
1109 | //\r | |
1110 | AsmCpuid (CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32, NULL, NULL);\r | |
1111 | MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);\r | |
1112 | }\r | |
1113 | }\r | |
1114 | } else {\r | |
1115 | //\r | |
1116 | // Extract core count based on CACHE information\r | |
1117 | //\r | |
1118 | if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {\r | |
1119 | AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);\r | |
1120 | if (CacheParamsEax.Uint32 != 0) {\r | |
1121 | MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;\r | |
1122 | }\r | |
1123 | }\r | |
1124 | }\r | |
1125 | \r | |
1126 | ThreadBits = (UINTN)(HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);\r | |
1127 | CoreBits = (UINTN)(HighBitSet32 (MaxCoresPerPackage - 1) + 1);\r | |
1128 | }\r | |
1129 | \r | |
1130 | if (Thread != NULL) {\r | |
1131 | *Thread = InitialApicId & ((1 << ThreadBits) - 1);\r | |
1132 | }\r | |
1133 | \r | |
1134 | if (Core != NULL) {\r | |
1135 | *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);\r | |
1136 | }\r | |
1137 | \r | |
1138 | if (Package != NULL) {\r | |
1139 | *Package = (InitialApicId >> (ThreadBits + CoreBits));\r | |
1140 | }\r | |
1141 | }\r | |
1142 | \r | |
1143 | /**\r | |
1144 | Get Package ID/Die ID/Tile ID/Module ID/Core ID/Thread ID of a processor.\r | |
1145 | \r | |
1146 | The algorithm assumes the target system has symmetry across physical\r | |
1147 | package boundaries with respect to the number of threads per core, number of\r | |
1148 | cores per module, number of modules per tile, number of tiles per die, number\r | |
1149 | of dies per package.\r | |
1150 | \r | |
1151 | @param[in] InitialApicId Initial APIC ID of the target logical processor.\r | |
1152 | @param[out] Package Returns the processor package ID.\r | |
1153 | @param[out] Die Returns the processor die ID.\r | |
1154 | @param[out] Tile Returns the processor tile ID.\r | |
1155 | @param[out] Module Returns the processor module ID.\r | |
1156 | @param[out] Core Returns the processor core ID.\r | |
1157 | @param[out] Thread Returns the processor thread ID.\r | |
1158 | **/\r | |
1159 | VOID\r | |
1160 | EFIAPI\r | |
1161 | GetProcessorLocation2ByApicId (\r | |
1162 | IN UINT32 InitialApicId,\r | |
1163 | OUT UINT32 *Package OPTIONAL,\r | |
1164 | OUT UINT32 *Die OPTIONAL,\r | |
1165 | OUT UINT32 *Tile OPTIONAL,\r | |
1166 | OUT UINT32 *Module OPTIONAL,\r | |
1167 | OUT UINT32 *Core OPTIONAL,\r | |
1168 | OUT UINT32 *Thread OPTIONAL\r | |
1169 | )\r | |
1170 | {\r | |
1171 | CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;\r | |
1172 | CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;\r | |
1173 | UINT32 MaxStandardCpuIdIndex;\r | |
1174 | UINT32 Index;\r | |
1175 | UINTN LevelType;\r | |
1176 | UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];\r | |
1177 | UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];\r | |
1178 | \r | |
1179 | for (LevelType = 0; LevelType < ARRAY_SIZE (Bits); LevelType++) {\r | |
1180 | Bits[LevelType] = 0;\r | |
1181 | }\r | |
1182 | \r | |
1183 | //\r | |
1184 | // Get max index of CPUID\r | |
1185 | //\r | |
1186 | AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);\r | |
1187 | if (MaxStandardCpuIdIndex < CPUID_V2_EXTENDED_TOPOLOGY) {\r | |
1188 | if (Die != NULL) {\r | |
1189 | *Die = 0;\r | |
1190 | }\r | |
1191 | \r | |
1192 | if (Tile != NULL) {\r | |
1193 | *Tile = 0;\r | |
1194 | }\r | |
1195 | \r | |
1196 | if (Module != NULL) {\r | |
1197 | *Module = 0;\r | |
1198 | }\r | |
1199 | \r | |
1200 | GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread);\r | |
1201 | return;\r | |
1202 | }\r | |
1203 | \r | |
1204 | //\r | |
1205 | // If the V2 extended topology enumeration leaf is available, it\r | |
1206 | // is the preferred mechanism for enumerating topology.\r | |
1207 | //\r | |
1208 | for (Index = 0; ; Index++) {\r | |
1209 | AsmCpuidEx (\r | |
1210 | CPUID_V2_EXTENDED_TOPOLOGY,\r | |
1211 | Index,\r | |
1212 | &ExtendedTopologyEax.Uint32,\r | |
1213 | NULL,\r | |
1214 | &ExtendedTopologyEcx.Uint32,\r | |
1215 | NULL\r | |
1216 | );\r | |
1217 | \r | |
1218 | LevelType = ExtendedTopologyEcx.Bits.LevelType;\r | |
1219 | \r | |
1220 | //\r | |
1221 | // first level reported should be SMT.\r | |
1222 | //\r | |
1223 | ASSERT ((Index != 0) || (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT));\r | |
1224 | if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {\r | |
1225 | break;\r | |
1226 | }\r | |
1227 | \r | |
1228 | ASSERT (LevelType < ARRAY_SIZE (Bits));\r | |
1229 | Bits[LevelType] = ExtendedTopologyEax.Bits.ApicIdShift;\r | |
1230 | }\r | |
1231 | \r | |
1232 | for (LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE; LevelType < ARRAY_SIZE (Bits); LevelType++) {\r | |
1233 | //\r | |
1234 | // If there are more levels between level-1 (low-level) and level-2 (high-level), the unknown levels will be ignored\r | |
1235 | // and treated as an extension of the last known level (i.e., level-1 in this case).\r | |
1236 | //\r | |
1237 | if (Bits[LevelType] == 0) {\r | |
1238 | Bits[LevelType] = Bits[LevelType - 1];\r | |
1239 | }\r | |
1240 | }\r | |
1241 | \r | |
1242 | Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = Package;\r | |
1243 | Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE] = Die;\r | |
1244 | Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE] = Tile;\r | |
1245 | Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE] = Module;\r | |
1246 | Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE] = Core;\r | |
1247 | Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT] = Thread;\r | |
1248 | \r | |
1249 | Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = 32;\r | |
1250 | \r | |
1251 | for ( LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT\r | |
1252 | ; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1\r | |
1253 | ; LevelType++\r | |
1254 | )\r | |
1255 | {\r | |
1256 | if (Location[LevelType] != NULL) {\r | |
1257 | //\r | |
1258 | // Bits[i] holds the number of bits to shift right on x2APIC ID to get a unique\r | |
1259 | // topology ID of the next level type.\r | |
1260 | //\r | |
1261 | *Location[LevelType] = InitialApicId >> Bits[LevelType - 1];\r | |
1262 | \r | |
1263 | //\r | |
1264 | // Bits[i] - Bits[i-1] holds the number of bits for the next ONE level type.\r | |
1265 | //\r | |
1266 | *Location[LevelType] &= (1 << (Bits[LevelType] - Bits[LevelType - 1])) - 1;\r | |
1267 | }\r | |
1268 | }\r | |
1269 | }\r |