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1/** @file\r
2Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.\r
3\r
4Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
5Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
6\r
7This program and the accompanying materials\r
8are licensed and made available under the terms and conditions of the BSD License\r
9which accompanies this distribution. The full text of the license may be found at\r
10http://opensource.org/licenses/bsd-license.php\r
11\r
12THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14\r
15**/\r
16\r
17#ifndef _CPU_PISMMCPUDXESMM_H_\r
18#define _CPU_PISMMCPUDXESMM_H_\r
19\r
20#include <PiSmm.h>\r
21\r
22#include <Protocol/MpService.h>\r
23#include <Protocol/SmmConfiguration.h>\r
24#include <Protocol/SmmCpu.h>\r
25#include <Protocol/SmmAccess2.h>\r
26#include <Protocol/SmmReadyToLock.h>\r
27#include <Protocol/SmmCpuService.h>\r
28#include <Protocol/SmmMemoryAttribute.h>\r
29\r
30#include <Guid/AcpiS3Context.h>\r
31#include <Guid/MemoryAttributesTable.h>\r
32#include <Guid/PiSmmMemoryAttributesTable.h>\r
33\r
34#include <Library/BaseLib.h>\r
35#include <Library/IoLib.h>\r
36#include <Library/TimerLib.h>\r
37#include <Library/SynchronizationLib.h>\r
38#include <Library/DebugLib.h>\r
39#include <Library/BaseMemoryLib.h>\r
40#include <Library/PcdLib.h>\r
41#include <Library/MtrrLib.h>\r
42#include <Library/SmmCpuPlatformHookLib.h>\r
43#include <Library/SmmServicesTableLib.h>\r
44#include <Library/MemoryAllocationLib.h>\r
45#include <Library/UefiBootServicesTableLib.h>\r
46#include <Library/UefiRuntimeServicesTableLib.h>\r
47#include <Library/DebugAgentLib.h>\r
48#include <Library/UefiLib.h>\r
49#include <Library/HobLib.h>\r
50#include <Library/LocalApicLib.h>\r
51#include <Library/UefiCpuLib.h>\r
52#include <Library/CpuExceptionHandlerLib.h>\r
53#include <Library/ReportStatusCodeLib.h>\r
54#include <Library/SmmCpuFeaturesLib.h>\r
55#include <Library/PeCoffGetEntryPointLib.h>\r
56\r
57#include <AcpiCpuData.h>\r
58#include <CpuHotPlugData.h>\r
59\r
60#include <Register/Cpuid.h>\r
61#include <Register/Msr.h>\r
62\r
63#include "CpuService.h"\r
64#include "SmmProfile.h"\r
65\r
66//\r
67// MSRs required for configuration of SMM Code Access Check\r
68//\r
69#define EFI_MSR_SMM_MCA_CAP 0x17D\r
70#define SMM_CODE_ACCESS_CHK_BIT BIT58\r
71\r
72#define SMM_FEATURE_CONTROL_LOCK_BIT BIT0\r
73#define SMM_CODE_CHK_EN_BIT BIT2\r
74\r
75///\r
76/// Page Table Entry\r
77///\r
78#define IA32_PG_P BIT0\r
79#define IA32_PG_RW BIT1\r
80#define IA32_PG_U BIT2\r
81#define IA32_PG_WT BIT3\r
82#define IA32_PG_CD BIT4\r
83#define IA32_PG_A BIT5\r
84#define IA32_PG_D BIT6\r
85#define IA32_PG_PS BIT7\r
86#define IA32_PG_PAT_2M BIT12\r
87#define IA32_PG_PAT_4K IA32_PG_PS\r
88#define IA32_PG_PMNT BIT62\r
89#define IA32_PG_NX BIT63\r
90\r
91#define PAGE_ATTRIBUTE_BITS (IA32_PG_D | IA32_PG_A | IA32_PG_U | IA32_PG_RW | IA32_PG_P)\r
92//\r
93// Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE\r
94// X64 PAE PDPTE does not have such restriction\r
95//\r
96#define IA32_PAE_PDPTE_ATTRIBUTE_BITS (IA32_PG_P)\r
97\r
98#define PAGE_PROGATE_BITS (IA32_PG_NX | PAGE_ATTRIBUTE_BITS)\r
99\r
100#define PAGING_4K_MASK 0xFFF\r
101#define PAGING_2M_MASK 0x1FFFFF\r
102#define PAGING_1G_MASK 0x3FFFFFFF\r
103\r
104#define PAGING_PAE_INDEX_MASK 0x1FF\r
105\r
106#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull\r
107#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull\r
108#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull\r
109\r
110#define SMRR_MAX_ADDRESS BASE_4GB\r
111\r
112typedef enum {\r
113 PageNone,\r
114 Page4K,\r
115 Page2M,\r
116 Page1G,\r
117} PAGE_ATTRIBUTE;\r
118\r
119typedef struct {\r
120 PAGE_ATTRIBUTE Attribute;\r
121 UINT64 Length;\r
122 UINT64 AddressMask;\r
123} PAGE_ATTRIBUTE_TABLE;\r
124\r
125//\r
126// Size of Task-State Segment defined in IA32 Manual\r
127//\r
128#define TSS_SIZE 104\r
129#define TSS_X64_IST1_OFFSET 36\r
130#define TSS_IA32_CR3_OFFSET 28\r
131#define TSS_IA32_ESP_OFFSET 56\r
132\r
133#define CR0_WP BIT16\r
134\r
135//\r
136// Code select value\r
137//\r
138#define PROTECT_MODE_CODE_SEGMENT 0x08\r
139#define LONG_MODE_CODE_SEGMENT 0x38\r
140\r
141//\r
142// The size 0x20 must be bigger than\r
143// the size of template code of SmmInit. Currently,\r
144// the size of SmmInit requires the 0x16 Bytes buffer\r
145// at least.\r
146//\r
147#define BACK_BUF_SIZE 0x20\r
148\r
149#define EXCEPTION_VECTOR_NUMBER 0x20\r
150\r
151#define INVALID_APIC_ID 0xFFFFFFFFFFFFFFFFULL\r
152\r
153typedef UINT32 SMM_CPU_ARRIVAL_EXCEPTIONS;\r
154#define ARRIVAL_EXCEPTION_BLOCKED 0x1\r
155#define ARRIVAL_EXCEPTION_DELAYED 0x2\r
156#define ARRIVAL_EXCEPTION_SMI_DISABLED 0x4\r
157\r
158//\r
159// Private structure for the SMM CPU module that is stored in DXE Runtime memory\r
160// Contains the SMM Configuration Protocols that is produced.\r
161// Contains a mix of DXE and SMM contents. All the fields must be used properly.\r
162//\r
163#define SMM_CPU_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('s', 'c', 'p', 'u')\r
164\r
165typedef struct {\r
166 UINTN Signature;\r
167\r
168 EFI_HANDLE SmmCpuHandle;\r
169\r
170 EFI_PROCESSOR_INFORMATION *ProcessorInfo;\r
171 SMM_CPU_OPERATION *Operation;\r
172 UINTN *CpuSaveStateSize;\r
173 VOID **CpuSaveState;\r
174\r
175 EFI_SMM_RESERVED_SMRAM_REGION SmmReservedSmramRegion[1];\r
176 EFI_SMM_ENTRY_CONTEXT SmmCoreEntryContext;\r
177 EFI_SMM_ENTRY_POINT SmmCoreEntry;\r
178\r
179 EFI_SMM_CONFIGURATION_PROTOCOL SmmConfiguration;\r
180} SMM_CPU_PRIVATE_DATA;\r
181\r
182extern SMM_CPU_PRIVATE_DATA *gSmmCpuPrivate;\r
183extern CPU_HOT_PLUG_DATA mCpuHotPlugData;\r
184extern UINTN mMaxNumberOfCpus;\r
185extern UINTN mNumberOfCpus;\r
186extern EFI_SMM_CPU_PROTOCOL mSmmCpu;\r
187\r
188///\r
189/// The mode of the CPU at the time an SMI occurs\r
190///\r
191extern UINT8 mSmmSaveStateRegisterLma;\r
192\r
193//\r
194// SMM CPU Protocol function prototypes.\r
195//\r
196\r
197/**\r
198 Read information from the CPU save state.\r
199\r
200 @param This EFI_SMM_CPU_PROTOCOL instance\r
201 @param Width The number of bytes to read from the CPU save state.\r
202 @param Register Specifies the CPU register to read form the save state.\r
203 @param CpuIndex Specifies the zero-based index of the CPU save state\r
204 @param Buffer Upon return, this holds the CPU register value read from the save state.\r
205\r
206 @retval EFI_SUCCESS The register was read from Save State\r
207 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r
208 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r
209\r
210**/\r
211EFI_STATUS\r
212EFIAPI\r
213SmmReadSaveState (\r
214 IN CONST EFI_SMM_CPU_PROTOCOL *This,\r
215 IN UINTN Width,\r
216 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
217 IN UINTN CpuIndex,\r
218 OUT VOID *Buffer\r
219 );\r
220\r
221/**\r
222 Write data to the CPU save state.\r
223\r
224 @param This EFI_SMM_CPU_PROTOCOL instance\r
225 @param Width The number of bytes to read from the CPU save state.\r
226 @param Register Specifies the CPU register to write to the save state.\r
227 @param CpuIndex Specifies the zero-based index of the CPU save state\r
228 @param Buffer Upon entry, this holds the new CPU register value.\r
229\r
230 @retval EFI_SUCCESS The register was written from Save State\r
231 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r
232 @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct\r
233\r
234**/\r
235EFI_STATUS\r
236EFIAPI\r
237SmmWriteSaveState (\r
238 IN CONST EFI_SMM_CPU_PROTOCOL *This,\r
239 IN UINTN Width,\r
240 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
241 IN UINTN CpuIndex,\r
242 IN CONST VOID *Buffer\r
243 );\r
244\r
245/**\r
246Read a CPU Save State register on the target processor.\r
247\r
248This function abstracts the differences that whether the CPU Save State register is in the\r
249IA32 CPU Save State Map or X64 CPU Save State Map.\r
250\r
251This function supports reading a CPU Save State register in SMBase relocation handler.\r
252\r
253@param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r
254@param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r
255@param[in] Width The number of bytes to read from the CPU save state.\r
256@param[out] Buffer Upon return, this holds the CPU register value read from the save state.\r
257\r
258@retval EFI_SUCCESS The register was read from Save State.\r
259@retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r
260@retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r
261\r
262**/\r
263EFI_STATUS\r
264EFIAPI\r
265ReadSaveStateRegister (\r
266 IN UINTN CpuIndex,\r
267 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
268 IN UINTN Width,\r
269 OUT VOID *Buffer\r
270 );\r
271\r
272/**\r
273Write value to a CPU Save State register on the target processor.\r
274\r
275This function abstracts the differences that whether the CPU Save State register is in the\r
276IA32 CPU Save State Map or X64 CPU Save State Map.\r
277\r
278This function supports writing a CPU Save State register in SMBase relocation handler.\r
279\r
280@param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r
281@param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r
282@param[in] Width The number of bytes to read from the CPU save state.\r
283@param[in] Buffer Upon entry, this holds the new CPU register value.\r
284\r
285@retval EFI_SUCCESS The register was written to Save State.\r
286@retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r
287@retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct.\r
288\r
289**/\r
290EFI_STATUS\r
291EFIAPI\r
292WriteSaveStateRegister (\r
293 IN UINTN CpuIndex,\r
294 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
295 IN UINTN Width,\r
296 IN CONST VOID *Buffer\r
297 );\r
298\r
299extern CONST UINT8 gcSmmInitTemplate[];\r
300extern CONST UINT16 gcSmmInitSize;\r
301X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr0;\r
302extern UINT32 mSmmCr0;\r
303X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr3;\r
304extern UINT32 mSmmCr4;\r
305X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr4;\r
306X86_ASSEMBLY_PATCH_LABEL gPatchSmmInitStack;\r
307\r
308/**\r
309 Semaphore operation for all processor relocate SMMBase.\r
310**/\r
311VOID\r
312EFIAPI\r
313SmmRelocationSemaphoreComplete (\r
314 VOID\r
315 );\r
316\r
317///\r
318/// The type of SMM CPU Information\r
319///\r
320typedef struct {\r
321 SPIN_LOCK *Busy;\r
322 volatile EFI_AP_PROCEDURE Procedure;\r
323 volatile VOID *Parameter;\r
324 volatile UINT32 *Run;\r
325 volatile BOOLEAN *Present;\r
326} SMM_CPU_DATA_BLOCK;\r
327\r
328typedef enum {\r
329 SmmCpuSyncModeTradition,\r
330 SmmCpuSyncModeRelaxedAp,\r
331 SmmCpuSyncModeMax\r
332} SMM_CPU_SYNC_MODE;\r
333\r
334typedef struct {\r
335 //\r
336 // Pointer to an array. The array should be located immediately after this structure\r
337 // so that UC cache-ability can be set together.\r
338 //\r
339 SMM_CPU_DATA_BLOCK *CpuData;\r
340 volatile UINT32 *Counter;\r
341 volatile UINT32 BspIndex;\r
342 volatile BOOLEAN *InsideSmm;\r
343 volatile BOOLEAN *AllCpusInSync;\r
344 volatile SMM_CPU_SYNC_MODE EffectiveSyncMode;\r
345 volatile BOOLEAN SwitchBsp;\r
346 volatile BOOLEAN *CandidateBsp;\r
347} SMM_DISPATCHER_MP_SYNC_DATA;\r
348\r
349#define MSR_SPIN_LOCK_INIT_NUM 15\r
350\r
351typedef struct {\r
352 SPIN_LOCK *SpinLock;\r
353 UINT32 MsrIndex;\r
354} MP_MSR_LOCK;\r
355\r
356#define SMM_PSD_OFFSET 0xfb00\r
357\r
358///\r
359/// All global semaphores' pointer\r
360///\r
361typedef struct {\r
362 volatile UINT32 *Counter;\r
363 volatile BOOLEAN *InsideSmm;\r
364 volatile BOOLEAN *AllCpusInSync;\r
365 SPIN_LOCK *PFLock;\r
366 SPIN_LOCK *CodeAccessCheckLock;\r
367 SPIN_LOCK *MemoryMappedLock;\r
368} SMM_CPU_SEMAPHORE_GLOBAL;\r
369\r
370///\r
371/// All semaphores for each processor\r
372///\r
373typedef struct {\r
374 SPIN_LOCK *Busy;\r
375 volatile UINT32 *Run;\r
376 volatile BOOLEAN *Present;\r
377} SMM_CPU_SEMAPHORE_CPU;\r
378\r
379///\r
380/// All MSRs semaphores' pointer and counter\r
381///\r
382typedef struct {\r
383 SPIN_LOCK *Msr;\r
384 UINTN AvailableCounter;\r
385} SMM_CPU_SEMAPHORE_MSR;\r
386\r
387///\r
388/// All semaphores' information\r
389///\r
390typedef struct {\r
391 SMM_CPU_SEMAPHORE_GLOBAL SemaphoreGlobal;\r
392 SMM_CPU_SEMAPHORE_CPU SemaphoreCpu;\r
393 SMM_CPU_SEMAPHORE_MSR SemaphoreMsr;\r
394} SMM_CPU_SEMAPHORES;\r
395\r
396extern IA32_DESCRIPTOR gcSmiGdtr;\r
397extern EFI_PHYSICAL_ADDRESS mGdtBuffer;\r
398extern UINTN mGdtBufferSize;\r
399extern IA32_DESCRIPTOR gcSmiIdtr;\r
400extern VOID *gcSmiIdtrPtr;\r
401extern UINT64 gPhyMask;\r
402extern SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData;\r
403extern UINTN mSmmStackArrayBase;\r
404extern UINTN mSmmStackArrayEnd;\r
405extern UINTN mSmmStackSize;\r
406extern EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService;\r
407extern IA32_DESCRIPTOR gcSmiInitGdtr;\r
408extern SMM_CPU_SEMAPHORES mSmmCpuSemaphores;\r
409extern UINTN mSemaphoreSize;\r
410extern SPIN_LOCK *mPFLock;\r
411extern SPIN_LOCK *mConfigSmmCodeAccessCheckLock;\r
412extern SPIN_LOCK *mMemoryMappedLock;\r
413extern EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges;\r
414extern UINTN mSmmCpuSmramRangeCount;\r
415extern UINT8 mPhysicalAddressBits;\r
416\r
417//\r
418// Copy of the PcdPteMemoryEncryptionAddressOrMask\r
419//\r
420extern UINT64 mAddressEncMask;\r
421\r
422/**\r
423 Create 4G PageTable in SMRAM.\r
424\r
425 @param[in] Is32BitPageTable Whether the page table is 32-bit PAE\r
426 @return PageTable Address\r
427\r
428**/\r
429UINT32\r
430Gen4GPageTable (\r
431 IN BOOLEAN Is32BitPageTable\r
432 );\r
433\r
434\r
435/**\r
436 Initialize global data for MP synchronization.\r
437\r
438 @param Stacks Base address of SMI stack buffer for all processors.\r
439 @param StackSize Stack size for each processor in SMM.\r
440\r
441**/\r
442UINT32\r
443InitializeMpServiceData (\r
444 IN VOID *Stacks,\r
445 IN UINTN StackSize\r
446 );\r
447\r
448/**\r
449 Initialize Timer for SMM AP Sync.\r
450\r
451**/\r
452VOID\r
453InitializeSmmTimer (\r
454 VOID\r
455 );\r
456\r
457/**\r
458 Start Timer for SMM AP Sync.\r
459\r
460**/\r
461UINT64\r
462EFIAPI\r
463StartSyncTimer (\r
464 VOID\r
465 );\r
466\r
467/**\r
468 Check if the SMM AP Sync timer is timeout.\r
469\r
470 @param Timer The start timer from the begin.\r
471\r
472**/\r
473BOOLEAN\r
474EFIAPI\r
475IsSyncTimerTimeout (\r
476 IN UINT64 Timer\r
477 );\r
478\r
479/**\r
480 Initialize IDT for SMM Stack Guard.\r
481\r
482**/\r
483VOID\r
484EFIAPI\r
485InitializeIDTSmmStackGuard (\r
486 VOID\r
487 );\r
488\r
489/**\r
490 Initialize Gdt for all processors.\r
491\r
492 @param[in] Cr3 CR3 value.\r
493 @param[out] GdtStepSize The step size for GDT table.\r
494\r
495 @return GdtBase for processor 0.\r
496 GdtBase for processor X is: GdtBase + (GdtStepSize * X)\r
497**/\r
498VOID *\r
499InitGdt (\r
500 IN UINTN Cr3,\r
501 OUT UINTN *GdtStepSize\r
502 );\r
503\r
504/**\r
505\r
506 Register the SMM Foundation entry point.\r
507\r
508 @param This Pointer to EFI_SMM_CONFIGURATION_PROTOCOL instance\r
509 @param SmmEntryPoint SMM Foundation EntryPoint\r
510\r
511 @retval EFI_SUCCESS Successfully to register SMM foundation entry point\r
512\r
513**/\r
514EFI_STATUS\r
515EFIAPI\r
516RegisterSmmEntry (\r
517 IN CONST EFI_SMM_CONFIGURATION_PROTOCOL *This,\r
518 IN EFI_SMM_ENTRY_POINT SmmEntryPoint\r
519 );\r
520\r
521/**\r
522 Create PageTable for SMM use.\r
523\r
524 @return PageTable Address\r
525\r
526**/\r
527UINT32\r
528SmmInitPageTable (\r
529 VOID\r
530 );\r
531\r
532/**\r
533 Schedule a procedure to run on the specified CPU.\r
534\r
535 @param Procedure The address of the procedure to run\r
536 @param CpuIndex Target CPU number\r
537 @param ProcArguments The parameter to pass to the procedure\r
538\r
539 @retval EFI_INVALID_PARAMETER CpuNumber not valid\r
540 @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP\r
541 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM\r
542 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy\r
543 @retval EFI_SUCCESS - The procedure has been successfully scheduled\r
544\r
545**/\r
546EFI_STATUS\r
547EFIAPI\r
548SmmStartupThisAp (\r
549 IN EFI_AP_PROCEDURE Procedure,\r
550 IN UINTN CpuIndex,\r
551 IN OUT VOID *ProcArguments OPTIONAL\r
552 );\r
553\r
554/**\r
555 Schedule a procedure to run on the specified CPU in a blocking fashion.\r
556\r
557 @param Procedure The address of the procedure to run\r
558 @param CpuIndex Target CPU Index\r
559 @param ProcArguments The parameter to pass to the procedure\r
560\r
561 @retval EFI_INVALID_PARAMETER CpuNumber not valid\r
562 @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP\r
563 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM\r
564 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy\r
565 @retval EFI_SUCCESS The procedure has been successfully scheduled\r
566\r
567**/\r
568EFI_STATUS\r
569EFIAPI\r
570SmmBlockingStartupThisAp (\r
571 IN EFI_AP_PROCEDURE Procedure,\r
572 IN UINTN CpuIndex,\r
573 IN OUT VOID *ProcArguments OPTIONAL\r
574 );\r
575\r
576/**\r
577 This function sets the attributes for the memory region specified by BaseAddress and\r
578 Length from their current attributes to the attributes specified by Attributes.\r
579\r
580 @param[in] BaseAddress The physical address that is the start address of a memory region.\r
581 @param[in] Length The size in bytes of the memory region.\r
582 @param[in] Attributes The bit mask of attributes to set for the memory region.\r
583\r
584 @retval EFI_SUCCESS The attributes were set for the memory region.\r
585 @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r
586 BaseAddress and Length cannot be modified.\r
587 @retval EFI_INVALID_PARAMETER Length is zero.\r
588 Attributes specified an illegal combination of attributes that\r
589 cannot be set together.\r
590 @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r
591 the memory resource range.\r
592 @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r
593 resource range specified by BaseAddress and Length.\r
594 The bit mask of attributes is not support for the memory resource\r
595 range specified by BaseAddress and Length.\r
596\r
597**/\r
598EFI_STATUS\r
599EFIAPI\r
600SmmSetMemoryAttributes (\r
601 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
602 IN UINT64 Length,\r
603 IN UINT64 Attributes\r
604 );\r
605\r
606/**\r
607 This function clears the attributes for the memory region specified by BaseAddress and\r
608 Length from their current attributes to the attributes specified by Attributes.\r
609\r
610 @param[in] BaseAddress The physical address that is the start address of a memory region.\r
611 @param[in] Length The size in bytes of the memory region.\r
612 @param[in] Attributes The bit mask of attributes to clear for the memory region.\r
613\r
614 @retval EFI_SUCCESS The attributes were cleared for the memory region.\r
615 @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r
616 BaseAddress and Length cannot be modified.\r
617 @retval EFI_INVALID_PARAMETER Length is zero.\r
618 Attributes specified an illegal combination of attributes that\r
619 cannot be set together.\r
620 @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r
621 the memory resource range.\r
622 @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r
623 resource range specified by BaseAddress and Length.\r
624 The bit mask of attributes is not support for the memory resource\r
625 range specified by BaseAddress and Length.\r
626\r
627**/\r
628EFI_STATUS\r
629EFIAPI\r
630SmmClearMemoryAttributes (\r
631 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
632 IN UINT64 Length,\r
633 IN UINT64 Attributes\r
634 );\r
635\r
636/**\r
637 Initialize MP synchronization data.\r
638\r
639**/\r
640VOID\r
641EFIAPI\r
642InitializeMpSyncData (\r
643 VOID\r
644 );\r
645\r
646/**\r
647\r
648 Find out SMRAM information including SMRR base and SMRR size.\r
649\r
650 @param SmrrBase SMRR base\r
651 @param SmrrSize SMRR size\r
652\r
653**/\r
654VOID\r
655FindSmramInfo (\r
656 OUT UINT32 *SmrrBase,\r
657 OUT UINT32 *SmrrSize\r
658 );\r
659\r
660/**\r
661 Relocate SmmBases for each processor.\r
662\r
663 Execute on first boot and all S3 resumes\r
664\r
665**/\r
666VOID\r
667EFIAPI\r
668SmmRelocateBases (\r
669 VOID\r
670 );\r
671\r
672/**\r
673 Page Fault handler for SMM use.\r
674\r
675 @param InterruptType Defines the type of interrupt or exception that\r
676 occurred on the processor.This parameter is processor architecture specific.\r
677 @param SystemContext A pointer to the processor context when\r
678 the interrupt occurred on the processor.\r
679**/\r
680VOID\r
681EFIAPI\r
682SmiPFHandler (\r
683 IN EFI_EXCEPTION_TYPE InterruptType,\r
684 IN EFI_SYSTEM_CONTEXT SystemContext\r
685 );\r
686\r
687/**\r
688 Perform the remaining tasks.\r
689\r
690**/\r
691VOID\r
692PerformRemainingTasks (\r
693 VOID\r
694 );\r
695\r
696/**\r
697 Perform the pre tasks.\r
698\r
699**/\r
700VOID\r
701PerformPreTasks (\r
702 VOID\r
703 );\r
704\r
705/**\r
706 Initialize MSR spin lock by MSR index.\r
707\r
708 @param MsrIndex MSR index value.\r
709\r
710**/\r
711VOID\r
712InitMsrSpinLockByIndex (\r
713 IN UINT32 MsrIndex\r
714 );\r
715\r
716/**\r
717 Hook return address of SMM Save State so that semaphore code\r
718 can be executed immediately after AP exits SMM to indicate to\r
719 the BSP that an AP has exited SMM after SMBASE relocation.\r
720\r
721 @param[in] CpuIndex The processor index.\r
722 @param[in] RebasedFlag A pointer to a flag that is set to TRUE\r
723 immediately after AP exits SMM.\r
724\r
725**/\r
726VOID\r
727SemaphoreHook (\r
728 IN UINTN CpuIndex,\r
729 IN volatile BOOLEAN *RebasedFlag\r
730 );\r
731\r
732/**\r
733Configure SMM Code Access Check feature for all processors.\r
734SMM Feature Control MSR will be locked after configuration.\r
735**/\r
736VOID\r
737ConfigSmmCodeAccessCheck (\r
738 VOID\r
739 );\r
740\r
741/**\r
742 Hook the code executed immediately after an RSM instruction on the currently\r
743 executing CPU. The mode of code executed immediately after RSM must be\r
744 detected, and the appropriate hook must be selected. Always clear the auto\r
745 HALT restart flag if it is set.\r
746\r
747 @param[in] CpuIndex The processor index for the currently\r
748 executing CPU.\r
749 @param[in] CpuState Pointer to SMRAM Save State Map for the\r
750 currently executing CPU.\r
751 @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to\r
752 32-bit mode from 64-bit SMM.\r
753 @param[in] NewInstructionPointer Instruction pointer to use if resuming to\r
754 same mode as SMM.\r
755\r
756 @retval The value of the original instruction pointer before it was hooked.\r
757\r
758**/\r
759UINT64\r
760EFIAPI\r
761HookReturnFromSmm (\r
762 IN UINTN CpuIndex,\r
763 SMRAM_SAVE_STATE_MAP *CpuState,\r
764 UINT64 NewInstructionPointer32,\r
765 UINT64 NewInstructionPointer\r
766 );\r
767\r
768/**\r
769 Get the size of the SMI Handler in bytes.\r
770\r
771 @retval The size, in bytes, of the SMI Handler.\r
772\r
773**/\r
774UINTN\r
775EFIAPI\r
776GetSmiHandlerSize (\r
777 VOID\r
778 );\r
779\r
780/**\r
781 Install the SMI handler for the CPU specified by CpuIndex. This function\r
782 is called by the CPU that was elected as monarch during System Management\r
783 Mode initialization.\r
784\r
785 @param[in] CpuIndex The index of the CPU to install the custom SMI handler.\r
786 The value must be between 0 and the NumberOfCpus field\r
787 in the System Management System Table (SMST).\r
788 @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.\r
789 @param[in] SmiStack The stack to use when an SMI is processed by the\r
790 the CPU specified by CpuIndex.\r
791 @param[in] StackSize The size, in bytes, if the stack used when an SMI is\r
792 processed by the CPU specified by CpuIndex.\r
793 @param[in] GdtBase The base address of the GDT to use when an SMI is\r
794 processed by the CPU specified by CpuIndex.\r
795 @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is\r
796 processed by the CPU specified by CpuIndex.\r
797 @param[in] IdtBase The base address of the IDT to use when an SMI is\r
798 processed by the CPU specified by CpuIndex.\r
799 @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is\r
800 processed by the CPU specified by CpuIndex.\r
801 @param[in] Cr3 The base address of the page tables to use when an SMI\r
802 is processed by the CPU specified by CpuIndex.\r
803**/\r
804VOID\r
805EFIAPI\r
806InstallSmiHandler (\r
807 IN UINTN CpuIndex,\r
808 IN UINT32 SmBase,\r
809 IN VOID *SmiStack,\r
810 IN UINTN StackSize,\r
811 IN UINTN GdtBase,\r
812 IN UINTN GdtSize,\r
813 IN UINTN IdtBase,\r
814 IN UINTN IdtSize,\r
815 IN UINT32 Cr3\r
816 );\r
817\r
818/**\r
819 Search module name by input IP address and output it.\r
820\r
821 @param CallerIpAddress Caller instruction pointer.\r
822\r
823**/\r
824VOID\r
825DumpModuleInfoByIp (\r
826 IN UINTN CallerIpAddress\r
827 );\r
828\r
829/**\r
830 This function sets memory attribute according to MemoryAttributesTable.\r
831**/\r
832VOID\r
833SetMemMapAttributes (\r
834 VOID\r
835 );\r
836\r
837/**\r
838 This function sets UEFI memory attribute according to UEFI memory map.\r
839**/\r
840VOID\r
841SetUefiMemMapAttributes (\r
842 VOID\r
843 );\r
844\r
845/**\r
846 Return if the Address is forbidden as SMM communication buffer.\r
847\r
848 @param[in] Address the address to be checked\r
849\r
850 @return TRUE The address is forbidden as SMM communication buffer.\r
851 @return FALSE The address is allowed as SMM communication buffer.\r
852**/\r
853BOOLEAN\r
854IsSmmCommBufferForbiddenAddress (\r
855 IN UINT64 Address\r
856 );\r
857\r
858/**\r
859 This function caches the UEFI memory map information.\r
860**/\r
861VOID\r
862GetUefiMemoryMap (\r
863 VOID\r
864 );\r
865\r
866/**\r
867 This function sets memory attribute for page table.\r
868**/\r
869VOID\r
870SetPageTableAttributes (\r
871 VOID\r
872 );\r
873\r
874/**\r
875 Return page table base.\r
876\r
877 @return page table base.\r
878**/\r
879UINTN\r
880GetPageTableBase (\r
881 VOID\r
882 );\r
883\r
884/**\r
885 This function sets the attributes for the memory region specified by BaseAddress and\r
886 Length from their current attributes to the attributes specified by Attributes.\r
887\r
888 @param[in] BaseAddress The physical address that is the start address of a memory region.\r
889 @param[in] Length The size in bytes of the memory region.\r
890 @param[in] Attributes The bit mask of attributes to set for the memory region.\r
891 @param[out] IsSplitted TRUE means page table splitted. FALSE means page table not splitted.\r
892\r
893 @retval EFI_SUCCESS The attributes were set for the memory region.\r
894 @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r
895 BaseAddress and Length cannot be modified.\r
896 @retval EFI_INVALID_PARAMETER Length is zero.\r
897 Attributes specified an illegal combination of attributes that\r
898 cannot be set together.\r
899 @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r
900 the memory resource range.\r
901 @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r
902 resource range specified by BaseAddress and Length.\r
903 The bit mask of attributes is not support for the memory resource\r
904 range specified by BaseAddress and Length.\r
905\r
906**/\r
907EFI_STATUS\r
908EFIAPI\r
909SmmSetMemoryAttributesEx (\r
910 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
911 IN UINT64 Length,\r
912 IN UINT64 Attributes,\r
913 OUT BOOLEAN *IsSplitted OPTIONAL\r
914 );\r
915\r
916/**\r
917 This function clears the attributes for the memory region specified by BaseAddress and\r
918 Length from their current attributes to the attributes specified by Attributes.\r
919\r
920 @param[in] BaseAddress The physical address that is the start address of a memory region.\r
921 @param[in] Length The size in bytes of the memory region.\r
922 @param[in] Attributes The bit mask of attributes to clear for the memory region.\r
923 @param[out] IsSplitted TRUE means page table splitted. FALSE means page table not splitted.\r
924\r
925 @retval EFI_SUCCESS The attributes were cleared for the memory region.\r
926 @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r
927 BaseAddress and Length cannot be modified.\r
928 @retval EFI_INVALID_PARAMETER Length is zero.\r
929 Attributes specified an illegal combination of attributes that\r
930 cannot be set together.\r
931 @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r
932 the memory resource range.\r
933 @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r
934 resource range specified by BaseAddress and Length.\r
935 The bit mask of attributes is not support for the memory resource\r
936 range specified by BaseAddress and Length.\r
937\r
938**/\r
939EFI_STATUS\r
940EFIAPI\r
941SmmClearMemoryAttributesEx (\r
942 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
943 IN UINT64 Length,\r
944 IN UINT64 Attributes,\r
945 OUT BOOLEAN *IsSplitted OPTIONAL\r
946 );\r
947\r
948/**\r
949 This API provides a way to allocate memory for page table.\r
950\r
951 This API can be called more once to allocate memory for page tables.\r
952\r
953 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the\r
954 allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL\r
955 is returned. If there is not enough memory remaining to satisfy the request, then NULL is\r
956 returned.\r
957\r
958 @param Pages The number of 4 KB pages to allocate.\r
959\r
960 @return A pointer to the allocated buffer or NULL if allocation fails.\r
961\r
962**/\r
963VOID *\r
964AllocatePageTableMemory (\r
965 IN UINTN Pages\r
966 );\r
967\r
968/**\r
969 Allocate pages for code.\r
970\r
971 @param[in] Pages Number of pages to be allocated.\r
972\r
973 @return Allocated memory.\r
974**/\r
975VOID *\r
976AllocateCodePages (\r
977 IN UINTN Pages\r
978 );\r
979\r
980/**\r
981 Allocate aligned pages for code.\r
982\r
983 @param[in] Pages Number of pages to be allocated.\r
984 @param[in] Alignment The requested alignment of the allocation.\r
985 Must be a power of two.\r
986 If Alignment is zero, then byte alignment is used.\r
987\r
988 @return Allocated memory.\r
989**/\r
990VOID *\r
991AllocateAlignedCodePages (\r
992 IN UINTN Pages,\r
993 IN UINTN Alignment\r
994 );\r
995\r
996\r
997//\r
998// S3 related global variable and function prototype.\r
999//\r
1000\r
1001extern BOOLEAN mSmmS3Flag;\r
1002\r
1003/**\r
1004 Initialize SMM S3 resume state structure used during S3 Resume.\r
1005\r
1006 @param[in] Cr3 The base address of the page tables to use in SMM.\r
1007\r
1008**/\r
1009VOID\r
1010InitSmmS3ResumeState (\r
1011 IN UINT32 Cr3\r
1012 );\r
1013\r
1014/**\r
1015 Get ACPI CPU data.\r
1016\r
1017**/\r
1018VOID\r
1019GetAcpiCpuData (\r
1020 VOID\r
1021 );\r
1022\r
1023/**\r
1024 Restore SMM Configuration in S3 boot path.\r
1025\r
1026**/\r
1027VOID\r
1028RestoreSmmConfigurationInS3 (\r
1029 VOID\r
1030 );\r
1031\r
1032/**\r
1033 Get ACPI S3 enable flag.\r
1034\r
1035**/\r
1036VOID\r
1037GetAcpiS3EnableFlag (\r
1038 VOID\r
1039 );\r
1040\r
1041/**\r
1042 Transfer AP to safe hlt-loop after it finished restore CPU features on S3 patch.\r
1043\r
1044 @param[in] ApHltLoopCode The address of the safe hlt-loop function.\r
1045 @param[in] TopOfStack A pointer to the new stack to use for the ApHltLoopCode.\r
1046 @param[in] NumberToFinishAddress Address of Semaphore of APs finish count.\r
1047\r
1048**/\r
1049VOID\r
1050TransferApToSafeState (\r
1051 IN UINTN ApHltLoopCode,\r
1052 IN UINTN TopOfStack,\r
1053 IN UINTN NumberToFinishAddress\r
1054 );\r
1055\r
1056/**\r
1057 This function set given attributes of the memory region specified by\r
1058 BaseAddress and Length.\r
1059\r
1060 @param This The EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL instance.\r
1061 @param BaseAddress The physical address that is the start address of\r
1062 a memory region.\r
1063 @param Length The size in bytes of the memory region.\r
1064 @param Attributes The bit mask of attributes to set for the memory\r
1065 region.\r
1066\r
1067 @retval EFI_SUCCESS The attributes were set for the memory region.\r
1068 @retval EFI_INVALID_PARAMETER Length is zero.\r
1069 Attributes specified an illegal combination of\r
1070 attributes that cannot be set together.\r
1071 @retval EFI_UNSUPPORTED The processor does not support one or more\r
1072 bytes of the memory resource range specified\r
1073 by BaseAddress and Length.\r
1074 The bit mask of attributes is not supported for\r
1075 the memory resource range specified by\r
1076 BaseAddress and Length.\r
1077\r
1078**/\r
1079EFI_STATUS\r
1080EFIAPI\r
1081EdkiiSmmSetMemoryAttributes (\r
1082 IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This,\r
1083 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
1084 IN UINT64 Length,\r
1085 IN UINT64 Attributes\r
1086 );\r
1087\r
1088/**\r
1089 This function clears given attributes of the memory region specified by\r
1090 BaseAddress and Length.\r
1091\r
1092 @param This The EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL instance.\r
1093 @param BaseAddress The physical address that is the start address of\r
1094 a memory region.\r
1095 @param Length The size in bytes of the memory region.\r
1096 @param Attributes The bit mask of attributes to clear for the memory\r
1097 region.\r
1098\r
1099 @retval EFI_SUCCESS The attributes were cleared for the memory region.\r
1100 @retval EFI_INVALID_PARAMETER Length is zero.\r
1101 Attributes specified an illegal combination of\r
1102 attributes that cannot be cleared together.\r
1103 @retval EFI_UNSUPPORTED The processor does not support one or more\r
1104 bytes of the memory resource range specified\r
1105 by BaseAddress and Length.\r
1106 The bit mask of attributes is not supported for\r
1107 the memory resource range specified by\r
1108 BaseAddress and Length.\r
1109\r
1110**/\r
1111EFI_STATUS\r
1112EFIAPI\r
1113EdkiiSmmClearMemoryAttributes (\r
1114 IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This,\r
1115 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
1116 IN UINT64 Length,\r
1117 IN UINT64 Attributes\r
1118 );\r
1119\r
1120/**\r
1121 This function retrieves the attributes of the memory region specified by\r
1122 BaseAddress and Length. If different attributes are got from different part\r
1123 of the memory region, EFI_NO_MAPPING will be returned.\r
1124\r
1125 @param This The EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL instance.\r
1126 @param BaseAddress The physical address that is the start address of\r
1127 a memory region.\r
1128 @param Length The size in bytes of the memory region.\r
1129 @param Attributes Pointer to attributes returned.\r
1130\r
1131 @retval EFI_SUCCESS The attributes got for the memory region.\r
1132 @retval EFI_INVALID_PARAMETER Length is zero.\r
1133 Attributes is NULL.\r
1134 @retval EFI_NO_MAPPING Attributes are not consistent cross the memory\r
1135 region.\r
1136 @retval EFI_UNSUPPORTED The processor does not support one or more\r
1137 bytes of the memory resource range specified\r
1138 by BaseAddress and Length.\r
1139\r
1140**/\r
1141EFI_STATUS\r
1142EFIAPI\r
1143EdkiiSmmGetMemoryAttributes (\r
1144 IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This,\r
1145 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
1146 IN UINT64 Length,\r
1147 IN UINT64 *Attributes\r
1148 );\r
1149\r
1150/**\r
1151 This function fixes up the address of the global variable or function\r
1152 referred in SmmInit assembly files to be the absoute address.\r
1153**/\r
1154VOID\r
1155EFIAPI\r
1156PiSmmCpuSmmInitFixupAddress (\r
1157 );\r
1158\r
1159/**\r
1160 This function fixes up the address of the global variable or function\r
1161 referred in SmiEntry assembly files to be the absoute address.\r
1162**/\r
1163VOID\r
1164EFIAPI\r
1165PiSmmCpuSmiEntryFixupAddress (\r
1166 );\r
1167\r
1168#endif\r
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