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1 | ## @file UefiCpuPkg.dec\r | |
2 | # This Package provides UEFI compatible CPU modules and libraries.\r | |
3 | #\r | |
4 | # Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.<BR>\r | |
5 | #\r | |
6 | # SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
7 | #\r | |
8 | ##\r | |
9 | \r | |
10 | [Defines]\r | |
11 | DEC_SPECIFICATION = 0x00010005\r | |
12 | PACKAGE_NAME = UefiCpuPkg\r | |
13 | PACKAGE_UNI_FILE = UefiCpuPkg.uni\r | |
14 | PACKAGE_GUID = 2171df9b-0d39-45aa-ac37-2de190010d23\r | |
15 | PACKAGE_VERSION = 0.90\r | |
16 | \r | |
17 | [Includes]\r | |
18 | Include\r | |
19 | \r | |
20 | [LibraryClasses]\r | |
21 | ## @libraryclass Defines some routines that are generic for IA32 family CPU\r | |
22 | ## to be UEFI specification compliant.\r | |
23 | ##\r | |
24 | UefiCpuLib|Include/Library/UefiCpuLib.h\r | |
25 | \r | |
26 | ## @libraryclass Defines some routines that are used to register/manage/program\r | |
27 | ## CPU features.\r | |
28 | ##\r | |
29 | RegisterCpuFeaturesLib|Include/Library/RegisterCpuFeaturesLib.h\r | |
30 | \r | |
31 | [LibraryClasses.IA32, LibraryClasses.X64]\r | |
32 | ## @libraryclass Provides functions to manage MTRR settings on IA32 and X64 CPUs.\r | |
33 | ##\r | |
34 | MtrrLib|Include/Library/MtrrLib.h\r | |
35 | \r | |
36 | ## @libraryclass Provides functions to manage the Local APIC on IA32 and X64 CPUs.\r | |
37 | ##\r | |
38 | LocalApicLib|Include/Library/LocalApicLib.h\r | |
39 | \r | |
40 | ## @libraryclass Provides platform specific initialization functions in the SEC phase.\r | |
41 | ##\r | |
42 | PlatformSecLib|Include/Library/PlatformSecLib.h\r | |
43 | \r | |
44 | ## @libraryclass Public include file for the SMM CPU Platform Hook Library.\r | |
45 | ##\r | |
46 | SmmCpuPlatformHookLib|Include/Library/SmmCpuPlatformHookLib.h\r | |
47 | \r | |
48 | ## @libraryclass Provides the CPU specific programming for PiSmmCpuDxeSmm module.\r | |
49 | ##\r | |
50 | SmmCpuFeaturesLib|Include/Library/SmmCpuFeaturesLib.h\r | |
51 | \r | |
52 | ## @libraryclass Provides functions to support MP services on CpuMpPei and CpuDxe module.\r | |
53 | ##\r | |
54 | MpInitLib|Include/Library/MpInitLib.h\r | |
55 | \r | |
56 | ## @libraryclass Provides function to support VMGEXIT processing.\r | |
57 | VmgExitLib|Include/Library/VmgExitLib.h\r | |
58 | \r | |
59 | [Guids]\r | |
60 | gUefiCpuPkgTokenSpaceGuid = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}\r | |
61 | gMsegSmramGuid = { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }}\r | |
62 | \r | |
63 | ## Include/Guid/CpuFeaturesSetDone.h\r | |
64 | gEdkiiCpuFeaturesSetDoneGuid = { 0xa82485ce, 0xad6b, 0x4101, { 0x99, 0xd3, 0xe1, 0x35, 0x8c, 0x9e, 0x7e, 0x37 }}\r | |
65 | \r | |
66 | ## Include/Guid/CpuFeaturesInitDone.h\r | |
67 | gEdkiiCpuFeaturesInitDoneGuid = { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }}\r | |
68 | \r | |
69 | ## Include/Guid/MicrocodePatchHob.h\r | |
70 | gEdkiiMicrocodePatchHobGuid = { 0xd178f11d, 0x8716, 0x418e, { 0xa1, 0x31, 0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43 }}\r | |
71 | \r | |
72 | [Protocols]\r | |
73 | ## Include/Protocol/SmmCpuService.h\r | |
74 | gEfiSmmCpuServiceProtocolGuid = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }}\r | |
75 | \r | |
76 | ## Include/Protocol/SmMonitorInit.h\r | |
77 | gEfiSmMonitorInitProtocolGuid = { 0x228f344d, 0xb3de, 0x43bb, { 0xa4, 0xd7, 0xea, 0x20, 0xb, 0x1b, 0x14, 0x82 }}\r | |
78 | \r | |
79 | #\r | |
80 | # [Error.gUefiCpuPkgTokenSpaceGuid]\r | |
81 | # 0x80000001 | Invalid value provided.\r | |
82 | #\r | |
83 | \r | |
84 | [Ppis]\r | |
85 | gEdkiiPeiMpServices2PpiGuid = { 0x5cb9cb3d, 0x31a4, 0x480c, { 0x94, 0x98, 0x29, 0xd2, 0x69, 0xba, 0xcf, 0xba}}\r | |
86 | \r | |
87 | ## Include/Ppi/ShadowMicrocode.h\r | |
88 | gEdkiiPeiShadowMicrocodePpiGuid = { 0x430f6965, 0x9a69, 0x41c5, { 0x93, 0xed, 0x8b, 0xf0, 0x64, 0x35, 0xc1, 0xc6 }}\r | |
89 | \r | |
90 | ## Include/Ppi/RepublishSecPpi.h\r | |
91 | gRepublishSecPpiPpiGuid = { 0x27a71b1e, 0x73ee, 0x43d6, { 0xac, 0xe3, 0x52, 0x1a, 0x2d, 0xc5, 0xd0, 0x92 }}\r | |
92 | \r | |
93 | [PcdsFeatureFlag]\r | |
94 | ## Indicates if SMM Profile will be enabled.\r | |
95 | # If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged.\r | |
96 | # In X64 build, it could not be enabled when PcdCpuSmmRestrictedMemoryAccess is TRUE.\r | |
97 | # In IA32 build, the page table memory is not marked as read-only when it is enabled.\r | |
98 | # This PCD is only for validation purpose. It should be set to false in production.<BR><BR>\r | |
99 | # TRUE - SMM Profile will be enabled.<BR>\r | |
100 | # FALSE - SMM Profile will be disabled.<BR>\r | |
101 | # @Prompt Enable SMM Profile.\r | |
102 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE|BOOLEAN|0x32132109\r | |
103 | \r | |
104 | ## Indicates if the SMM profile log buffer is a ring buffer.\r | |
105 | # If disabled, no additional log can be done when the buffer is full.<BR><BR>\r | |
106 | # TRUE - the SMM profile log buffer is a ring buffer.<BR>\r | |
107 | # FALSE - the SMM profile log buffer is a normal buffer.<BR>\r | |
108 | # @Prompt The SMM profile log buffer is a ring buffer.\r | |
109 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileRingBuffer|FALSE|BOOLEAN|0x3213210a\r | |
110 | \r | |
111 | ## Indicates if SMM Startup AP in a blocking fashion.\r | |
112 | # TRUE - SMM Startup AP in a blocking fashion.<BR>\r | |
113 | # FALSE - SMM Startup AP in a non-blocking fashion.<BR>\r | |
114 | # @Prompt SMM Startup AP in a blocking fashion.\r | |
115 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|FALSE|BOOLEAN|0x32132108\r | |
116 | \r | |
117 | ## Indicates if SMM Stack Guard will be enabled.\r | |
118 | # If enabled, stack overflow in SMM can be caught, preventing chaotic consequences.<BR><BR>\r | |
119 | # TRUE - SMM Stack Guard will be enabled.<BR>\r | |
120 | # FALSE - SMM Stack Guard will be disabled.<BR>\r | |
121 | # @Prompt Enable SMM Stack Guard.\r | |
122 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard|TRUE|BOOLEAN|0x1000001C\r | |
123 | \r | |
124 | ## Indicates if BSP election in SMM will be enabled.\r | |
125 | # If enabled, a BSP will be dynamically elected among all processors in each SMI.\r | |
126 | # Otherwise, processor 0 is always as BSP in each SMI.<BR><BR>\r | |
127 | # TRUE - BSP election in SMM will be enabled.<BR>\r | |
128 | # FALSE - BSP election in SMM will be disabled.<BR>\r | |
129 | # @Prompt Enable BSP election in SMM.\r | |
130 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE|BOOLEAN|0x32132106\r | |
131 | \r | |
132 | ## Indicates if CPU SMM hot-plug will be enabled.<BR><BR>\r | |
133 | # TRUE - SMM CPU hot-plug will be enabled.<BR>\r | |
134 | # FALSE - SMM CPU hot-plug will be disabled.<BR>\r | |
135 | # @Prompt SMM CPU hot-plug.\r | |
136 | gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE|BOOLEAN|0x3213210C\r | |
137 | \r | |
138 | ## Indicates if SMM Debug will be enabled.\r | |
139 | # If enabled, hardware breakpoints in SMRAM can be set outside of SMM mode and take effect in SMM.<BR><BR>\r | |
140 | # TRUE - SMM Debug will be enabled.<BR>\r | |
141 | # FALSE - SMM Debug will be disabled.<BR>\r | |
142 | # @Prompt Enable SMM Debug.\r | |
143 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug|FALSE|BOOLEAN|0x1000001B\r | |
144 | \r | |
145 | ## Indicates if lock SMM Feature Control MSR.<BR><BR>\r | |
146 | # TRUE - SMM Feature Control MSR will be locked.<BR>\r | |
147 | # FALSE - SMM Feature Control MSR will not be locked.<BR>\r | |
148 | # @Prompt Lock SMM Feature Control MSR.\r | |
149 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|TRUE|BOOLEAN|0x3213210B\r | |
150 | \r | |
151 | [PcdsFixedAtBuild]\r | |
152 | ## List of exception vectors which need switching stack.\r | |
153 | # This PCD will only take into effect if PcdCpuStackGuard is enabled.\r | |
154 | # By default exception #DD(8), #PF(14) are supported.\r | |
155 | # @Prompt Specify exception vectors which need switching stack.\r | |
156 | gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList|{0x08, 0x0E}|VOID*|0x30002000\r | |
157 | \r | |
158 | ## Size of good stack for an exception.\r | |
159 | # This PCD will only take into effect if PcdCpuStackGuard is enabled.\r | |
160 | # @Prompt Specify size of good stack of exception which need switching stack.\r | |
161 | gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize|2048|UINT32|0x30002001\r | |
162 | \r | |
163 | ## Count of pre allocated SMM MP tokens per chunk.\r | |
164 | # @Prompt Specify the count of pre allocated SMM MP tokens per chunk.\r | |
165 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmMpTokenCountPerChunk|64|UINT32|0x30002002\r | |
166 | \r | |
167 | ## Area of memory where the SEV-ES work area block lives.\r | |
168 | # @Prompt Configure the SEV-ES work area base\r | |
169 | gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase|0x0|UINT32|0x30002005\r | |
170 | \r | |
171 | ## Size of teh area of memory where the SEV-ES work area block lives.\r | |
172 | # @Prompt Configure the SEV-ES work area base\r | |
173 | gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaSize|0x0|UINT32|0x30002006\r | |
174 | \r | |
175 | [PcdsFixedAtBuild, PcdsPatchableInModule]\r | |
176 | ## This value is the CPU Local APIC base address, which aligns the address on a 4-KByte boundary.\r | |
177 | # @Prompt Configure base address of CPU Local APIC\r | |
178 | # @Expression 0x80000001 | (gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress & 0xfff) == 0\r | |
179 | gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress|0xfee00000|UINT32|0x00000001\r | |
180 | \r | |
181 | ## Specifies delay value in microseconds after sending out an INIT IPI.\r | |
182 | # @Prompt Configure delay value after send an INIT IPI\r | |
183 | gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10000|UINT32|0x30000002\r | |
184 | \r | |
185 | ## This value specifies the Application Processor (AP) stack size, used for Mp Service, which must\r | |
186 | ## aligns the address on a 4-KByte boundary.\r | |
187 | # @Prompt Configure stack size for Application Processor (AP)\r | |
188 | gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x8000|UINT32|0x00000003\r | |
189 | \r | |
190 | ## Specifies stack size in the temporary RAM. 0 means half of TemporaryRamSize.\r | |
191 | # @Prompt Stack size in the temporary RAM.\r | |
192 | gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0|UINT32|0x10001003\r | |
193 | \r | |
194 | ## Specifies buffer size in bytes to save SMM profile data. The value should be a multiple of 4KB.\r | |
195 | # @Prompt SMM profile data buffer size.\r | |
196 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileSize|0x200000|UINT32|0x32132107\r | |
197 | \r | |
198 | ## Specifies stack size in bytes for each processor in SMM.\r | |
199 | # @Prompt Processor stack size in SMM.\r | |
200 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x2000|UINT32|0x32132105\r | |
201 | \r | |
202 | ## Specifies shadow stack size in bytes for each processor in SMM.\r | |
203 | # @Prompt Processor shadow stack size in SMM.\r | |
204 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmShadowStackSize|0x2000|UINT32|0x3213210E\r | |
205 | \r | |
206 | ## Indicates if SMM Code Access Check is enabled.\r | |
207 | # If enabled, the SMM handler cannot execute the code outside SMM regions.\r | |
208 | # This PCD is suggested to TRUE in production image.<BR><BR>\r | |
209 | # TRUE - SMM Code Access Check will be enabled.<BR>\r | |
210 | # FALSE - SMM Code Access Check will be disabled.<BR>\r | |
211 | # @Prompt SMM Code Access Check.\r | |
212 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable|TRUE|BOOLEAN|0x60000013\r | |
213 | \r | |
214 | ## Specifies the number of variable MTRRs reserved for OS use. The default number of\r | |
215 | # MTRRs reserved for OS use is 2.\r | |
216 | # @Prompt Number of reserved variable MTRRs.\r | |
217 | gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0x2|UINT32|0x00000015\r | |
218 | \r | |
219 | ## Specifies buffer size in bytes for STM exception stack. The value should be a multiple of 4KB.\r | |
220 | # @Prompt STM exception stack size.\r | |
221 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStmExceptionStackSize|0x1000|UINT32|0x32132111\r | |
222 | \r | |
223 | ## Specifies buffer size in bytes of MSEG. The value should be a multiple of 4KB.\r | |
224 | # @Prompt MSEG size.\r | |
225 | gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize|0x200000|UINT32|0x32132112\r | |
226 | \r | |
227 | ## Specifies the supported CPU features bit in array.\r | |
228 | # @Prompt Supported CPU features.\r | |
229 | gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSupport|{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}|VOID*|0x00000016\r | |
230 | \r | |
231 | ## Specifies if CPU features will be initialized after SMM relocation.\r | |
232 | # @Prompt If CPU features will be initialized after SMM relocation.\r | |
233 | gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitAfterSmmRelocation|FALSE|BOOLEAN|0x0000001C\r | |
234 | \r | |
235 | ## Specifies if CPU features will be initialized during S3 resume.\r | |
236 | # @Prompt If CPU features will be initialized during S3 resume.\r | |
237 | gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume|FALSE|BOOLEAN|0x0000001D\r | |
238 | \r | |
239 | ## Specifies CPUID Leaf 0x15 Time Stamp Counter and Nominal Core Crystal Clock Frequency.\r | |
240 | # TSC Frequency = ECX (core crystal clock frequency) * EBX/EAX.\r | |
241 | # Intel Xeon Processor Scalable Family with CPUID signature 06_55H = 25000000 (25MHz)\r | |
242 | # 6th and 7th generation Intel Core processors and Intel Xeon W Processor Family = 24000000 (24MHz)\r | |
243 | # Intel Atom processors based on Goldmont Microarchitecture with CPUID signature 06_5CH = 19200000 (19.2MHz)\r | |
244 | # @Prompt This PCD is the nominal frequency of the core crystal clock in Hz as is CPUID Leaf 0x15:ECX\r | |
245 | gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency|24000000|UINT64|0x32132113\r | |
246 | \r | |
247 | ## Specifies the periodic interval value in microseconds for the status check\r | |
248 | # of APs for StartupAllAPs() and StartupThisAP() executed in non-blocking\r | |
249 | # mode in DXE phase.\r | |
250 | # @Prompt Periodic interval value in microseconds for AP status check in DXE.\r | |
251 | gUefiCpuPkgTokenSpaceGuid.PcdCpuApStatusCheckIntervalInMicroSeconds|100000|UINT32|0x0000001E\r | |
252 | \r | |
253 | [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]\r | |
254 | ## Specifies max supported number of Logical Processors.\r | |
255 | # @Prompt Configure max supported number of Logical Processors\r | |
256 | gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|64|UINT32|0x00000002\r | |
257 | ## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.\r | |
258 | # @Prompt Timeout for the BSP to detect all APs for the first time.\r | |
259 | gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000|UINT32|0x00000004\r | |
260 | ## Specifies the number of Logical Processors that are available in the\r | |
261 | # preboot environment after platform reset, including BSP and APs. Possible\r | |
262 | # values:<BR><BR>\r | |
263 | # zero (default) - PcdCpuBootLogicalProcessorNumber is ignored, and\r | |
264 | # PcdCpuApInitTimeOutInMicroSeconds limits the initial AP\r | |
265 | # detection by the BSP.<BR>\r | |
266 | # nonzero - PcdCpuApInitTimeOutInMicroSeconds is ignored. The initial\r | |
267 | # AP detection finishes only when the detected CPU count\r | |
268 | # (BSP plus APs) reaches the value of\r | |
269 | # PcdCpuBootLogicalProcessorNumber, regardless of how long\r | |
270 | # that takes.<BR>\r | |
271 | # @Prompt Number of Logical Processors available after platform reset.\r | |
272 | gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber|0|UINT32|0x00000008\r | |
273 | ## Specifies the base address of the first microcode Patch in the microcode Region.\r | |
274 | # @Prompt Microcode Region base address.\r | |
275 | gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x00000005\r | |
276 | ## Specifies the size of the microcode Region.\r | |
277 | # @Prompt Microcode Region size.\r | |
278 | gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x00000006\r | |
279 | ## Specifies the AP wait loop state during POST phase.\r | |
280 | # The value is defined as below.<BR><BR>\r | |
281 | # 1: Place AP in the Hlt-Loop state.<BR>\r | |
282 | # 2: Place AP in the Mwait-Loop state.<BR>\r | |
283 | # 3: Place AP in the Run-Loop state.<BR>\r | |
284 | # @Prompt The AP wait loop state.\r | |
285 | # @ValidRange 0x80000001 | 1 - 3\r | |
286 | gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|1|UINT8|0x60008006\r | |
287 | ## Specifies the AP target C-state for Mwait during POST phase.\r | |
288 | # The default value 0 means C1 state.\r | |
289 | # The value is defined as below.<BR><BR>\r | |
290 | # @Prompt The specified AP target C-state for Mwait.\r | |
291 | gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0|UINT8|0x00000007\r | |
292 | \r | |
293 | ## Specifies timeout value in microseconds for the BSP in SMM to wait for all APs to come into SMM.\r | |
294 | # @Prompt AP synchronization timeout value in SMM.\r | |
295 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000000|UINT64|0x32132104\r | |
296 | \r | |
297 | ## Indicates the CPU synchronization method used when processing an SMI.\r | |
298 | # 0x00 - Traditional CPU synchronization method.<BR>\r | |
299 | # 0x01 - Relaxed CPU synchronization method.<BR>\r | |
300 | # @Prompt SMM CPU Synchronization Method.\r | |
301 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode|0x00|UINT8|0x60000014\r | |
302 | \r | |
303 | ## Specifies the On-demand clock modulation duty cycle when ACPI feature is enabled.\r | |
304 | # @Prompt The encoded values for target duty cycle modulation.\r | |
305 | # @ValidRange 0x80000001 | 0 - 15\r | |
306 | gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle|0x0|UINT8|0x0000001A\r | |
307 | \r | |
308 | ## Indicates if the current boot is a power-on reset.<BR><BR>\r | |
309 | # TRUE - Current boot is a power-on reset.<BR>\r | |
310 | # FALSE - Current boot is not a power-on reset.<BR>\r | |
311 | # @Prompt Current boot is a power-on reset.\r | |
312 | gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset|FALSE|BOOLEAN|0x0000001B\r | |
313 | \r | |
314 | [PcdsFixedAtBuild.X64, PcdsPatchableInModule.X64, PcdsDynamic.X64, PcdsDynamicEx.X64]\r | |
315 | ## Indicate access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.\r | |
316 | # MMIO access is always allowed regardless of the value of this PCD.\r | |
317 | # Loose of such restriction is only required by RAS components in X64 platforms.\r | |
318 | # The PCD value is considered as constantly TRUE in IA32 platforms.\r | |
319 | # When the PCD value is TRUE, page table is initialized to cover all memory spaces\r | |
320 | # and the memory occupied by page table is protected by page table itself as read-only.\r | |
321 | # In X64 build, it cannot be enabled at the same time with SMM profile feature (PcdCpuSmmProfileEnable).\r | |
322 | # In X64 build, it could not be enabled also at the same time with heap guard feature for SMM\r | |
323 | # (PcdHeapGuardPropertyMask in MdeModulePkg).\r | |
324 | # In IA32 build, page table memory is not marked as read-only when either SMM profile feature (PcdCpuSmmProfileEnable)\r | |
325 | # or heap guard feature for SMM (PcdHeapGuardPropertyMask in MdeModulePkg) is enabled.\r | |
326 | # TRUE - Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.<BR>\r | |
327 | # FALSE - Access to any type of non-SMRAM memory after SmmReadyToLock is allowed.<BR>\r | |
328 | # @Prompt Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.\r | |
329 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F\r | |
330 | \r | |
331 | [PcdsDynamic, PcdsDynamicEx]\r | |
332 | ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.\r | |
333 | # @Prompt The pointer to a CPU S3 data buffer.\r | |
334 | # @ValidList 0x80000001 | 0\r | |
335 | gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0x0|UINT64|0x60000010\r | |
336 | \r | |
337 | ## Contains the pointer to a CPU Hot Plug Data structure if CPU hot-plug is supported.\r | |
338 | # @Prompt The pointer to CPU Hot Plug Data.\r | |
339 | # @ValidList 0x80000001 | 0\r | |
340 | gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress|0x0|UINT64|0x60000011\r | |
341 | \r | |
342 | ## Indicates processor feature capabilities, each bit corresponding to a specific feature.\r | |
343 | # @Prompt Processor feature capabilities.\r | |
344 | # @ValidList 0x80000001 | 0\r | |
345 | gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000018\r | |
346 | \r | |
347 | ## As input, specifies user's desired settings for enabling/disabling processor features.\r | |
348 | ## As output, specifies actual settings for processor features, each bit corresponding to a specific feature.\r | |
349 | # @Prompt As input, specifies user's desired processor feature settings. As output, specifies actual processor feature settings.\r | |
350 | # @ValidList 0x80000001 | 0\r | |
351 | gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000019\r | |
352 | \r | |
353 | ## Contains the size of memory required when CPU processor trace is enabled.<BR><BR>\r | |
354 | # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>\r | |
355 | # This PCD is ignored if CPU processor trace is disabled.<BR><BR>\r | |
356 | # Default value is 0x00 which means 4KB of memory is allocated if CPU processor trace is enabled.<BR>\r | |
357 | # 0x0 - 4K.<BR>\r | |
358 | # 0x1 - 8K.<BR>\r | |
359 | # 0x2 - 16K.<BR>\r | |
360 | # 0x3 - 32K.<BR>\r | |
361 | # 0x4 - 64K.<BR>\r | |
362 | # 0x5 - 128K.<BR>\r | |
363 | # 0x6 - 256K.<BR>\r | |
364 | # 0x7 - 512K.<BR>\r | |
365 | # 0x8 - 1M.<BR>\r | |
366 | # 0x9 - 2M.<BR>\r | |
367 | # 0xA - 4M.<BR>\r | |
368 | # 0xB - 8M.<BR>\r | |
369 | # 0xC - 16M.<BR>\r | |
370 | # 0xD - 32M.<BR>\r | |
371 | # 0xE - 64M.<BR>\r | |
372 | # 0xF - 128M.<BR>\r | |
373 | # @Prompt The memory size used for processor trace if processor trace is enabled.\r | |
374 | # @ValidRange 0x80000001 | 0 - 0xF\r | |
375 | gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize|0x0|UINT32|0x60000012\r | |
376 | \r | |
377 | ## Contains the processor trace output scheme when CPU processor trace is enabled.<BR><BR>\r | |
378 | # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>\r | |
379 | # This PCD is ignored if CPU processor trace is disabled.<BR><BR>\r | |
380 | # Default value is 0 which means single range output scheme will be used if CPU processor trace is enabled.<BR>\r | |
381 | # 0 - Single Range output scheme.<BR>\r | |
382 | # 1 - ToPA(Table of physical address) scheme.<BR>\r | |
383 | # @Prompt The processor trace output scheme used when processor trace is enabled.\r | |
384 | # @ValidRange 0x80000001 | 0 - 1\r | |
385 | gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme|0x0|UINT8|0x60000015\r | |
386 | \r | |
387 | ## This dynamic PCD indicates whether SEV-ES is enabled\r | |
388 | # TRUE - SEV-ES is enabled\r | |
389 | # FALSE - SEV-ES is not enabled\r | |
390 | # @Prompt SEV-ES Status\r | |
391 | gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|FALSE|BOOLEAN|0x60000016\r | |
392 | \r | |
393 | [UserExtensions.TianoCore."ExtraFiles"]\r | |
394 | UefiCpuPkgExtra.uni\r |