ArmPkg/ArmPkg.dec

   1 #/** @file
   2 # ARM processor package.
   3 #
   4 # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
   5 # Copyright (c) 2011 - 2022, ARM Limited. All rights reserved.
   6 # Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
   7 #
   8 #    SPDX-License-Identifier: BSD-2-Clause-Patent
   9 #
  10 #**/
  11
  12 [Defines]
  13   DEC_SPECIFICATION              = 0x00010005
  14   PACKAGE_NAME                   = ArmPkg
  15   PACKAGE_GUID                   = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F
  16   PACKAGE_VERSION                = 0.1
  17
  18 ################################################################################
  19 #
  20 # Include Section - list of Include Paths that are provided by this package.
  21 #                   Comments are used for Keywords and Module Types.
  22 #
  23 # Supported Module Types:
  24 #  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
  25 #
  26 ################################################################################
  27 [Includes.common]
  28   Include                        # Root include for the package
  29
  30 [LibraryClasses.common]
  31   ##  @libraryclass  Convert Arm instructions to a human readable format.
  32   #
  33   ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
  34
  35   ##  @libraryclass  Provides an interface to Arm generic counters.
  36   #
  37   ArmGenericTimerCounterLib|Include/Library/ArmGenericTimerCounterLib.h
  38
  39   ##  @libraryclass  Provides an interface to initialize a
  40   #   Generic Interrupt Controller (GIC).
  41   #
  42   ArmGicArchLib|Include/Library/ArmGicArchLib.h
  43
  44   ##  @libraryclass  Provides a Generic Interrupt Controller (GIC)
  45   #   configuration interface.
  46   #
  47   ArmGicLib|Include/Library/ArmGicLib.h
  48
  49   ##  @libraryclass  Provides a HyperVisor Call (HVC) interface.
  50   #
  51   ArmHvcLib|Include/Library/ArmHvcLib.h
  52
  53   ##  @libraryclass  Provides an interface to Arm registers.
  54   #
  55   ArmLib|Include/Library/ArmLib.h
  56
  57   ##  @libraryclass  Provides a Mmu interface.
  58   #
  59   ArmMmuLib|Include/Library/ArmMmuLib.h
  60
  61   ##  @libraryclass  Provides a Mailbox Transport Layer (MTL) interface
  62   #   for the System Control and Management Interface (SCMI).
  63   #
  64   ArmMtlLib|Include/Library/ArmMtlLib.h
  65
  66   ##  @libraryclass  Provides a System Monitor Call (SMC) interface.
  67   #
  68   ArmSmcLib|Include/Library/ArmSmcLib.h
  69
  70   ##  @libraryclass  Provides a SuperVisor Call (SVC) interface.
  71   #
  72   ArmSvcLib|Include/Library/ArmSvcLib.h
  73
  74   ##  @libraryclass  Provides a default exception handler.
  75   #
  76   DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
  77
  78   ##  @libraryclass  Provides an interface to query miscellaneous OEM
  79   #   information.
  80   #
  81   OemMiscLib|Include/Library/OemMiscLib.h
  82
  83   ##  @libraryclass  Provides an OpTee interface.
  84   #
  85   OpteeLib|Include/Library/OpteeLib.h
  86
  87   ##  @libraryclass  Provides a semihosting interface.
  88   #
  89   SemihostLib|Include/Library/SemihostLib.h
  90
  91   ##  @libraryclass  Provides an interface for a StandaloneMm Mmu.
  92   #
  93   StandaloneMmMmuLib|Include/Library/StandaloneMmMmuLib.h
  94
  95 [Guids.common]
  96   gArmTokenSpaceGuid       = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }
  97
  98   ## ARM MPCore table
  99   # Include/Guid/ArmMpCoreInfo.h
 100   gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5,  {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }
 101
 102   gArmMmuReplaceLiveTranslationEntryFuncGuid = { 0xa8b50ff3, 0x08ec, 0x4dd3, {0xbf, 0x04, 0x28, 0xbf, 0x71, 0x75, 0xc7, 0x4a} }
 103
 104 [Protocols.common]
 105   ## Arm System Control and Management Interface(SCMI) Base protocol
 106   ## ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h
 107   gArmScmiBaseProtocolGuid = { 0xd7e5abe9, 0x33ab, 0x418e, { 0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f } }
 108
 109   ## Arm System Control and Management Interface(SCMI) Clock management protocol
 110   ## ArmPkg/Include/Protocol/ArmScmiClockProtocol.h
 111   gArmScmiClockProtocolGuid = { 0x91ce67a8, 0xe0aa, 0x4012, { 0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa } }
 112   gArmScmiClock2ProtocolGuid = { 0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } }
 113
 114   ## Arm System Control and Management Interface(SCMI) Clock management protocol
 115   ## ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h
 116   gArmScmiPerformanceProtocolGuid = { 0x9b8ba84, 0x3dd3, 0x49a6, { 0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad } }
 117
 118 [Ppis]
 119   ## Include/Ppi/ArmMpCoreInfo.h
 120   gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }
 121
 122 [PcdsFeatureFlag.common]
 123   gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001
 124
 125   # On ARM Architecture with the Security Extension, the address for the
 126   # Vector Table can be mapped anywhere in the memory map. It means we can
 127   # point the Exception Vector Table to its location in CpuDxe.
 128   # By default we copy the Vector Table at  PcdGet64(PcdCpuVectorBaseAddress)
 129   gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022
 130   # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before
 131   # it has been configured by the CPU DXE
 132   gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032
 133
 134   # Define if the GICv3 controller should use the GICv2 legacy
 135   gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042
 136
 137   ## Define the conduit to use for monitor calls.
 138   # Default PcdMonitorConduitHvc = FALSE, conduit = SMC
 139   # If PcdMonitorConduitHvc = TRUE, conduit = HVC
 140   gArmTokenSpaceGuid.PcdMonitorConduitHvc|FALSE|BOOLEAN|0x00000047
 141
 142 [PcdsFeatureFlag.ARM]
 143   # Whether to map normal memory as non-shareable. FALSE is the safe choice, but
 144   # TRUE may be appropriate to fix performance problems if you don't care about
 145   # hardware coherency (i.e., no virtualization or cache coherent DMA)
 146   gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043
 147
 148 [PcdsFeatureFlag.AARCH64, PcdsFeatureFlag.ARM]
 149   ## Used to select method for requesting services from S-EL1.<BR><BR>
 150   #   TRUE  - Selects FF-A calls for communication between S-EL0 and SPMC.<BR>
 151   #   FALSE - Selects SVC calls for communication between S-EL0 and SPMC.<BR>
 152   # @Prompt Enable FF-A support.
 153   gArmTokenSpaceGuid.PcdFfaEnable|FALSE|BOOLEAN|0x0000005B
 154
 155 [PcdsFixedAtBuild.common]
 156   gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
 157
 158   # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.
 159   # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
 160   gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024
 161
 162   gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004
 163   gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005
 164
 165   #
 166   # ARM Secure Firmware PCDs
 167   #
 168   gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015
 169   gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016
 170   gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F
 171   gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030
 172
 173   #
 174   # ARM Hypervisor Firmware PCDs
 175   #
 176   gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A
 177   gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B
 178   gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C
 179   gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D
 180
 181   # Use ClusterId + CoreId to identify the PrimaryCore
 182   gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031
 183   # The Primary Core is ClusterId[0] & CoreId[0]
 184   gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037
 185
 186   #
 187   # SMBIOS PCDs
 188   #
 189   gArmTokenSpaceGuid.PcdSystemProductName|L""|VOID*|0x30000053
 190   gArmTokenSpaceGuid.PcdSystemVersion|L""|VOID*|0x30000054
 191   gArmTokenSpaceGuid.PcdBaseBoardManufacturer|L""|VOID*|0x30000055
 192   gArmTokenSpaceGuid.PcdBaseBoardProductName|L""|VOID*|0x30000056
 193   gArmTokenSpaceGuid.PcdBaseBoardVersion|L""|VOID*|0x30000057
 194   gArmTokenSpaceGuid.PcdProcessorManufacturer|L""|VOID*|0x30000071
 195   gArmTokenSpaceGuid.PcdProcessorVersion|L""|VOID*|0x30000072
 196   gArmTokenSpaceGuid.PcdProcessorSerialNumber|L""|VOID*|0x30000073
 197   gArmTokenSpaceGuid.PcdProcessorAssetTag|L""|VOID*|0x30000074
 198   gArmTokenSpaceGuid.PcdProcessorPartNumber|L""|VOID*|0x30000075
 199
 200   #
 201   # ARM L2x0 PCDs
 202   #
 203   gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B
 204
 205   #
 206   # ARM Normal (or Non Secure) Firmware PCDs
 207   #
 208   gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C
 209   gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E
 210
 211   #
 212   # Value to add to a host address to obtain a device address, using
 213   # unsigned 64-bit integer arithmetic on both ARM and AArch64. This
 214   # means we can rely on truncation on overflow to specify negative
 215   # offsets.
 216   #
 217   gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044
 218
 219 [PcdsFixedAtBuild.common, PcdsPatchableInModule.common]
 220   gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B
 221   gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D
 222
 223 [PcdsFixedAtBuild.ARM]
 224   #
 225   # ARM Security Extension
 226   #
 227
 228   # Secure Configuration Register
 229   # - BIT0 : NS - Non Secure bit
 230   # - BIT1 : IRQ Handler
 231   # - BIT2 : FIQ Handler
 232   # - BIT3 : EA - External Abort
 233   # - BIT4 : FW - F bit writable
 234   # - BIT5 : AW - A bit writable
 235   # - BIT6 : nET - Not Early Termination
 236   # - BIT7 : SCD - Secure Monitor Call Disable
 237   # - BIT8 : HCE - Hyp Call enable
 238   # - BIT9 : SIF - Secure Instruction Fetch
 239   # 0x31 = NS | EA | FW
 240   gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038
 241
 242   # By default we do not do a transition to non-secure mode
 243   gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E
 244
 245   # Non Secure Access Control Register
 246   # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality
 247   # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31
 248   # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable
 249   # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable
 250   # 0xC00 = cp10 | cp11
 251   gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039
 252
 253 [PcdsFixedAtBuild.AARCH64]
 254   #
 255   # AArch64 Security Extension
 256   #
 257
 258   # Secure Configuration Register
 259   # - BIT0 : NS - Non Secure bit
 260   # - BIT1 : IRQ Handler
 261   # - BIT2 : FIQ Handler
 262   # - BIT3 : EA - External Abort
 263   # - BIT4 : FW - F bit writable
 264   # - BIT5 : AW - A bit writable
 265   # - BIT6 : nET - Not Early Termination
 266   # - BIT7 : SCD - Secure Monitor Call Disable
 267   # - BIT8 : HCE - Hyp Call enable
 268   # - BIT9 : SIF - Secure Instruction Fetch
 269   # - BIT10: RW -  Register width control for lower exception levels
 270   # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer
 271   # - BIT12: TWI - Trap WFI
 272   # - BIT13: TWE - Trap WFE
 273   # 0x501 = NS | HCE | RW
 274   gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038
 275
 276   # By default we do transition to EL2 non-secure mode with Stack for EL2.
 277   #        Mode Description              Bits
 278   # NS EL2 SP2 all interrupts disabled =  0x3c9
 279   # NS EL1 SP1 all interrupts disabled =  0x3c5
 280   # Other modes include using SP0 or switching to Aarch32, but these are
 281   # not currently supported.
 282   gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E
 283
 284
 285 #
 286 # These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be
 287 # redefined when using UEFI in a context of virtual machine.
 288 #
 289 [PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]
 290
 291   # System Memory (DRAM): These PCDs define the region of in-built system memory
 292   # Some platforms can get DRAM extensions, these additional regions may be
 293   # declared to UEFI using separate resource descriptor HOBs
 294   gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029
 295   gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A
 296
 297   gArmTokenSpaceGuid.PcdMmBufferBase|0|UINT64|0x00000045
 298   gArmTokenSpaceGuid.PcdMmBufferSize|0|UINT64|0x00000046
 299
 300   gArmTokenSpaceGuid.PcdSystemBiosRelease|0xFFFF|UINT16|0x30000058
 301   gArmTokenSpaceGuid.PcdEmbeddedControllerFirmwareRelease|0xFFFF|UINT16|0x30000059
 302
 303 [PcdsFixedAtBuild.common, PcdsDynamic.common]
 304   #
 305   # ARM Architectural Timer
 306   #
 307   gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034
 308
 309   # ARM Architectural Timer Interrupt(GIC PPI) numbers
 310   gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035
 311   gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036
 312   gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040
 313   gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041
 314
 315   #
 316   # ARM Generic Watchdog
 317   #
 318
 319   gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007
 320   gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008
 321   gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009
 322
 323   #
 324   # ARM Generic Interrupt Controller
 325   #
 326   gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C
 327   # Base address for the GIC Redistributor region that contains the boot CPU
 328   gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E
 329   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D
 330   gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025
 331
 332   #
 333   # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.
 334   # Note that "IO" is just another MMIO range that simulates IO space; there
 335   # are no special instructions to access it.
 336   #
 337   # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are
 338   # specific to their containing address spaces. In order to get the physical
 339   # address for the CPU, for a given access, the respective translation value
 340   # has to be added.
 341   #
 342   # The translations always have to be initialized like this, using UINT64:
 343   #
 344   #   UINT64 IoCpuBase;     // mapping target in 64-bit cpu-physical space
 345   #   UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space
 346   #   UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space
 347   #
 348   #   gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;
 349   #   gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;
 350   #   gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;
 351   #
 352   # because (a) the target address space (ie. the cpu-physical space) is
 353   # 64-bit, and (b) the translation values are meant as offsets for *modular*
 354   # arithmetic.
 355   #
 356   # Accordingly, the translation itself needs to be implemented as:
 357   #
 358   #   UINT64 UntranslatedIoAddress;     // input parameter
 359   #   UINT32 UntranslatedMmio32Address; // input parameter
 360   #   UINT64 UntranslatedMmio64Address; // input parameter
 361   #
 362   #   UINT64 TranslatedIoAddress;       // output parameter
 363   #   UINT64 TranslatedMmio32Address;   // output parameter
 364   #   UINT64 TranslatedMmio64Address;   // output parameter
 365   #
 366   #   TranslatedIoAddress     = UntranslatedIoAddress +
 367   #                             gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation;
 368   #   TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +
 369   #                             gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation;
 370   #   TranslatedMmio64Address = UntranslatedMmio64Address +
 371   #                             gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation;
 372   #
 373   #  The modular arithmetic performed in UINT64 ensures that the translation
 374   #  works correctly regardless of the relation between IoCpuBase and
 375   #  PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and
 376   #  PcdPciMmio64Base.
 377   #
 378   gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050
 379   gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051
 380   gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053
 381   gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054
 382   gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056
 383   gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057
 384
 385   #
 386   # Inclusive range of allowed PCI buses.
 387   #
 388   gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059
 389   gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A
 390
 391 [PcdsDynamicEx]
 392   #
 393   # This dynamic PCD hold the GUID of a firmware FFS which contains
 394   # the LinuxBoot payload.
 395   #
 396   gArmTokenSpaceGuid.PcdLinuxBootFileGuid|{0x0}|VOID*|0x0000005C