ArmPkg/ArmPkg.dec

   1 #/** @file
   2 # ARM processor package.
   3 #
   4 # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
   5 # Copyright (c) 2011 - 2022, ARM Limited. All rights reserved.
   6 # Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
   7 #
   8 #    SPDX-License-Identifier: BSD-2-Clause-Patent
   9 #
  10 #**/
  11
  12 [Defines]
  13   DEC_SPECIFICATION              = 0x00010005
  14   PACKAGE_NAME                   = ArmPkg
  15   PACKAGE_GUID                   = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F
  16   PACKAGE_VERSION                = 0.1
  17
  18 ################################################################################
  19 #
  20 # Include Section - list of Include Paths that are provided by this package.
  21 #                   Comments are used for Keywords and Module Types.
  22 #
  23 # Supported Module Types:
  24 #  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
  25 #
  26 ################################################################################
  27 [Includes.common]
  28   Include                        # Root include for the package
  29
  30 [LibraryClasses.common]
  31   ##  @libraryclass  Convert Arm instructions to a human readable format.
  32   #
  33   ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
  34
  35   ##  @libraryclass  Provides an interface to Arm generic counters.
  36   #
  37   ArmGenericTimerCounterLib|Include/Library/ArmGenericTimerCounterLib.h
  38
  39   ##  @libraryclass  Provides an interface to initialize a
  40   #   Generic Interrupt Controller (GIC).
  41   #
  42   ArmGicArchLib|Include/Library/ArmGicArchLib.h
  43
  44   ##  @libraryclass  Provides a Generic Interrupt Controller (GIC)
  45   #   configuration interface.
  46   #
  47   ArmGicLib|Include/Library/ArmGicLib.h
  48
  49   ##  @libraryclass  Provides a HyperVisor Call (HVC) interface.
  50   #
  51   ArmHvcLib|Include/Library/ArmHvcLib.h
  52
  53   ##  @libraryclass  Provides an interface to Arm registers.
  54   #
  55   ArmLib|Include/Library/ArmLib.h
  56
  57   ##  @libraryclass  Provides a Mmu interface.
  58   #
  59   ArmMmuLib|Include/Library/ArmMmuLib.h
  60
  61   ##  @libraryclass  Provides a Mailbox Transport Layer (MTL) interface
  62   #   for the System Control and Management Interface (SCMI).
  63   #
  64   ArmMtlLib|Include/Library/ArmMtlLib.h
  65
  66   ##  @libraryclass  Provides a System Monitor Call (SMC) interface.
  67   #
  68   ArmSmcLib|Include/Library/ArmSmcLib.h
  69
  70   ##  @libraryclass  Provides a SuperVisor Call (SVC) interface.
  71   #
  72   ArmSvcLib|Include/Library/ArmSvcLib.h
  73
  74   ##  @libraryclass  Provides a Monitor Call interface that will use the
  75   #   default conduit (HVC or SMC).
  76   #
  77   ArmMonitorLib|Include/Library/ArmMonitorLib.h
  78
  79   ##  @libraryclass  Provides a default exception handler.
  80   #
  81   DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
  82
  83   ##  @libraryclass  Provides an interface to query miscellaneous OEM
  84   #   information.
  85   #
  86   OemMiscLib|Include/Library/OemMiscLib.h
  87
  88   ##  @libraryclass  Provides an OpTee interface.
  89   #
  90   OpteeLib|Include/Library/OpteeLib.h
  91
  92   ##  @libraryclass  Provides a semihosting interface.
  93   #
  94   SemihostLib|Include/Library/SemihostLib.h
  95
  96   ##  @libraryclass  Provides an interface for a StandaloneMm Mmu.
  97   #
  98   StandaloneMmMmuLib|Include/Library/StandaloneMmMmuLib.h
  99
 100 [Guids.common]
 101   gArmTokenSpaceGuid       = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }
 102
 103   ## ARM MPCore table
 104   # Include/Guid/ArmMpCoreInfo.h
 105   gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5,  {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }
 106
 107   gArmMmuReplaceLiveTranslationEntryFuncGuid = { 0xa8b50ff3, 0x08ec, 0x4dd3, {0xbf, 0x04, 0x28, 0xbf, 0x71, 0x75, 0xc7, 0x4a} }
 108
 109 [Protocols.common]
 110   ## Arm System Control and Management Interface(SCMI) Base protocol
 111   ## ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h
 112   gArmScmiBaseProtocolGuid = { 0xd7e5abe9, 0x33ab, 0x418e, { 0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f } }
 113
 114   ## Arm System Control and Management Interface(SCMI) Clock management protocol
 115   ## ArmPkg/Include/Protocol/ArmScmiClockProtocol.h
 116   gArmScmiClockProtocolGuid = { 0x91ce67a8, 0xe0aa, 0x4012, { 0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa } }
 117   gArmScmiClock2ProtocolGuid = { 0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } }
 118
 119   ## Arm System Control and Management Interface(SCMI) Clock management protocol
 120   ## ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h
 121   gArmScmiPerformanceProtocolGuid = { 0x9b8ba84, 0x3dd3, 0x49a6, { 0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad } }
 122
 123 [Ppis]
 124   ## Include/Ppi/ArmMpCoreInfo.h
 125   gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }
 126
 127 [PcdsFeatureFlag.common]
 128   gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001
 129
 130   # On ARM Architecture with the Security Extension, the address for the
 131   # Vector Table can be mapped anywhere in the memory map. It means we can
 132   # point the Exception Vector Table to its location in CpuDxe.
 133   # By default we copy the Vector Table at  PcdGet64(PcdCpuVectorBaseAddress)
 134   gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022
 135   # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before
 136   # it has been configured by the CPU DXE
 137   gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032
 138
 139   # Define if the GICv3 controller should use the GICv2 legacy
 140   gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042
 141
 142   ## Define the conduit to use for monitor calls.
 143   # Default PcdMonitorConduitHvc = FALSE, conduit = SMC
 144   # If PcdMonitorConduitHvc = TRUE, conduit = HVC
 145   gArmTokenSpaceGuid.PcdMonitorConduitHvc|FALSE|BOOLEAN|0x00000047
 146
 147 [PcdsFeatureFlag.ARM]
 148   # Whether to map normal memory as non-shareable. FALSE is the safe choice, but
 149   # TRUE may be appropriate to fix performance problems if you don't care about
 150   # hardware coherency (i.e., no virtualization or cache coherent DMA)
 151   gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043
 152
 153 [PcdsFeatureFlag.AARCH64, PcdsFeatureFlag.ARM]
 154   ## Used to select method for requesting services from S-EL1.<BR><BR>
 155   #   TRUE  - Selects FF-A calls for communication between S-EL0 and SPMC.<BR>
 156   #   FALSE - Selects SVC calls for communication between S-EL0 and SPMC.<BR>
 157   # @Prompt Enable FF-A support.
 158   gArmTokenSpaceGuid.PcdFfaEnable|FALSE|BOOLEAN|0x0000005B
 159
 160 [PcdsFixedAtBuild.common]
 161   gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
 162
 163   # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.
 164   # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
 165   gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024
 166
 167   gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004
 168   gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005
 169
 170   #
 171   # ARM Secure Firmware PCDs
 172   #
 173   gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015
 174   gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016
 175   gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F
 176   gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030
 177
 178   #
 179   # ARM Hypervisor Firmware PCDs
 180   #
 181   gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A
 182   gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B
 183   gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C
 184   gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D
 185
 186   # Use ClusterId + CoreId to identify the PrimaryCore
 187   gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031
 188   # The Primary Core is ClusterId[0] & CoreId[0]
 189   gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037
 190
 191   #
 192   # SMBIOS PCDs
 193   #
 194   gArmTokenSpaceGuid.PcdSystemProductName|L""|VOID*|0x30000053
 195   gArmTokenSpaceGuid.PcdSystemVersion|L""|VOID*|0x30000054
 196   gArmTokenSpaceGuid.PcdBaseBoardManufacturer|L""|VOID*|0x30000055
 197   gArmTokenSpaceGuid.PcdBaseBoardProductName|L""|VOID*|0x30000056
 198   gArmTokenSpaceGuid.PcdBaseBoardVersion|L""|VOID*|0x30000057
 199   gArmTokenSpaceGuid.PcdProcessorManufacturer|L""|VOID*|0x30000071
 200   gArmTokenSpaceGuid.PcdProcessorVersion|L""|VOID*|0x30000072
 201   gArmTokenSpaceGuid.PcdProcessorSerialNumber|L""|VOID*|0x30000073
 202   gArmTokenSpaceGuid.PcdProcessorAssetTag|L""|VOID*|0x30000074
 203   gArmTokenSpaceGuid.PcdProcessorPartNumber|L""|VOID*|0x30000075
 204
 205   #
 206   # ARM L2x0 PCDs
 207   #
 208   gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B
 209
 210   #
 211   # ARM Normal (or Non Secure) Firmware PCDs
 212   #
 213   gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C
 214   gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E
 215
 216   #
 217   # Value to add to a host address to obtain a device address, using
 218   # unsigned 64-bit integer arithmetic on both ARM and AArch64. This
 219   # means we can rely on truncation on overflow to specify negative
 220   # offsets.
 221   #
 222   gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044
 223
 224 [PcdsFixedAtBuild.common, PcdsPatchableInModule.common]
 225   gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B
 226   gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D
 227
 228 [PcdsFixedAtBuild.ARM]
 229   #
 230   # ARM Security Extension
 231   #
 232
 233   # Secure Configuration Register
 234   # - BIT0 : NS - Non Secure bit
 235   # - BIT1 : IRQ Handler
 236   # - BIT2 : FIQ Handler
 237   # - BIT3 : EA - External Abort
 238   # - BIT4 : FW - F bit writable
 239   # - BIT5 : AW - A bit writable
 240   # - BIT6 : nET - Not Early Termination
 241   # - BIT7 : SCD - Secure Monitor Call Disable
 242   # - BIT8 : HCE - Hyp Call enable
 243   # - BIT9 : SIF - Secure Instruction Fetch
 244   # 0x31 = NS | EA | FW
 245   gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038
 246
 247   # By default we do not do a transition to non-secure mode
 248   gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E
 249
 250   # Non Secure Access Control Register
 251   # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality
 252   # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31
 253   # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable
 254   # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable
 255   # 0xC00 = cp10 | cp11
 256   gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039
 257
 258 [PcdsFixedAtBuild.AARCH64]
 259   #
 260   # AArch64 Security Extension
 261   #
 262
 263   # Secure Configuration Register
 264   # - BIT0 : NS - Non Secure bit
 265   # - BIT1 : IRQ Handler
 266   # - BIT2 : FIQ Handler
 267   # - BIT3 : EA - External Abort
 268   # - BIT4 : FW - F bit writable
 269   # - BIT5 : AW - A bit writable
 270   # - BIT6 : nET - Not Early Termination
 271   # - BIT7 : SCD - Secure Monitor Call Disable
 272   # - BIT8 : HCE - Hyp Call enable
 273   # - BIT9 : SIF - Secure Instruction Fetch
 274   # - BIT10: RW -  Register width control for lower exception levels
 275   # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer
 276   # - BIT12: TWI - Trap WFI
 277   # - BIT13: TWE - Trap WFE
 278   # 0x501 = NS | HCE | RW
 279   gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038
 280
 281   # By default we do transition to EL2 non-secure mode with Stack for EL2.
 282   #        Mode Description              Bits
 283   # NS EL2 SP2 all interrupts disabled =  0x3c9
 284   # NS EL1 SP1 all interrupts disabled =  0x3c5
 285   # Other modes include using SP0 or switching to Aarch32, but these are
 286   # not currently supported.
 287   gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E
 288
 289
 290 #
 291 # These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be
 292 # redefined when using UEFI in a context of virtual machine.
 293 #
 294 [PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]
 295
 296   # System Memory (DRAM): These PCDs define the region of in-built system memory
 297   # Some platforms can get DRAM extensions, these additional regions may be
 298   # declared to UEFI using separate resource descriptor HOBs
 299   gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029
 300   gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A
 301
 302   gArmTokenSpaceGuid.PcdMmBufferBase|0|UINT64|0x00000045
 303   gArmTokenSpaceGuid.PcdMmBufferSize|0|UINT64|0x00000046
 304
 305   gArmTokenSpaceGuid.PcdSystemBiosRelease|0xFFFF|UINT16|0x30000058
 306   gArmTokenSpaceGuid.PcdEmbeddedControllerFirmwareRelease|0xFFFF|UINT16|0x30000059
 307
 308 [PcdsFixedAtBuild.common, PcdsDynamic.common]
 309   #
 310   # ARM Architectural Timer
 311   #
 312   gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034
 313
 314   # ARM Architectural Timer Interrupt(GIC PPI) numbers
 315   gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035
 316   gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036
 317   gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040
 318   gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041
 319
 320   #
 321   # ARM Generic Watchdog
 322   #
 323
 324   gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007
 325   gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008
 326   gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009
 327
 328   #
 329   # ARM Generic Interrupt Controller
 330   #
 331   gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C
 332   # Base address for the GIC Redistributor region that contains the boot CPU
 333   gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E
 334   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D
 335   gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025
 336
 337   #
 338   # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.
 339   # Note that "IO" is just another MMIO range that simulates IO space; there
 340   # are no special instructions to access it.
 341   #
 342   # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are
 343   # specific to their containing address spaces. In order to get the physical
 344   # address for the CPU, for a given access, the respective translation value
 345   # has to be added.
 346   #
 347   # The translations always have to be initialized like this, using UINT64:
 348   #
 349   #   UINT64 IoCpuBase;     // mapping target in 64-bit cpu-physical space
 350   #   UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space
 351   #   UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space
 352   #
 353   #   gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;
 354   #   gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;
 355   #   gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;
 356   #
 357   # because (a) the target address space (ie. the cpu-physical space) is
 358   # 64-bit, and (b) the translation values are meant as offsets for *modular*
 359   # arithmetic.
 360   #
 361   # Accordingly, the translation itself needs to be implemented as:
 362   #
 363   #   UINT64 UntranslatedIoAddress;     // input parameter
 364   #   UINT32 UntranslatedMmio32Address; // input parameter
 365   #   UINT64 UntranslatedMmio64Address; // input parameter
 366   #
 367   #   UINT64 TranslatedIoAddress;       // output parameter
 368   #   UINT64 TranslatedMmio32Address;   // output parameter
 369   #   UINT64 TranslatedMmio64Address;   // output parameter
 370   #
 371   #   TranslatedIoAddress     = UntranslatedIoAddress +
 372   #                             gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation;
 373   #   TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +
 374   #                             gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation;
 375   #   TranslatedMmio64Address = UntranslatedMmio64Address +
 376   #                             gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation;
 377   #
 378   #  The modular arithmetic performed in UINT64 ensures that the translation
 379   #  works correctly regardless of the relation between IoCpuBase and
 380   #  PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and
 381   #  PcdPciMmio64Base.
 382   #
 383   gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050
 384   gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051
 385   gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053
 386   gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054
 387   gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056
 388   gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057
 389
 390   #
 391   # Inclusive range of allowed PCI buses.
 392   #
 393   gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059
 394   gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A
 395
 396 [PcdsDynamicEx]
 397   #
 398   # This dynamic PCD hold the GUID of a firmware FFS which contains
 399   # the LinuxBoot payload.
 400   #
 401   gArmTokenSpaceGuid.PcdLinuxBootFileGuid|{0x0}|VOID*|0x0000005C