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[mirror_edk2.git] / ArmPkg / ArmPkg.dec
1 #/** @file
2 # ARM processor package.
3 #
4 # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
5 # Copyright (c) 2011 - 2021, ARM Limited. All rights reserved.
6 # Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
7 #
8 # SPDX-License-Identifier: BSD-2-Clause-Patent
9 #
10 #**/
11
12 [Defines]
13 DEC_SPECIFICATION = 0x00010005
14 PACKAGE_NAME = ArmPkg
15 PACKAGE_GUID = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F
16 PACKAGE_VERSION = 0.1
17
18 ################################################################################
19 #
20 # Include Section - list of Include Paths that are provided by this package.
21 # Comments are used for Keywords and Module Types.
22 #
23 # Supported Module Types:
24 # BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
25 #
26 ################################################################################
27 [Includes.common]
28 Include # Root include for the package
29
30 [LibraryClasses.common]
31 ## @libraryclass Convert Arm instructions to a human readable format.
32 #
33 ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
34
35 ## @libraryclass Provides an interface to Arm generic counters.
36 #
37 ArmGenericTimerCounterLib|Include/Library/ArmGenericTimerCounterLib.h
38
39 ## @libraryclass Provides an interface to initialize a
40 # Generic Interrupt Controller (GIC).
41 #
42 ArmGicArchLib|Include/Library/ArmGicArchLib.h
43
44 ## @libraryclass Provides a Generic Interrupt Controller (GIC)
45 # configuration interface.
46 #
47 ArmGicLib|Include/Library/ArmGicLib.h
48
49 ## @libraryclass Provides a HyperVisor Call (HVC) interface.
50 #
51 ArmHvcLib|Include/Library/ArmHvcLib.h
52
53 ## @libraryclass Provides an interface to Arm registers.
54 #
55 ArmLib|Include/Library/ArmLib.h
56
57 ## @libraryclass Provides a Mmu interface.
58 #
59 ArmMmuLib|Include/Library/ArmMmuLib.h
60
61 ## @libraryclass Provides a Mailbox Transport Layer (MTL) interface
62 # for the System Control and Management Interface (SCMI).
63 #
64 ArmMtlLib|Include/Library/ArmMtlLib.h
65
66 ## @libraryclass Provides a System Monitor Call (SMC) interface.
67 #
68 ArmSmcLib|Include/Library/ArmSmcLib.h
69
70 ## @libraryclass Provides a SuperVisor Call (SVC) interface.
71 #
72 ArmSvcLib|Include/Library/ArmSvcLib.h
73
74 ## @libraryclass Provides a default exception handler.
75 #
76 DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
77
78 ## @libraryclass Provides an interface to query miscellaneous OEM
79 # information.
80 #
81 OemMiscLib|Include/Library/OemMiscLib.h
82
83 ## @libraryclass Provides an OpTee interface.
84 #
85 OpteeLib|Include/Library/OpteeLib.h
86
87 ## @libraryclass Provides a semihosting interface.
88 #
89 SemihostLib|Include/Library/SemihostLib.h
90
91 ## @libraryclass Provides an interface for a StandaloneMm Mmu.
92 #
93 StandaloneMmMmuLib|Include/Library/StandaloneMmMmuLib.h
94
95 [Guids.common]
96 gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }
97
98 ## ARM MPCore table
99 # Include/Guid/ArmMpCoreInfo.h
100 gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }
101
102 [Protocols.common]
103 ## Arm System Control and Management Interface(SCMI) Base protocol
104 ## ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h
105 gArmScmiBaseProtocolGuid = { 0xd7e5abe9, 0x33ab, 0x418e, { 0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f } }
106
107 ## Arm System Control and Management Interface(SCMI) Clock management protocol
108 ## ArmPkg/Include/Protocol/ArmScmiClockProtocol.h
109 gArmScmiClockProtocolGuid = { 0x91ce67a8, 0xe0aa, 0x4012, { 0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa } }
110 gArmScmiClock2ProtocolGuid = { 0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } }
111
112 ## Arm System Control and Management Interface(SCMI) Clock management protocol
113 ## ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h
114 gArmScmiPerformanceProtocolGuid = { 0x9b8ba84, 0x3dd3, 0x49a6, { 0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad } }
115
116 [Ppis]
117 ## Include/Ppi/ArmMpCoreInfo.h
118 gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }
119
120 [PcdsFeatureFlag.common]
121 gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001
122
123 # On ARM Architecture with the Security Extension, the address for the
124 # Vector Table can be mapped anywhere in the memory map. It means we can
125 # point the Exception Vector Table to its location in CpuDxe.
126 # By default we copy the Vector Table at PcdGet64(PcdCpuVectorBaseAddress)
127 gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022
128 # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before
129 # it has been configured by the CPU DXE
130 gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032
131
132 # Define if the GICv3 controller should use the GICv2 legacy
133 gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042
134
135 [PcdsFeatureFlag.ARM]
136 # Whether to map normal memory as non-shareable. FALSE is the safe choice, but
137 # TRUE may be appropriate to fix performance problems if you don't care about
138 # hardware coherency (i.e., no virtualization or cache coherent DMA)
139 gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043
140
141 [PcdsFeatureFlag.AARCH64, PcdsFeatureFlag.ARM]
142 ## Used to select method for requesting services from S-EL1.<BR><BR>
143 # TRUE - Selects FF-A calls for communication between S-EL0 and SPMC.<BR>
144 # FALSE - Selects SVC calls for communication between S-EL0 and SPMC.<BR>
145 # @Prompt Enable FF-A support.
146 gArmTokenSpaceGuid.PcdFfaEnable|FALSE|BOOLEAN|0x0000005B
147
148 [PcdsFixedAtBuild.common]
149 gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
150
151 # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.
152 # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
153 gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024
154
155 gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004
156 gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005
157
158 #
159 # ARM Secure Firmware PCDs
160 #
161 gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015
162 gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016
163 gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F
164 gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030
165
166 #
167 # ARM Hypervisor Firmware PCDs
168 #
169 gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A
170 gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B
171 gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C
172 gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D
173
174 # Use ClusterId + CoreId to identify the PrimaryCore
175 gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031
176 # The Primary Core is ClusterId[0] & CoreId[0]
177 gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037
178
179 #
180 # SMBIOS PCDs
181 #
182 gArmTokenSpaceGuid.PcdSystemProductName|L""|VOID*|0x30000053
183 gArmTokenSpaceGuid.PcdSystemVersion|L""|VOID*|0x30000054
184 gArmTokenSpaceGuid.PcdBaseBoardManufacturer|L""|VOID*|0x30000055
185 gArmTokenSpaceGuid.PcdBaseBoardProductName|L""|VOID*|0x30000056
186 gArmTokenSpaceGuid.PcdBaseBoardVersion|L""|VOID*|0x30000057
187 gArmTokenSpaceGuid.PcdProcessorManufacturer|L""|VOID*|0x30000071
188 gArmTokenSpaceGuid.PcdProcessorVersion|L""|VOID*|0x30000072
189 gArmTokenSpaceGuid.PcdProcessorSerialNumber|L""|VOID*|0x30000073
190 gArmTokenSpaceGuid.PcdProcessorAssetTag|L""|VOID*|0x30000074
191 gArmTokenSpaceGuid.PcdProcessorPartNumber|L""|VOID*|0x30000075
192
193 #
194 # ARM L2x0 PCDs
195 #
196 gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B
197
198 #
199 # ARM Normal (or Non Secure) Firmware PCDs
200 #
201 gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C
202 gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E
203
204 #
205 # Value to add to a host address to obtain a device address, using
206 # unsigned 64-bit integer arithmetic on both ARM and AArch64. This
207 # means we can rely on truncation on overflow to specify negative
208 # offsets.
209 #
210 gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044
211
212 [PcdsFixedAtBuild.common, PcdsPatchableInModule.common]
213 gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B
214 gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D
215
216 [PcdsFixedAtBuild.ARM]
217 #
218 # ARM Security Extension
219 #
220
221 # Secure Configuration Register
222 # - BIT0 : NS - Non Secure bit
223 # - BIT1 : IRQ Handler
224 # - BIT2 : FIQ Handler
225 # - BIT3 : EA - External Abort
226 # - BIT4 : FW - F bit writable
227 # - BIT5 : AW - A bit writable
228 # - BIT6 : nET - Not Early Termination
229 # - BIT7 : SCD - Secure Monitor Call Disable
230 # - BIT8 : HCE - Hyp Call enable
231 # - BIT9 : SIF - Secure Instruction Fetch
232 # 0x31 = NS | EA | FW
233 gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038
234
235 # By default we do not do a transition to non-secure mode
236 gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E
237
238 # Non Secure Access Control Register
239 # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality
240 # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31
241 # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable
242 # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable
243 # 0xC00 = cp10 | cp11
244 gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039
245
246 [PcdsFixedAtBuild.AARCH64]
247 #
248 # AArch64 Security Extension
249 #
250
251 # Secure Configuration Register
252 # - BIT0 : NS - Non Secure bit
253 # - BIT1 : IRQ Handler
254 # - BIT2 : FIQ Handler
255 # - BIT3 : EA - External Abort
256 # - BIT4 : FW - F bit writable
257 # - BIT5 : AW - A bit writable
258 # - BIT6 : nET - Not Early Termination
259 # - BIT7 : SCD - Secure Monitor Call Disable
260 # - BIT8 : HCE - Hyp Call enable
261 # - BIT9 : SIF - Secure Instruction Fetch
262 # - BIT10: RW - Register width control for lower exception levels
263 # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer
264 # - BIT12: TWI - Trap WFI
265 # - BIT13: TWE - Trap WFE
266 # 0x501 = NS | HCE | RW
267 gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038
268
269 # By default we do transition to EL2 non-secure mode with Stack for EL2.
270 # Mode Description Bits
271 # NS EL2 SP2 all interrupts disabled = 0x3c9
272 # NS EL1 SP1 all interrupts disabled = 0x3c5
273 # Other modes include using SP0 or switching to Aarch32, but these are
274 # not currently supported.
275 gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E
276
277
278 #
279 # These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be
280 # redefined when using UEFI in a context of virtual machine.
281 #
282 [PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]
283
284 # System Memory (DRAM): These PCDs define the region of in-built system memory
285 # Some platforms can get DRAM extensions, these additional regions may be
286 # declared to UEFI using separate resource descriptor HOBs
287 gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029
288 gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A
289
290 gArmTokenSpaceGuid.PcdMmBufferBase|0|UINT64|0x00000045
291 gArmTokenSpaceGuid.PcdMmBufferSize|0|UINT64|0x00000046
292
293 gArmTokenSpaceGuid.PcdSystemBiosRelease|0xFFFF|UINT16|0x30000058
294 gArmTokenSpaceGuid.PcdEmbeddedControllerFirmwareRelease|0xFFFF|UINT16|0x30000059
295
296 [PcdsFixedAtBuild.common, PcdsDynamic.common]
297 #
298 # ARM Architectural Timer
299 #
300 gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034
301
302 # ARM Architectural Timer Interrupt(GIC PPI) numbers
303 gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035
304 gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036
305 gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040
306 gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041
307
308 #
309 # ARM Generic Watchdog
310 #
311
312 gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007
313 gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008
314 gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009
315
316 #
317 # ARM Generic Interrupt Controller
318 #
319 gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C
320 # Base address for the GIC Redistributor region that contains the boot CPU
321 gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E
322 gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D
323 gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025
324
325 #
326 # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.
327 # Note that "IO" is just another MMIO range that simulates IO space; there
328 # are no special instructions to access it.
329 #
330 # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are
331 # specific to their containing address spaces. In order to get the physical
332 # address for the CPU, for a given access, the respective translation value
333 # has to be added.
334 #
335 # The translations always have to be initialized like this, using UINT64:
336 #
337 # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space
338 # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space
339 # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space
340 #
341 # gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;
342 # gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;
343 # gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;
344 #
345 # because (a) the target address space (ie. the cpu-physical space) is
346 # 64-bit, and (b) the translation values are meant as offsets for *modular*
347 # arithmetic.
348 #
349 # Accordingly, the translation itself needs to be implemented as:
350 #
351 # UINT64 UntranslatedIoAddress; // input parameter
352 # UINT32 UntranslatedMmio32Address; // input parameter
353 # UINT64 UntranslatedMmio64Address; // input parameter
354 #
355 # UINT64 TranslatedIoAddress; // output parameter
356 # UINT64 TranslatedMmio32Address; // output parameter
357 # UINT64 TranslatedMmio64Address; // output parameter
358 #
359 # TranslatedIoAddress = UntranslatedIoAddress +
360 # gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation;
361 # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +
362 # gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation;
363 # TranslatedMmio64Address = UntranslatedMmio64Address +
364 # gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation;
365 #
366 # The modular arithmetic performed in UINT64 ensures that the translation
367 # works correctly regardless of the relation between IoCpuBase and
368 # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and
369 # PcdPciMmio64Base.
370 #
371 gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050
372 gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051
373 gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053
374 gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054
375 gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056
376 gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057
377
378 #
379 # Inclusive range of allowed PCI buses.
380 #
381 gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059
382 gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A
383
384 [PcdsDynamicEx]
385 #
386 # This dynamic PCD hold the GUID of a firmware FFS which contains
387 # the LinuxBoot payload.
388 #
389 gArmTokenSpaceGuid.PcdLinuxBootFileGuid|{0x0}|VOID*|0x0000005C