ArmPkg/Drivers/ArmGic/ArmGicLib.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #include <Uefi.h>
  16 #include <Library/IoLib.h>
  17 #include <Library/ArmGicLib.h>
  18 #include <Library/PcdLib.h>
  19
  20 UINTN
  21 EFIAPI
  22 ArmGicGetInterfaceIdentification (
  23   IN  INTN          GicInterruptInterfaceBase
  24   )
  25 {
  26   // Read the GIC Identification Register
  27   return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIIDR);
  28 }
  29
  30 UINTN
  31 EFIAPI
  32 ArmGicGetMaxNumInterrupts (
  33   IN  INTN          GicDistributorBase
  34   )
  35 {
  36   return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F) + 1);
  37 }
  38
  39 VOID
  40 EFIAPI
  41 ArmGicSendSgiTo (
  42   IN  INTN          GicDistributorBase,
  43   IN  INTN          TargetListFilter,
  44   IN  INTN          CPUTargetList,
  45   IN  INTN          SgiId
  46   )
  47 {
  48   MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId);
  49 }
  50
  51 UINTN
  52 EFIAPI
  53 ArmGicAcknowledgeInterrupt (
  54   IN  UINTN          GicInterruptInterfaceBase
  55   )
  56 {
  57   // Read the Interrupt Acknowledge Register
  58   return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
  59 }
  60
  61 VOID
  62 EFIAPI
  63 ArmGicEndOfInterrupt (
  64   IN  UINTN                 GicInterruptInterfaceBase,
  65   IN UINTN                  Source
  66   )
  67 {
  68   MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, Source);
  69 }
  70
  71 VOID
  72 EFIAPI
  73 ArmGicEnableInterrupt (
  74   IN UINTN                  GicDistributorBase,
  75   IN UINTN                  Source
  76   )
  77 {
  78   UINT32    RegOffset;
  79   UINTN     RegShift;
  80
  81   // Calculate enable register offset and bit position
  82   RegOffset = Source / 32;
  83   RegShift = Source % 32;
  84
  85   // Write set-enable register
  86   MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset), 1 << RegShift);
  87 }
  88
  89 VOID
  90 EFIAPI
  91 ArmGicDisableInterrupt (
  92   IN UINTN                  GicDistributorBase,
  93   IN UINTN                  Source
  94   )
  95 {
  96   UINT32    RegOffset;
  97   UINTN     RegShift;
  98
  99   // Calculate enable register offset and bit position
 100   RegOffset = Source / 32;
 101   RegShift = Source % 32;
 102
 103   // Write clear-enable register
 104   MmioWrite32 (GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset), 1 << RegShift);
 105 }
 106
 107 BOOLEAN
 108 EFIAPI
 109 ArmGicIsInterruptEnabled (
 110   IN UINTN                  GicDistributorBase,
 111   IN UINTN                  Source
 112   )
 113 {
 114   UINT32    RegOffset;
 115   UINTN     RegShift;
 116
 117   // Calculate enable register offset and bit position
 118   RegOffset = Source / 32;
 119   RegShift = Source % 32;
 120
 121   return ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)) & (1 << RegShift)) != 0);
 122 }