ArmPkg/ArmGic: Make the GicDxe driver depends on ArmGicLib (cont)

... and also rename the ArmGicLib sources to use an explicit 'Lib' suffix.

The renaming did not work well with SVN. Files were missing from the initial commit.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15622 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/Drivers/ArmGic/ArmGic.c b/ArmPkg/Drivers/ArmGic/ArmGic.c
deleted file mode 100644 (file)
index 1717368..0000000
--- a/ArmPkg/Drivers/ArmGic/ArmGic.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/** @file\r
-*\r
-*  Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-*  \r
-*  This program and the accompanying materials                          \r
-*  are licensed and made available under the terms and conditions of the BSD License         \r
-*  which accompanies this distribution.  The full text of the license may be found at        \r
-*  http://opensource.org/licenses/bsd-license.php                                            \r
-*\r
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
-*\r
-**/\r
-\r
-#include <Uefi.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/ArmGicLib.h>\r
-#include <Library/PcdLib.h>\r
-\r
-UINTN\r
-EFIAPI\r
-ArmGicGetMaxNumInterrupts (\r
-  IN  INTN          GicDistributorBase\r
-  )\r
-{\r
-  return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F) + 1);\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-ArmGicSendSgiTo (\r
-  IN  INTN          GicDistributorBase,\r
-  IN  INTN          TargetListFilter,\r
-  IN  INTN          CPUTargetList,\r
-  IN  INTN          SgiId\r
-  )\r
-{\r
-  MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId);\r
-}\r
-\r
-UINTN\r
-EFIAPI\r
-ArmGicAcknowledgeInterrupt (\r
-  IN  UINTN          GicInterruptInterfaceBase\r
-  )\r
-{\r
-  // Read the Interrupt Acknowledge Register\r
-  return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-ArmGicEndOfInterrupt (\r
-  IN  UINTN                 GicInterruptInterfaceBase,\r
-  IN UINTN                  Source\r
-  )\r
-{\r
-  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, Source);\r
-}\r

diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
new file mode 100644 (file)
index 0000000..0fe62f2
--- /dev/null
+++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
@@ -0,0 +1,122 @@
+/** @file\r
+*\r
+*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
+*\r
+*  This program and the accompanying materials\r
+*  are licensed and made available under the terms and conditions of the BSD License\r
+*  which accompanies this distribution.  The full text of the license may be found at\r
+*  http://opensource.org/licenses/bsd-license.php\r
+*\r
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <Uefi.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/ArmGicLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+UINTN\r
+EFIAPI\r
+ArmGicGetInterfaceIdentification (\r
+  IN  INTN          GicInterruptInterfaceBase\r
+  )\r
+{\r
+  // Read the GIC Identification Register\r
+  return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIIDR);\r
+}\r
+\r
+UINTN\r
+EFIAPI\r
+ArmGicGetMaxNumInterrupts (\r
+  IN  INTN          GicDistributorBase\r
+  )\r
+{\r
+  return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F) + 1);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicSendSgiTo (\r
+  IN  INTN          GicDistributorBase,\r
+  IN  INTN          TargetListFilter,\r
+  IN  INTN          CPUTargetList,\r
+  IN  INTN          SgiId\r
+  )\r
+{\r
+  MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId);\r
+}\r
+\r
+UINTN\r
+EFIAPI\r
+ArmGicAcknowledgeInterrupt (\r
+  IN  UINTN          GicInterruptInterfaceBase\r
+  )\r
+{\r
+  // Read the Interrupt Acknowledge Register\r
+  return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicEndOfInterrupt (\r
+  IN  UINTN                 GicInterruptInterfaceBase,\r
+  IN UINTN                  Source\r
+  )\r
+{\r
+  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, Source);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicEnableInterrupt (\r
+  IN UINTN                  GicDistributorBase,\r
+  IN UINTN                  Source\r
+  )\r
+{\r
+  UINT32    RegOffset;\r
+  UINTN     RegShift;\r
+\r
+  // Calculate enable register offset and bit position\r
+  RegOffset = Source / 32;\r
+  RegShift = Source % 32;\r
+\r
+  // Write set-enable register\r
+  MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset), 1 << RegShift);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicDisableInterrupt (\r
+  IN UINTN                  GicDistributorBase,\r
+  IN UINTN                  Source\r
+  )\r
+{\r
+  UINT32    RegOffset;\r
+  UINTN     RegShift;\r
+\r
+  // Calculate enable register offset and bit position\r
+  RegOffset = Source / 32;\r
+  RegShift = Source % 32;\r
+\r
+  // Write clear-enable register\r
+  MmioWrite32 (GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset), 1 << RegShift);\r
+}\r
+\r
+BOOLEAN\r
+EFIAPI\r
+ArmGicIsInterruptEnabled (\r
+  IN UINTN                  GicDistributorBase,\r
+  IN UINTN                  Source\r
+  )\r
+{\r
+  UINT32    RegOffset;\r
+  UINTN     RegShift;\r
+\r
+  // Calculate enable register offset and bit position\r
+  RegOffset = Source / 32;\r
+  RegShift = Source % 32;\r
+\r
+  return ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)) & (1 << RegShift)) != 0);\r
+}\r

diff --git a/ArmPkg/Drivers/ArmGic/ArmGicNonSec.c b/ArmPkg/Drivers/ArmGic/ArmGicNonSec.c
deleted file mode 100644 (file)
index 55ff56e..0000000
--- a/ArmPkg/Drivers/ArmGic/ArmGicNonSec.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/** @file\r
-*\r
-*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
-*  \r
-*  This program and the accompanying materials                          \r
-*  are licensed and made available under the terms and conditions of the BSD License         \r
-*  which accompanies this distribution.  The full text of the license may be found at        \r
-*  http://opensource.org/licenses/bsd-license.php                                            \r
-*\r
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
-*\r
-**/\r
-\r
-#include <Uefi.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/ArmGicLib.h>\r
-\r
-\r
-VOID\r
-EFIAPI\r
-ArmGicEnableInterruptInterface (\r
-  IN  INTN          GicInterruptInterfaceBase\r
-  )\r
-{  \r
-  /*\r
-  * Enable the CPU interface in Non-Secure world\r
-  * Note: The ICCICR register is banked when Security extensions are implemented\r
-  */\r
-  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x1);\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-ArmGicEnableDistributor (\r
-  IN  INTN          GicDistributorBase\r
-  )\r
-{\r
-  /*\r
-   * Enable GIC distributor in Non-Secure world.\r
-   * Note: The ICDDCR register is banked when Security extensions are implemented\r
-   */\r
-  MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x1);\r
-}\r

diff --git a/ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c b/ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c
new file mode 100644 (file)
index 0000000..0bbc509
--- /dev/null
+++ b/ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c
@@ -0,0 +1,65 @@
+/** @file\r
+*\r
+*  Copyright (c) 2014, ARM Limited. All rights reserved.\r
+*\r
+*  This program and the accompanying materials\r
+*  are licensed and made available under the terms and conditions of the BSD License\r
+*  which accompanies this distribution.  The full text of the license may be found at\r
+*  http://opensource.org/licenses/bsd-license.php\r
+*\r
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <Uefi.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/ArmGicLib.h>\r
+\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicEnableInterruptInterface (\r
+  IN  INTN          GicInterruptInterfaceBase\r
+  )\r
+{  \r
+  /*\r
+  * Enable the CPU interface in Non-Secure world\r
+  * Note: The ICCICR register is banked when Security extensions are implemented\r
+  */\r
+  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x1);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicDisableInterruptInterface (\r
+  IN  INTN          GicInterruptInterfaceBase\r
+  )\r
+{\r
+  // Disable Gic Interface\r
+  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x0);\r
+  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x0);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicEnableDistributor (\r
+  IN  INTN          GicDistributorBase\r
+  )\r
+{\r
+  /*\r
+   * Enable GIC distributor in Non-Secure world.\r
+   * Note: The ICDDCR register is banked when Security extensions are implemented\r
+   */\r
+  MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x1);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicDisableDistributor (\r
+  IN  INTN          GicDistributorBase\r
+  )\r
+{\r
+  // Disable Gic Distributor\r
+  MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x0);\r
+}\r

diff --git a/ArmPkg/Drivers/ArmGic/ArmGicSec.c b/ArmPkg/Drivers/ArmGic/ArmGicSec.c
deleted file mode 100644 (file)
index f249eac..0000000
--- a/ArmPkg/Drivers/ArmGic/ArmGicSec.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/** @file\r
-*\r
-*  Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-*  \r
-*  This program and the accompanying materials                          \r
-*  are licensed and made available under the terms and conditions of the BSD License         \r
-*  which accompanies this distribution.  The full text of the license may be found at        \r
-*  http://opensource.org/licenses/bsd-license.php                                            \r
-*\r
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
-*\r
-**/\r
-\r
-#include <Base.h>\r
-#include <Library/ArmLib.h>\r
-#include <Library/ArmPlatformLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/ArmGicLib.h>\r
-\r
-/*\r
- * This function configures the all interrupts to be Non-secure.\r
- *\r
- */\r
-VOID\r
-EFIAPI\r
-ArmGicSetupNonSecure (\r
-  IN  UINTN         MpId,\r
-  IN  INTN          GicDistributorBase,\r
-  IN  INTN          GicInterruptInterfaceBase\r
-  )\r
-{\r
-  UINTN InterruptId;\r
-  UINTN CachedPriorityMask;\r
-  UINTN Index;\r
-\r
-  CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);\r
-\r
-  // Set priority Mask so that no interrupts get through to CPU\r
-  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);\r
-\r
-  InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
-\r
-  // Only try to clear valid interrupts. Ignore spurious interrupts.\r
-  while ((InterruptId & 0x3FF) < ArmGicGetMaxNumInterrupts (GicDistributorBase))   {\r
-    // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal\r
-    ArmGicEndOfInterrupt (GicInterruptInterfaceBase, InterruptId);\r
-\r
-    // Next\r
-    InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
-  }\r
-\r
-  // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).\r
-  if (ArmPlatformIsPrimaryCore (MpId)) {\r
-    // Ensure all GIC interrupts are Non-Secure\r
-    for (Index = 0; Index < (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32); Index++) {\r
-      MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);\r
-    }\r
-  } else {\r
-    // The secondary cores only set the Non Secure bit to their banked PPIs\r
-    MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);\r
-  }\r
-\r
-  // Ensure all interrupts can get through the priority mask\r
-  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);\r
-}\r
-\r
-/*\r
- * This function configures the interrupts set by the mask to be secure.\r
- *\r
- */\r
-VOID\r
-EFIAPI\r
-ArmGicSetSecureInterrupts (\r
-  IN  UINTN         GicDistributorBase,\r
-  IN  UINTN*        GicSecureInterruptMask,\r
-  IN  UINTN         GicSecureInterruptMaskSize\r
-  )\r
-{\r
-  UINTN  Index;\r
-  UINT32 InterruptStatus;\r
-\r
-  // We must not have more interrupts defined by the mask than the number of available interrupts\r
-  ASSERT(GicSecureInterruptMaskSize <= (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32));\r
-\r
-  // Set all the interrupts defined by the mask as Secure\r
-  for (Index = 0; Index < GicSecureInterruptMaskSize; Index++) {\r
-    InterruptStatus = MmioRead32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4));\r
-    MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), InterruptStatus & (~GicSecureInterruptMask[Index]));\r
-  }\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-ArmGicEnableInterruptInterface (\r
-  IN  INTN          GicInterruptInterfaceBase\r
-  )\r
-{\r
-  // Set Priority Mask to allow interrupts\r
-  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);\r
-\r
-  // Enable CPU interface in Secure world\r
-  // Enable CPU interface in Non-secure World\r
-  // Signal Secure Interrupts to CPU using FIQ line *\r
-  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,\r
-      ARM_GIC_ICCICR_ENABLE_SECURE |\r
-      ARM_GIC_ICCICR_ENABLE_NS |\r
-      ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-ArmGicDisableInterruptInterface (\r
-  IN  INTN          GicInterruptInterfaceBase\r
-  )\r
-{\r
-  UINT32    ControlValue;\r
-\r
-  // Disable CPU interface in Secure world and Non-secure World\r
-  ControlValue = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR);\r
-  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, ControlValue & ~(ARM_GIC_ICCICR_ENABLE_SECURE | ARM_GIC_ICCICR_ENABLE_NS));\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-ArmGicEnableDistributor (\r
-  IN  INTN          GicDistributorBase\r
-  )\r
-{\r
-  // Turn on the GIC distributor\r
-  MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 1);\r
-}\r

diff --git a/ArmPkg/Drivers/ArmGic/ArmGicSecLib.c b/ArmPkg/Drivers/ArmGic/ArmGicSecLib.c
new file mode 100644 (file)
index 0000000..f249eac
--- /dev/null
+++ b/ArmPkg/Drivers/ArmGic/ArmGicSecLib.c
@@ -0,0 +1,133 @@
+/** @file\r
+*\r
+*  Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+*  \r
+*  This program and the accompanying materials                          \r
+*  are licensed and made available under the terms and conditions of the BSD License         \r
+*  which accompanies this distribution.  The full text of the license may be found at        \r
+*  http://opensource.org/licenses/bsd-license.php                                            \r
+*\r
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+*\r
+**/\r
+\r
+#include <Base.h>\r
+#include <Library/ArmLib.h>\r
+#include <Library/ArmPlatformLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/ArmGicLib.h>\r
+\r
+/*\r
+ * This function configures the all interrupts to be Non-secure.\r
+ *\r
+ */\r
+VOID\r
+EFIAPI\r
+ArmGicSetupNonSecure (\r
+  IN  UINTN         MpId,\r
+  IN  INTN          GicDistributorBase,\r
+  IN  INTN          GicInterruptInterfaceBase\r
+  )\r
+{\r
+  UINTN InterruptId;\r
+  UINTN CachedPriorityMask;\r
+  UINTN Index;\r
+\r
+  CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);\r
+\r
+  // Set priority Mask so that no interrupts get through to CPU\r
+  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);\r
+\r
+  InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
+\r
+  // Only try to clear valid interrupts. Ignore spurious interrupts.\r
+  while ((InterruptId & 0x3FF) < ArmGicGetMaxNumInterrupts (GicDistributorBase))   {\r
+    // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal\r
+    ArmGicEndOfInterrupt (GicInterruptInterfaceBase, InterruptId);\r
+\r
+    // Next\r
+    InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
+  }\r
+\r
+  // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).\r
+  if (ArmPlatformIsPrimaryCore (MpId)) {\r
+    // Ensure all GIC interrupts are Non-Secure\r
+    for (Index = 0; Index < (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32); Index++) {\r
+      MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);\r
+    }\r
+  } else {\r
+    // The secondary cores only set the Non Secure bit to their banked PPIs\r
+    MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);\r
+  }\r
+\r
+  // Ensure all interrupts can get through the priority mask\r
+  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);\r
+}\r
+\r
+/*\r
+ * This function configures the interrupts set by the mask to be secure.\r
+ *\r
+ */\r
+VOID\r
+EFIAPI\r
+ArmGicSetSecureInterrupts (\r
+  IN  UINTN         GicDistributorBase,\r
+  IN  UINTN*        GicSecureInterruptMask,\r
+  IN  UINTN         GicSecureInterruptMaskSize\r
+  )\r
+{\r
+  UINTN  Index;\r
+  UINT32 InterruptStatus;\r
+\r
+  // We must not have more interrupts defined by the mask than the number of available interrupts\r
+  ASSERT(GicSecureInterruptMaskSize <= (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32));\r
+\r
+  // Set all the interrupts defined by the mask as Secure\r
+  for (Index = 0; Index < GicSecureInterruptMaskSize; Index++) {\r
+    InterruptStatus = MmioRead32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4));\r
+    MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), InterruptStatus & (~GicSecureInterruptMask[Index]));\r
+  }\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicEnableInterruptInterface (\r
+  IN  INTN          GicInterruptInterfaceBase\r
+  )\r
+{\r
+  // Set Priority Mask to allow interrupts\r
+  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);\r
+\r
+  // Enable CPU interface in Secure world\r
+  // Enable CPU interface in Non-secure World\r
+  // Signal Secure Interrupts to CPU using FIQ line *\r
+  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,\r
+      ARM_GIC_ICCICR_ENABLE_SECURE |\r
+      ARM_GIC_ICCICR_ENABLE_NS |\r
+      ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicDisableInterruptInterface (\r
+  IN  INTN          GicInterruptInterfaceBase\r
+  )\r
+{\r
+  UINT32    ControlValue;\r
+\r
+  // Disable CPU interface in Secure world and Non-secure World\r
+  ControlValue = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR);\r
+  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, ControlValue & ~(ARM_GIC_ICCICR_ENABLE_SECURE | ARM_GIC_ICCICR_ENABLE_NS));\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicEnableDistributor (\r
+  IN  INTN          GicDistributorBase\r
+  )\r
+{\r
+  // Turn on the GIC distributor\r
+  MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 1);\r
+}\r