ArmPkg/ArmGic: Introduced helper functions to access the GIC controller

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15621 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/Drivers/ArmGic/ArmGicDxe.c b/ArmPkg/Drivers/ArmGic/ArmGicDxe.c
index 9608c314ed50f3966e2e9b5f6f05cd8f1bc5e4f2..c360d113be3d1a1901196c220c9ea405cbc158d3 100644 (file)
--- a/ArmPkg/Drivers/ArmGic/ArmGicDxe.c
+++ b/ArmPkg/Drivers/ArmGic/ArmGicDxe.c
@@ -2,19 +2,19 @@
 \r
 Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>\r
 Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>\r
-Portions copyright (c) 2011-2013, ARM Ltd. All rights reserved.<BR> \r
+Portions copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>\r
 \r
-This program and the accompanying materials                          \r
-are licensed and made available under the terms and conditions of the BSD License         \r
-which accompanies this distribution.  The full text of the license may be found at        \r
-http://opensource.org/licenses/bsd-license.php                                            \r
-                                                                                          \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.   \r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
 \r
 Module Name:\r
 \r
-  Gic.c\r
+  ArmGicDxe.c\r
 \r
 Abstract:\r
 \r
@@ -111,21 +111,13 @@ EnableInterruptSource (
   IN HARDWARE_INTERRUPT_SOURCE          Source\r
   )\r
 {\r
-  UINT32    RegOffset;\r
-  UINTN     RegShift;\r
-  \r
   if (Source > mGicNumInterrupts) {\r
     ASSERT(FALSE);\r
     return EFI_UNSUPPORTED;\r
   }\r
-  \r
-  // Calculate enable register offset and bit position\r
-  RegOffset = Source / 32;\r
-  RegShift = Source % 32;\r
 \r
-  // Write set-enable register\r
-  MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset), 1 << RegShift);\r
-  \r
+  ArmGicEnableInterrupt (FixedPcdGet32 (PcdGicDistributorBase), Source);\r
+\r
   return EFI_SUCCESS;\r
 }\r
 \r
@@ -146,21 +138,13 @@ DisableInterruptSource (
   IN HARDWARE_INTERRUPT_SOURCE          Source\r
   )\r
 {\r
-  UINT32    RegOffset;\r
-  UINTN     RegShift;\r
-  \r
   if (Source > mGicNumInterrupts) {\r
     ASSERT(FALSE);\r
     return EFI_UNSUPPORTED;\r
   }\r
-  \r
-  // Calculate enable register offset and bit position\r
-  RegOffset = Source / 32;\r
-  RegShift = Source % 32;\r
 \r
-  // Write set-enable register\r
-  MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDICER + (4*RegOffset), 1 << RegShift);\r
-  \r
+  ArmGicDisableInterrupt (PcdGet32(PcdGicDistributorBase), Source);\r
+\r
   return EFI_SUCCESS;\r
 }\r
 \r
@@ -183,24 +167,13 @@ GetInterruptSourceState (
   IN BOOLEAN                            *InterruptState\r
   )\r
 {\r
-  UINT32    RegOffset;\r
-  UINTN     RegShift;\r
-  \r
   if (Source > mGicNumInterrupts) {\r
     ASSERT(FALSE);\r
     return EFI_UNSUPPORTED;\r
   }\r
-  \r
-  // calculate enable register offset and bit position\r
-  RegOffset = Source / 32;\r
-  RegShift = Source % 32;\r
-    \r
-  if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset)) & (1<<RegShift)) == 0) {\r
-    *InterruptState = FALSE;\r
-  } else {\r
-    *InterruptState = TRUE;\r
-  }\r
-  \r
+\r
+  *InterruptState = ArmGicIsInterruptEnabled (PcdGet32(PcdGicDistributorBase), Source);\r
+\r
   return EFI_SUCCESS;\r
 }\r
 \r
@@ -315,11 +288,10 @@ ExitBootServicesEvent (
   }\r
 \r
   // Disable Gic Interface\r
-  MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x0);\r
-  MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0x0);\r
+  ArmGicDisableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));\r
 \r
   // Disable Gic Distributor\r
-  MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x0);\r
+  ArmGicDisableDistributor (PcdGet32(PcdGicDistributorBase));\r
 }\r
 \r
 /**\r
@@ -391,23 +363,23 @@ InterruptDxeInitialize (
 \r
   // Set priority mask reg to 0xff to allow all priorities through\r
   MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0xff);\r
-  \r
+\r
   // Enable gic cpu interface\r
-  MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x1);\r
+  ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));\r
 \r
   // Enable gic distributor\r
-  MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x1);\r
-  \r
+  ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));\r
+\r
   // Initialize the array for the Interrupt Handlers\r
   gRegisteredInterruptHandlers = (HARDWARE_INTERRUPT_HANDLER*)AllocateZeroPool (sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts);\r
-  \r
+\r
   Status = gBS->InstallMultipleProtocolInterfaces (\r
                   &gHardwareInterruptHandle,\r
                   &gHardwareInterruptProtocolGuid,   &gHardwareInterruptProtocol,\r
                   NULL\r
                   );\r
   ASSERT_EFI_ERROR (Status);\r
-  \r
+\r
   //\r
   // Get the CPU protocol that this driver requires.\r
   //\r

diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/ArmGicLib.h
index af8941905b321731d88fe0c57cbe08e5f1da101c..24f1966b56c181fded87c77aabe282a43964cca5 100644 (file)
--- a/ArmPkg/Include/Library/ArmGicLib.h
+++ b/ArmPkg/Include/Library/ArmGicLib.h
@@ -1,6 +1,6 @@
 /** @file\r
 *\r
-*  Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
 *\r
 *  This program and the accompanying materials\r
 *  are licensed and made available under the terms and conditions of the BSD License\r
@@ -57,7 +57,7 @@
 #define ARM_GIC_ICCRPR          0x14  // Running Priority Register\r
 #define ARM_GIC_ICCPIR          0x18  // Highest Pending Interrupt Register\r
 #define ARM_GIC_ICCABPR         0x1C  // Aliased Binary Point Register\r
-#define ARM_GIC_ICCIDR          0xFC  // Identification Register\r
+#define ARM_GIC_ICCIIDR         0xFC  // Identification Register\r
 \r
 #define ARM_GIC_ICDSGIR_FILTER_TARGETLIST       0x0\r
 #define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE     0x1\r
@@ -71,14 +71,20 @@
 #define ARM_GIC_ICCICR_USE_SBPR                 0x10\r
 \r
 // Bit Mask for GICC_IIDR\r
-#define ARM_GIC_ICCIDR_GET_PRODUCT_ID(IccIdr)   (((IccIdr) >> 20) & 0xFFF)\r
-#define ARM_GIC_ICCIDR_GET_ARCH_VERSION(IccIdr) (((IccIdr) >> 16) & 0xF)\r
-#define ARM_GIC_ICCIDR_GET_REVISION(IccIdr)     (((IccIdr) >> 12) & 0xF)\r
-#define ARM_GIC_ICCIDR_GET_IMPLEMENTER(IccIdr)  ((IccIdr) & 0xFFF)\r
+#define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr)   (((IccIidr) >> 20) & 0xFFF)\r
+#define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)\r
+#define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr)     (((IccIidr) >> 12) & 0xF)\r
+#define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr)  ((IccIidr) & 0xFFF)\r
 \r
 // Bit Mask for\r
 #define ARM_GIC_ICCIAR_ACKINTID                 0x3FF\r
 \r
+UINTN\r
+EFIAPI\r
+ArmGicGetInterfaceIdentification (\r
+  IN  INTN          GicInterruptInterfaceBase\r
+  );\r
+\r
 //\r
 // GIC Secure interfaces\r
 //\r
@@ -116,6 +122,12 @@ ArmGicEnableDistributor (
   IN  INTN          GicDistributorBase\r
   );\r
 \r
+VOID\r
+EFIAPI\r
+ArmGicDisableDistributor (\r
+  IN  INTN          GicDistributorBase\r
+  );\r
+\r
 UINTN\r
 EFIAPI\r
 ArmGicGetMaxNumInterrupts (\r
@@ -151,4 +163,25 @@ ArmGicSetPriorityMask (
   IN  INTN          PriorityMask\r
   );\r
 \r
+VOID\r
+EFIAPI\r
+ArmGicEnableInterrupt (\r
+  IN UINTN                  GicDistributorBase,\r
+  IN UINTN                  Source\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicDisableInterrupt (\r
+  IN UINTN                  GicDistributorBase,\r
+  IN UINTN                  Source\r
+  );\r
+\r
+BOOLEAN\r
+EFIAPI\r
+ArmGicIsInterruptEnabled (\r
+  IN UINTN                  GicDistributorBase,\r
+  IN UINTN                  Source\r
+  );\r
+\r
 #endif\r

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/RTSMSec.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/RTSMSec.c
index 4c018f7672585972eec40668f417f2be497041b2..f5176eac90f41d90c2f7d2edc458c1487d4ab941 100644 (file)
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/RTSMSec.c
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/RTSMSec.c
@@ -1,6 +1,6 @@
 /** @file\r
 *\r
-*  Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
 *\r
 *  This program and the accompanying materials\r
 *  are licensed and made available under the terms and conditions of the BSD License\r
@@ -73,10 +73,10 @@ ArmPlatformSecInitialize (
   MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);\r
 \r
   // Read the GIC Identification Register\r
-  Identification = MmioRead32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCIDR);\r
+  Identification = ArmGicGetInterfaceIdentification (PcdGet32 (PcdGicInterruptInterfaceBase));\r
 \r
   // Check if we are GICv3\r
-  if (ARM_GIC_ICCIDR_GET_ARCH_VERSION(Identification) >= 0x3) {\r
+  if (ARM_GIC_ICCIIDR_GET_ARCH_VERSION(Identification) >= 0x3) {\r
     InitializeGicV3 ();\r
   }\r
 \r