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55a0d64b | 1 | /** @file\r |
2 | *\r | |
e700a1fc | 3 | * Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r |
55a0d64b | 4 | *\r |
1cb13673 OM |
5 | * This program and the accompanying materials\r |
6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
7 | * which accompanies this distribution. The full text of the license may be found at\r | |
8 | * http://opensource.org/licenses/bsd-license.php\r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
55a0d64b | 12 | *\r |
13 | **/\r | |
14 | \r | |
017baa1c OM |
15 | #ifndef __ARMGIC_H\r |
16 | #define __ARMGIC_H\r | |
55a0d64b | 17 | \r |
18 | //\r | |
19 | // GIC definitions\r | |
20 | //\r | |
21 | \r | |
22 | //\r | |
23 | // GIC Distributor\r | |
24 | //\r | |
25 | #define ARM_GIC_ICDDCR 0x000 // Distributor Control Register\r | |
26 | #define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register\r | |
27 | #define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register\r | |
28 | \r | |
29 | // Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BITS (see GIC spec)\r | |
30 | #define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers\r | |
31 | #define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers\r | |
32 | #define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers\r | |
33 | #define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers\r | |
34 | #define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers\r | |
35 | #define ARM_GIC_ICDABR 0x300 // Active Bit Registers\r | |
36 | \r | |
37 | // Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BYTES\r | |
38 | #define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers\r | |
39 | \r | |
40 | // Each reg base below repeats for VE_NUM_ARM_GIC_INTERRUPTS\r | |
41 | #define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers\r | |
42 | #define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers\r | |
43 | \r | |
44 | #define ARM_GIC_ICDPPISR 0xD00 // PPI Status register\r | |
45 | \r | |
46 | // just one of these\r | |
47 | #define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register\r | |
48 | \r | |
49 | //\r | |
50 | // GIC Cpu interface\r | |
51 | //\r | |
52 | #define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register\r | |
53 | #define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register\r | |
54 | #define ARM_GIC_ICCBPR 0x08 // Binary Point Register\r | |
55 | #define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register\r | |
56 | #define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register\r | |
57 | #define ARM_GIC_ICCRPR 0x14 // Running Priority Register\r | |
58 | #define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register\r | |
59 | #define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register\r | |
e700a1fc | 60 | #define ARM_GIC_ICCIIDR 0xFC // Identification Register\r |
55a0d64b | 61 | \r |
62 | #define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0\r | |
63 | #define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1\r | |
64 | #define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2\r | |
65 | \r | |
66 | // Bit-masks to configure the CPU Interface Control register\r | |
67 | #define ARM_GIC_ICCICR_ENABLE_SECURE 0x01\r | |
68 | #define ARM_GIC_ICCICR_ENABLE_NS 0x02\r | |
69 | #define ARM_GIC_ICCICR_ACK_CTL 0x04\r | |
70 | #define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08\r | |
71 | #define ARM_GIC_ICCICR_USE_SBPR 0x10\r | |
72 | \r | |
1cb13673 | 73 | // Bit Mask for GICC_IIDR\r |
e700a1fc OM |
74 | #define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr) (((IccIidr) >> 20) & 0xFFF)\r |
75 | #define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)\r | |
76 | #define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF)\r | |
77 | #define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF)\r | |
55a0d64b | 78 | \r |
2ca815a4 OM |
79 | // Bit Mask for\r |
80 | #define ARM_GIC_ICCIAR_ACKINTID 0x3FF\r | |
81 | \r | |
e700a1fc OM |
82 | UINTN\r |
83 | EFIAPI\r | |
84 | ArmGicGetInterfaceIdentification (\r | |
85 | IN INTN GicInterruptInterfaceBase\r | |
86 | );\r | |
87 | \r | |
55a0d64b | 88 | //\r |
92534106 | 89 | // GIC Secure interfaces\r |
55a0d64b | 90 | //\r |
91 | VOID\r | |
92 | EFIAPI\r | |
93 | ArmGicSetupNonSecure (\r | |
5e773144 | 94 | IN UINTN MpId,\r |
55a0d64b | 95 | IN INTN GicDistributorBase,\r |
96 | IN INTN GicInterruptInterfaceBase\r | |
97 | );\r | |
98 | \r | |
92534106 | 99 | VOID\r |
100 | EFIAPI\r | |
101 | ArmGicSetSecureInterrupts (\r | |
102 | IN UINTN GicDistributorBase,\r | |
103 | IN UINTN* GicSecureInterruptMask,\r | |
104 | IN UINTN GicSecureInterruptMaskSize\r | |
105 | );\r | |
106 | \r | |
55a0d64b | 107 | VOID\r |
108 | EFIAPI\r | |
109 | ArmGicEnableInterruptInterface (\r | |
110 | IN INTN GicInterruptInterfaceBase\r | |
111 | );\r | |
112 | \r | |
9736c297 | 113 | VOID\r |
114 | EFIAPI\r | |
115 | ArmGicDisableInterruptInterface (\r | |
116 | IN INTN GicInterruptInterfaceBase\r | |
117 | );\r | |
118 | \r | |
55a0d64b | 119 | VOID\r |
120 | EFIAPI\r | |
121 | ArmGicEnableDistributor (\r | |
122 | IN INTN GicDistributorBase\r | |
123 | );\r | |
124 | \r | |
e700a1fc OM |
125 | VOID\r |
126 | EFIAPI\r | |
127 | ArmGicDisableDistributor (\r | |
128 | IN INTN GicDistributorBase\r | |
129 | );\r | |
130 | \r | |
e9f7c58f | 131 | UINTN\r |
132 | EFIAPI\r | |
133 | ArmGicGetMaxNumInterrupts (\r | |
134 | IN INTN GicDistributorBase\r | |
135 | );\r | |
136 | \r | |
55a0d64b | 137 | VOID\r |
138 | EFIAPI\r | |
139 | ArmGicSendSgiTo (\r | |
140 | IN INTN GicDistributorBase,\r | |
141 | IN INTN TargetListFilter,\r | |
4c19ece3 | 142 | IN INTN CPUTargetList,\r |
143 | IN INTN SgiId\r | |
55a0d64b | 144 | );\r |
145 | \r | |
2ca815a4 | 146 | UINTN\r |
55a0d64b | 147 | EFIAPI\r |
315649cd | 148 | ArmGicAcknowledgeInterrupt (\r |
2ca815a4 | 149 | IN UINTN GicInterruptInterfaceBase\r |
55a0d64b | 150 | );\r |
151 | \r | |
d80401a1 OM |
152 | VOID\r |
153 | EFIAPI\r | |
154 | ArmGicEndOfInterrupt (\r | |
155 | IN UINTN GicInterruptInterfaceBase,\r | |
156 | IN UINTN Source\r | |
157 | );\r | |
158 | \r | |
55a0d64b | 159 | UINTN\r |
160 | EFIAPI\r | |
161 | ArmGicSetPriorityMask (\r | |
162 | IN INTN GicInterruptInterfaceBase,\r | |
163 | IN INTN PriorityMask\r | |
164 | );\r | |
165 | \r | |
e700a1fc OM |
166 | VOID\r |
167 | EFIAPI\r | |
168 | ArmGicEnableInterrupt (\r | |
169 | IN UINTN GicDistributorBase,\r | |
170 | IN UINTN Source\r | |
171 | );\r | |
172 | \r | |
173 | VOID\r | |
174 | EFIAPI\r | |
175 | ArmGicDisableInterrupt (\r | |
176 | IN UINTN GicDistributorBase,\r | |
177 | IN UINTN Source\r | |
178 | );\r | |
179 | \r | |
180 | BOOLEAN\r | |
181 | EFIAPI\r | |
182 | ArmGicIsInterruptEnabled (\r | |
183 | IN UINTN GicDistributorBase,\r | |
184 | IN UINTN Source\r | |
185 | );\r | |
186 | \r | |
55a0d64b | 187 | #endif\r |