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ArmPkg/ArmGic: Introduced support for GicV2 to ArmGicLib
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1 /** @file
2 *
3 * Copyright (c) 2011-2014, ARM Limited. All rights reserved.
4 *
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
9 *
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12 *
13 **/
14
15 #include <Base.h>
16 #include <Library/ArmGicLib.h>
17 #include <Library/IoLib.h>
18
19 #include "GicV2/ArmGicV2Lib.h"
20
21 UINTN
22 EFIAPI
23 ArmGicGetInterfaceIdentification (
24 IN INTN GicInterruptInterfaceBase
25 )
26 {
27 // Read the GIC Identification Register
28 return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIIDR);
29 }
30
31 UINTN
32 EFIAPI
33 ArmGicGetMaxNumInterrupts (
34 IN INTN GicDistributorBase
35 )
36 {
37 return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F) + 1);
38 }
39
40 VOID
41 EFIAPI
42 ArmGicSendSgiTo (
43 IN INTN GicDistributorBase,
44 IN INTN TargetListFilter,
45 IN INTN CPUTargetList,
46 IN INTN SgiId
47 )
48 {
49 MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId);
50 }
51
52 UINTN
53 EFIAPI
54 ArmGicAcknowledgeInterrupt (
55 IN UINTN GicInterruptInterfaceBase
56 )
57 {
58 return ArmGicV2AcknowledgeInterrupt (GicInterruptInterfaceBase);
59 }
60
61 VOID
62 EFIAPI
63 ArmGicEndOfInterrupt (
64 IN UINTN GicInterruptInterfaceBase,
65 IN UINTN Source
66 )
67 {
68 ArmGicV2EndOfInterrupt (GicInterruptInterfaceBase, Source);
69 }
70
71 VOID
72 EFIAPI
73 ArmGicEnableInterrupt (
74 IN UINTN GicDistributorBase,
75 IN UINTN Source
76 )
77 {
78 UINT32 RegOffset;
79 UINTN RegShift;
80
81 // Calculate enable register offset and bit position
82 RegOffset = Source / 32;
83 RegShift = Source % 32;
84
85 // Write set-enable register
86 MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset), 1 << RegShift);
87 }
88
89 VOID
90 EFIAPI
91 ArmGicDisableInterrupt (
92 IN UINTN GicDistributorBase,
93 IN UINTN Source
94 )
95 {
96 UINT32 RegOffset;
97 UINTN RegShift;
98
99 // Calculate enable register offset and bit position
100 RegOffset = Source / 32;
101 RegShift = Source % 32;
102
103 // Write clear-enable register
104 MmioWrite32 (GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset), 1 << RegShift);
105 }
106
107 BOOLEAN
108 EFIAPI
109 ArmGicIsInterruptEnabled (
110 IN UINTN GicDistributorBase,
111 IN UINTN Source
112 )
113 {
114 UINT32 RegOffset;
115 UINTN RegShift;
116
117 // Calculate enable register offset and bit position
118 RegOffset = Source / 32;
119 RegShift = Source % 32;
120
121 return ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)) & (1 << RegShift)) != 0);
122 }
123
124 VOID
125 EFIAPI
126 ArmGicDisableDistributor (
127 IN INTN GicDistributorBase
128 )
129 {
130 // Disable Gic Distributor
131 MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x0);
132 }
133
134 VOID
135 EFIAPI
136 ArmGicEnableInterruptInterface (
137 IN INTN GicInterruptInterfaceBase
138 )
139 {
140 return ArmGicV2EnableInterruptInterface (GicInterruptInterfaceBase);
141 }
142
143 VOID
144 EFIAPI
145 ArmGicDisableInterruptInterface (
146 IN INTN GicInterruptInterfaceBase
147 )
148 {
149 return ArmGicV2DisableInterruptInterface (GicInterruptInterfaceBase);
150 }