ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.h

   1 /** @file
   2 *
   3 *  Copyright (c) 2013-2014, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #ifndef _ARM_GIC_V2_H_
  16 #define _ARM_GIC_V2_H_
  17
  18 //
  19 // GIC definitions
  20 //
  21
  22 //
  23 // GIC Distributor
  24 //
  25 #define ARM_GIC_ICDDCR          0x000 // Distributor Control Register
  26 #define ARM_GIC_ICDICTR         0x004 // Interrupt Controller Type Register
  27 #define ARM_GIC_ICDIIDR         0x008 // Implementer Identification Register
  28
  29 // Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BITS (see GIC spec)
  30 #define ARM_GIC_ICDISR          0x080 // Interrupt Security Registers
  31 #define ARM_GIC_ICDISER         0x100 // Interrupt Set-Enable Registers
  32 #define ARM_GIC_ICDICER         0x180 // Interrupt Clear-Enable Registers
  33 #define ARM_GIC_ICDSPR          0x200 // Interrupt Set-Pending Registers
  34 #define ARM_GIC_ICDICPR         0x280 // Interrupt Clear-Pending Registers
  35 #define ARM_GIC_ICDABR          0x300 // Active Bit Registers
  36
  37 // Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BYTES
  38 #define ARM_GIC_ICDIPR          0x400 // Interrupt Priority Registers
  39
  40 // Each reg base below repeats for VE_NUM_ARM_GIC_INTERRUPTS
  41 #define ARM_GIC_ICDIPTR         0x800 // Interrupt Processor Target Registers
  42 #define ARM_GIC_ICDICFR         0xC00 // Interrupt Configuration Registers
  43
  44 #define ARM_GIC_ICDPPISR        0xD00 // PPI Status register
  45
  46 // just one of these
  47 #define ARM_GIC_ICDSGIR         0xF00 // Software Generated Interrupt Register
  48
  49 //
  50 // GIC Cpu interface
  51 //
  52 #define ARM_GIC_ICCICR          0x00  // CPU Interface Control Register
  53 #define ARM_GIC_ICCPMR          0x04  // Interrupt Priority Mask Register
  54 #define ARM_GIC_ICCBPR          0x08  // Binary Point Register
  55 #define ARM_GIC_ICCIAR          0x0C  // Interrupt Acknowledge Register
  56 #define ARM_GIC_ICCEIOR         0x10  // End Of Interrupt Register
  57 #define ARM_GIC_ICCRPR          0x14  // Running Priority Register
  58 #define ARM_GIC_ICCPIR          0x18  // Highest Pending Interrupt Register
  59 #define ARM_GIC_ICCABPR         0x1C  // Aliased Binary Point Register
  60 #define ARM_GIC_ICCIIDR         0xFC  // Identification Register
  61
  62 // Bit Mask for
  63 #define ARM_GIC_ICCIAR_ACKINTID                 0x3FF
  64
  65 // Interrupts from 1020 to 1023 are considered as special interrupts (eg: spurious interrupts)
  66 #define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) (((Interrupt) >= 1020) && ((Interrupt) <= 1023))
  67
  68 VOID
  69 EFIAPI
  70 ArmGicV2SetupNonSecure (
  71   IN  UINTN         MpId,
  72   IN  INTN          GicDistributorBase,
  73   IN  INTN          GicInterruptInterfaceBase
  74   );
  75
  76 VOID
  77 EFIAPI
  78 ArmGicV2EnableInterruptInterface (
  79   IN  INTN          GicInterruptInterfaceBase
  80   );
  81
  82 VOID
  83 EFIAPI
  84 ArmGicV2DisableInterruptInterface (
  85   IN  INTN          GicInterruptInterfaceBase
  86   );
  87
  88 UINTN
  89 EFIAPI
  90 ArmGicV2AcknowledgeInterrupt (
  91   IN  UINTN          GicInterruptInterfaceBase
  92   );
  93
  94 VOID
  95 EFIAPI
  96 ArmGicV2EndOfInterrupt (
  97   IN UINTN                  GicInterruptInterfaceBase,
  98   IN UINTN                  Source
  99   );
 100
 101 #endif