2 # Copyright (c) 2014, ARM Limited. All rights reserved.
4 # This program and the accompanying materials are licensed and made available
5 # under the terms and conditions of the BSD License which accompanies this
6 # distribution. The full text of the license may be found at
7 # http://opensource.org/licenses/bsd-license.php
9 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14 #include <AsmMacroIoLib.h>
15 #include <Library/ArmLib.h>
17 // For the moment we assume this will run in SVC mode on ARMv7
22 GCC_ASM_EXPORT(ArmGicGetControlSystemRegisterEnable)
23 GCC_ASM_EXPORT(ArmGicSetControlSystemRegisterEnable)
24 GCC_ASM_EXPORT(ArmGicV3EnableInterruptInterface)
25 GCC_ASM_EXPORT(ArmGicV3DisableInterruptInterface)
26 GCC_ASM_EXPORT(ArmGicV3EndOfInterrupt)
27 GCC_ASM_EXPORT(ArmGicV3AcknowledgeInterrupt)
28 GCC_ASM_EXPORT(ArmGicV3SetPriorityMask)
29 GCC_ASM_EXPORT(ArmGicV3SetBinaryPointer)
33 //ArmGicGetControlSystemRegisterEnable (
36 ASM_PFX(ArmGicGetControlSystemRegisterEnable):
37 mrc p15, 0, r0, c12, c12, 5 // ICC_SRE
42 //ArmGicSetControlSystemRegisterEnable (
43 // IN UINT32 ControlSystemRegisterEnable
45 ASM_PFX(ArmGicSetControlSystemRegisterEnable):
46 mcr p15, 0, r0, c12, c12, 5 // ICC_SRE
51 //ArmGicV3EnableInterruptInterface (
54 ASM_PFX(ArmGicV3EnableInterruptInterface):
56 mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1
60 //ArmGicV3DisableInterruptInterface (
63 ASM_PFX(ArmGicV3DisableInterruptInterface):
65 mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1
69 //ArmGicV3EndOfInterrupt (
70 // IN UINTN InterruptId
72 ASM_PFX(ArmGicV3EndOfInterrupt):
73 mcr p15, 0, r0, c12, c12, 1 //ICC_EOIR1
77 //ArmGicV3AcknowledgeInterrupt (
80 ASM_PFX(ArmGicV3AcknowledgeInterrupt):
81 mrc p15, 0, r0, c12, c8, 0 //ICC_IAR1
85 //ArmGicV3SetPriorityMask (
88 ASM_PFX(ArmGicV3SetPriorityMask):
89 mcr p15, 0, r0, c4, c6, 0 //ICC_PMR
93 //ArmGicV3SetBinaryPointer (
94 // IN UINTN BinaryPoint
96 ASM_PFX(ArmGicV3SetBinaryPointer):
97 mcr p15, 0, r0, c12, c12, 3 //ICC_BPR1