1 //------------------------------------------------------------------------------
3 // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
5 // This program and the accompanying materials
6 // are licensed and made available under the terms and conditions of the BSD License
7 // which accompanies this distribution. The full text of the license may be found at
8 // http://opensource.org/licenses/bsd-license.php
10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 //------------------------------------------------------------------------------
15 EXPORT ExceptionHandlersStart
16 EXPORT ExceptionHandlersEnd
17 EXPORT CommonExceptionEntry
18 EXPORT AsmCommonExceptionEntry
19 IMPORT CommonCExceptionHandler
22 AREA DxeExceptionHandlers, CODE, READONLY
24 ExceptionHandlersStart
30 b UndefinedInstructionEntry
33 b SoftwareInterruptEntry
42 b ReservedExceptionEntry
53 ldr R1,CommonExceptionEntry
56 UndefinedInstructionEntry
59 ldr R1,CommonExceptionEntry
62 SoftwareInterruptEntry
65 ldr R1,CommonExceptionEntry
72 ldr R1,CommonExceptionEntry
79 ldr R1,CommonExceptionEntry
82 ReservedExceptionEntry
85 ldr R1,CommonExceptionEntry
92 ldr R1,CommonExceptionEntry
99 ldr R1,CommonExceptionEntry
107 AsmCommonExceptionEntry
108 mrc p15, 0, r1, c6, c0, 2 ; Read IFAR
109 stmfd SP!,{R1} ; Store the IFAR
111 mrc p15, 0, r1, c5, c0, 1 ; Read IFSR
112 stmfd SP!,{R1} ; Store the IFSR
114 mrc p15, 0, r1, c6, c0, 0 ; Read DFAR
115 stmfd SP!,{R1} ; Store the DFAR
117 mrc p15, 0, r1, c5, c0, 0 ; Read DFSR
118 stmfd SP!,{R1} ; Store the DFSR
120 mrs R1,SPSR ; Read SPSR (which is the pre-exception CPSR)
121 stmfd SP!,{R1} ; Store the SPSR
123 stmfd SP!,{LR} ; Store the link register (which is the pre-exception PC)
124 stmfd SP,{SP,LR}^ ; Store user/system mode stack pointer and link register
125 nop ; Required by ARM architecture
126 SUB SP,SP,#0x08 ; Adjust stack pointer
127 stmfd SP!,{R2-R12} ; Store general purpose registers
129 ldr R3,[SP,#0x50] ; Read saved R1 from the stack (it was saved by the exception entry routine)
130 ldr R2,[SP,#0x4C] ; Read saved R0 from the stack (it was saved by the exception entry routine)
131 stmfd SP!,{R2-R3} ; Store general purpose registers R0 and R1
133 mov R1,SP ; Prepare System Context pointer as an argument for the exception handler
135 sub SP,SP,#4 ; Adjust SP to preserve 8-byte alignment
136 blx CommonCExceptionHandler ; Call exception handler
137 add SP,SP,#4 ; Adjust SP back to where we were
139 ldr R2,[SP,#0x40] ; Load CPSR from context, in case it has changed
140 MSR SPSR_cxsf,R2 ; Store it back to the SPSR to be restored when exiting this handler
142 ldmfd SP!,{R0-R12} ; Restore general purpose registers
143 ldm SP,{SP,LR}^ ; Restore user/system mode stack pointer and link register
144 nop ; Required by ARM architecture
145 add SP,SP,#0x08 ; Adjust stack pointer
146 ldmfd SP!,{LR} ; Restore the link register (which is the pre-exception PC)
147 add SP,SP,#0x1C ; Clear out the remaining stack space
148 movs PC,LR ; Return from exception