ArmPkg/Include/Chipset/AArch64.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
   5
   6   This program and the accompanying materials
   7   are licensed and made available under the terms and conditions of the BSD License
   8   which accompanies this distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef __AARCH64_H__
  17 #define __AARCH64_H__
  18
  19 #include <Chipset/AArch64Mmu.h>
  20 #include <Chipset/ArmArchTimer.h>
  21
  22 // ARM Interrupt ID in Exception Table
  23 #define ARM_ARCH_EXCEPTION_IRQ            EXCEPT_AARCH64_IRQ
  24
  25 // CPACR - Coprocessor Access Control Register definitions
  26 #define CPACR_TTA_EN            (1UL << 28)
  27 #define CPACR_FPEN_EL1          (1UL << 20)
  28 #define CPACR_FPEN_FULL         (3UL << 20)
  29 #define CPACR_CP_FULL_ACCESS    0x300000
  30
  31 // Coprocessor Trap Register (CPTR)
  32 #define AARCH64_CPTR_TFP        (1 << 10)
  33
  34 // ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions
  35 #define AARCH64_PFR0_FP         (0xF << 16)
  36 #define AARCH64_PFR0_GIC        (0xF << 24)
  37
  38 // SCR - Secure Configuration Register definitions
  39 #define SCR_NS                  (1 << 0)
  40 #define SCR_IRQ                 (1 << 1)
  41 #define SCR_FIQ                 (1 << 2)
  42 #define SCR_EA                  (1 << 3)
  43 #define SCR_FW                  (1 << 4)
  44 #define SCR_AW                  (1 << 5)
  45
  46 // MIDR - Main ID Register definitions
  47 #define ARM_CPU_TYPE_MASK       0xFFF
  48 #define ARM_CPU_TYPE_AEMv8      0xD0F
  49 #define ARM_CPU_TYPE_A53        0xD03
  50 #define ARM_CPU_TYPE_A57        0xD07
  51 #define ARM_CPU_TYPE_A15        0xC0F
  52 #define ARM_CPU_TYPE_A9         0xC09
  53 #define ARM_CPU_TYPE_A5         0xC05
  54
  55 #define ARM_CPU_REV_MASK        ((0xF << 20) | (0xF) )
  56 #define ARM_CPU_REV(rn, pn)     ((((rn) & 0xF) << 20) | ((pn) & 0xF))
  57
  58 // Hypervisor Configuration Register
  59 #define ARM_HCR_FMO                             BIT3
  60 #define ARM_HCR_IMO                             BIT4
  61 #define ARM_HCR_AMO                             BIT5
  62 #define ARM_HCR_TGE                             BIT27
  63
  64 // AArch64 Exception Level
  65 #define AARCH64_EL3       0xC
  66 #define AARCH64_EL2       0x8
  67 #define AARCH64_EL1       0x4
  68
  69 #define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1)
  70
  71 VOID
  72 EFIAPI
  73 ArmEnableSWPInstruction (
  74   VOID
  75   );
  76
  77 UINTN
  78 EFIAPI
  79 ArmReadCbar (
  80   VOID
  81   );
  82
  83 UINTN
  84 EFIAPI
  85 ArmReadTpidrurw (
  86   VOID
  87   );
  88
  89 VOID
  90 EFIAPI
  91 ArmWriteTpidrurw (
  92   UINTN Value
  93   );
  94
  95 UINTN
  96 EFIAPI
  97 ArmGetTCR (
  98   VOID
  99   );
 100
 101 VOID
 102 EFIAPI
 103 ArmSetTCR (
 104   UINTN Value
 105   );
 106
 107 UINTN
 108 EFIAPI
 109 ArmGetMAIR (
 110   VOID
 111   );
 112
 113 VOID
 114 EFIAPI
 115 ArmSetMAIR (
 116   UINTN Value
 117   );
 118
 119 VOID
 120 EFIAPI
 121 ArmDisableAlignmentCheck (
 122   VOID
 123   );
 124
 125 VOID
 126 EFIAPI
 127 ArmEnableAlignmentCheck (
 128   VOID
 129   );
 130
 131 VOID
 132 EFIAPI
 133 ArmDisableAllExceptions (
 134   VOID
 135   );
 136
 137 VOID
 138 ArmWriteHcr (
 139   IN UINTN Hcr
 140   );
 141
 142 UINTN
 143 ArmReadCurrentEL (
 144   VOID
 145   );
 146
 147 UINT64
 148 PageAttributeToGcdAttribute (
 149   IN UINT64 PageAttributes
 150   );
 151
 152 UINT64
 153 GcdAttributeToPageAttribute (
 154   IN UINT64 GcdAttributes
 155   );
 156
 157 UINTN
 158 ArmWriteCptr (
 159   IN  UINT64 Cptr
 160   );
 161
 162 #endif // __AARCH64_H__