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git.proxmox.com Git - mirror_edk2.git/blob - ArmPkg/Include/Chipset/AArch64.h
3 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
4 Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
13 #include <Chipset/AArch64Mmu.h>
15 // ARM Interrupt ID in Exception Table
16 #define ARM_ARCH_EXCEPTION_IRQ EXCEPT_AARCH64_IRQ
18 // CPACR - Coprocessor Access Control Register definitions
19 #define CPACR_TTA_EN (1UL << 28)
20 #define CPACR_FPEN_EL1 (1UL << 20)
21 #define CPACR_FPEN_FULL (3UL << 20)
22 #define CPACR_CP_FULL_ACCESS 0x300000
24 // Coprocessor Trap Register (CPTR)
25 #define AARCH64_CPTR_TFP (1 << 10)
27 // ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions
28 #define AARCH64_PFR0_FP (0xF << 16)
29 #define AARCH64_PFR0_GIC (0xF << 24)
31 // SCR - Secure Configuration Register definitions
32 #define SCR_NS (1 << 0)
33 #define SCR_IRQ (1 << 1)
34 #define SCR_FIQ (1 << 2)
35 #define SCR_EA (1 << 3)
36 #define SCR_FW (1 << 4)
37 #define SCR_AW (1 << 5)
39 // MIDR - Main ID Register definitions
40 #define ARM_CPU_TYPE_SHIFT 4
41 #define ARM_CPU_TYPE_MASK 0xFFF
42 #define ARM_CPU_TYPE_AEMV8 0xD0F
43 #define ARM_CPU_TYPE_A53 0xD03
44 #define ARM_CPU_TYPE_A57 0xD07
45 #define ARM_CPU_TYPE_A72 0xD08
46 #define ARM_CPU_TYPE_A15 0xC0F
47 #define ARM_CPU_TYPE_A9 0xC09
48 #define ARM_CPU_TYPE_A7 0xC07
49 #define ARM_CPU_TYPE_A5 0xC05
51 #define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )
52 #define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))
54 // Hypervisor Configuration Register
55 #define ARM_HCR_FMO BIT3
56 #define ARM_HCR_IMO BIT4
57 #define ARM_HCR_AMO BIT5
58 #define ARM_HCR_TSC BIT19
59 #define ARM_HCR_TGE BIT27
61 // Exception Syndrome Register
62 #define AARCH64_ESR_EC(Ecr) ((0x3F << 26) & (Ecr))
63 #define AARCH64_ESR_ISS(Ecr) ((0x1FFFFFF) & (Ecr))
65 #define AARCH64_ESR_EC_SMC32 (0x13 << 26)
66 #define AARCH64_ESR_EC_SMC64 (0x17 << 26)
68 // AArch64 Exception Level
69 #define AARCH64_EL3 0xC
70 #define AARCH64_EL2 0x8
71 #define AARCH64_EL1 0x4
73 // Saved Program Status Register definitions
78 #define SPSR_AARCH32 BIT4
80 #define SPSR_AARCH32_MODE_USER 0x0
81 #define SPSR_AARCH32_MODE_FIQ 0x1
82 #define SPSR_AARCH32_MODE_IRQ 0x2
83 #define SPSR_AARCH32_MODE_SVC 0x3
84 #define SPSR_AARCH32_MODE_ABORT 0x7
85 #define SPSR_AARCH32_MODE_UNDEF 0xB
86 #define SPSR_AARCH32_MODE_SYS 0xF
88 // Counter-timer Hypervisor Control register definitions
89 #define CNTHCTL_EL2_EL1PCTEN BIT0
90 #define CNTHCTL_EL2_EL1PCEN BIT1
92 #define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1)
94 // Vector table offset definitions
95 #define ARM_VECTOR_CUR_SP0_SYNC 0x000
96 #define ARM_VECTOR_CUR_SP0_IRQ 0x080
97 #define ARM_VECTOR_CUR_SP0_FIQ 0x100
98 #define ARM_VECTOR_CUR_SP0_SERR 0x180
100 #define ARM_VECTOR_CUR_SPX_SYNC 0x200
101 #define ARM_VECTOR_CUR_SPX_IRQ 0x280
102 #define ARM_VECTOR_CUR_SPX_FIQ 0x300
103 #define ARM_VECTOR_CUR_SPX_SERR 0x380
105 #define ARM_VECTOR_LOW_A64_SYNC 0x400
106 #define ARM_VECTOR_LOW_A64_IRQ 0x480
107 #define ARM_VECTOR_LOW_A64_FIQ 0x500
108 #define ARM_VECTOR_LOW_A64_SERR 0x580
110 #define ARM_VECTOR_LOW_A32_SYNC 0x600
111 #define ARM_VECTOR_LOW_A32_IRQ 0x680
112 #define ARM_VECTOR_LOW_A32_FIQ 0x700
113 #define ARM_VECTOR_LOW_A32_SERR 0x780
115 // The ID_AA64MMFR2_EL1 register was added in ARMv8.2. Since we
116 // build for ARMv8.0, we need to define the register here.
117 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
119 #define VECTOR_BASE(tbl) \
120 .section .text.##tbl##,"ax"; \
123 GCC_ASM_EXPORT(tbl); \
126 #define VECTOR_ENTRY(tbl, off) \
129 #define VECTOR_END(tbl) \
135 ArmEnableSWPInstruction (
183 ArmDisableAlignmentCheck (
189 ArmEnableAlignmentCheck (
195 ArmDisableStackAlignmentCheck (
201 ArmEnableStackAlignmentCheck (
207 ArmDisableAllExceptions (
241 #endif // __AARCH64_H__