ArmPkg: Fix Ecc error 8001 in Chipset

This patch fixes the following Ecc reported error:
Only capital letters are allowed to be used
for #define declarations

Edk2 coding standard stating that:
"Names starting with one or two underscores, such as
_MACRO_GUARD_FILE_NAME_H_, must not be used."
the include guard of ArmCortexA5x.h is also updated.

Ref:
https://edk2-docs.gitbook.io/edk-ii-c-coding-standards-specification/
5_source_files/53_include_files#
5-3-5-all-include-file-contents-must-be-protected-by-a-include-guard

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArch64.h
index 7c2b592f92ee65d8df2a36e8be31e802d81a7d1a..09d4cfe28da7b5583654ebc984713db273ac5272 100644 (file)
--- a/ArmPkg/Include/Chipset/AArch64.h
+++ b/ArmPkg/Include/Chipset/AArch64.h
@@ -1,7 +1,7 @@
 /** @file\r
 \r
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-  Copyright (c) 2011 - 2017, ARM Ltd. All rights reserved.<BR>\r
+  Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>\r
 \r
   SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
@@ -39,7 +39,7 @@
 // MIDR - Main ID Register definitions\r
 #define ARM_CPU_TYPE_SHIFT      4\r
 #define ARM_CPU_TYPE_MASK       0xFFF\r
-#define ARM_CPU_TYPE_AEMv8      0xD0F\r
+#define ARM_CPU_TYPE_AEMV8      0xD0F\r
 #define ARM_CPU_TYPE_A53        0xD03\r
 #define ARM_CPU_TYPE_A57        0xD07\r
 #define ARM_CPU_TYPE_A72        0xD08\r
@@ -97,10 +97,10 @@
 #define ARM_VECTOR_CUR_SP0_FIQ  0x100\r
 #define ARM_VECTOR_CUR_SP0_SERR 0x180\r
 \r
-#define ARM_VECTOR_CUR_SPx_SYNC 0x200\r
-#define ARM_VECTOR_CUR_SPx_IRQ  0x280\r
-#define ARM_VECTOR_CUR_SPx_FIQ  0x300\r
-#define ARM_VECTOR_CUR_SPx_SERR 0x380\r
+#define ARM_VECTOR_CUR_SPX_SYNC 0x200\r
+#define ARM_VECTOR_CUR_SPX_IRQ  0x280\r
+#define ARM_VECTOR_CUR_SPX_FIQ  0x300\r
+#define ARM_VECTOR_CUR_SPX_SERR 0x380\r
 \r
 #define ARM_VECTOR_LOW_A64_SYNC 0x400\r
 #define ARM_VECTOR_LOW_A64_IRQ  0x480\r

diff --git a/ArmPkg/Include/Chipset/AArch64Mmu.h b/ArmPkg/Include/Chipset/AArch64Mmu.h
index 606fe7420d6711530e188bba6f86e956b465187d..6c7ada16b18ace0e61cf222b78ac1a5ba20cbf47 100644 (file)
--- a/ArmPkg/Include/Chipset/AArch64Mmu.h
+++ b/ArmPkg/Include/Chipset/AArch64Mmu.h
@@ -1,6 +1,6 @@
 /** @file\r
 *\r
-*  Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+*  Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>\r
 *\r
 *  SPDX-License-Identifier: BSD-2-Clause-Patent\r
 *\r
@@ -190,7 +190,7 @@
 \r
 // The value written to the T*SZ fields are defined as 2^(64-T*SZ). So a 39Bit\r
 // Virtual address range for 512GB of virtual space sets T*SZ to 25\r
-#define INPUT_ADDRESS_SIZE_TO_TxSZ(a)        (64 - a)\r
+#define INPUT_ADDRESS_SIZE_TO_TXSZ(a)        (64 - a)\r
 \r
 // Uses LPAE Page Table format\r
 \r

diff --git a/ArmPkg/Include/Chipset/ArmCortexA5x.h b/ArmPkg/Include/Chipset/ArmCortexA5x.h
index 847a6e00430b332e78a91dcd561b213cd78ca271..e597eee947cf667da7478257f3a6fd807261439b 100644 (file)
--- a/ArmPkg/Include/Chipset/ArmCortexA5x.h
+++ b/ArmPkg/Include/Chipset/ArmCortexA5x.h
@@ -1,13 +1,13 @@
 /** @file\r
 \r
-  Copyright (c) 2012-2014, ARM Limited. All rights reserved.\r
+  Copyright (c) 2012 - 2021, Arm Limited. All rights reserved.<BR>\r
 \r
   SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
 \r
-#ifndef __ARM_CORTEX_A5x_H__\r
-#define __ARM_CORTEX_A5x_H__\r
+#ifndef ARM_CORTEX_A5X_H_\r
+#define ARM_CORTEX_A5X_H_\r
 \r
 //\r
 // Cortex A5x feature bit definitions\r
@@ -41,4 +41,4 @@ ArmUnsetCpuExCrBit (
   IN  UINT64    Bits\r
   );\r
 \r
-#endif\r
+#endif // ARM_CORTEX_A5X_H_\r

diff --git a/ArmPkg/Include/Chipset/ArmV7.h b/ArmPkg/Include/Chipset/ArmV7.h
index fe91031ef33da8f2ca827c367402070e09e64192..025f87a56d1699ebc33a9ee763ff5d77372773f7 100644 (file)
--- a/ArmPkg/Include/Chipset/ArmV7.h
+++ b/ArmPkg/Include/Chipset/ArmV7.h
@@ -1,7 +1,7 @@
 /** @file\r
 \r
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-  Copyright (c) 2011-2015, ARM Ltd. All rights reserved.<BR>\r
+  Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>\r
 \r
   SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
@@ -70,7 +70,7 @@
 // MIDR - Main ID Register definitions\r
 #define ARM_CPU_TYPE_SHIFT      4\r
 #define ARM_CPU_TYPE_MASK       0xFFF\r
-#define ARM_CPU_TYPE_AEMv8      0xD0F\r
+#define ARM_CPU_TYPE_AEMV8      0xD0F\r
 #define ARM_CPU_TYPE_A53        0xD03\r
 #define ARM_CPU_TYPE_A57        0xD07\r
 #define ARM_CPU_TYPE_A15        0xC0F\r

diff --git a/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S b/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S
index 5b10a1339ac184cceb0372415abf596d4c55f806..9202952ee9c0d4e5fcb5d82ed3f768b7d67a1354 100644 (file)
--- a/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S
+++ b/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S
@@ -1,5 +1,5 @@
 //\r
-// Copyright (c) 2011 - 2014 ARM LTD. All rights reserved.<BR>\r
+// Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>\r
 // Portion of Copyright (c) 2014 NVIDIA Corporation. All rights reserved.<BR>\r
 // Copyright (c) 2016 HP Development Company, L.P.\r
 //\r
@@ -200,19 +200,19 @@ ASM_PFX(SErrorSP0):
 //\r
 // Current EL with SPx: 0x200 - 0x380\r
 //\r
-VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_SYNC)\r
+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPX_SYNC)\r
 ASM_PFX(SynchronousExceptionSPx):\r
   ExceptionEntry  EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, SP0\r
 \r
-VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_IRQ)\r
+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPX_IRQ)\r
 ASM_PFX(IrqSPx):\r
   ExceptionEntry  EXCEPT_AARCH64_IRQ\r
 \r
-VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_FIQ)\r
+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPX_FIQ)\r
 ASM_PFX(FiqSPx):\r
   ExceptionEntry  EXCEPT_AARCH64_FIQ\r
 \r
-VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_SERR)\r
+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPX_SERR)\r
 ASM_PFX(SErrorSPx):\r
   ExceptionEntry  EXCEPT_AARCH64_SERROR\r
 \r

diff --git a/ArmPlatformPkg/PrePeiCore/AArch64/Exception.S b/ArmPlatformPkg/PrePeiCore/AArch64/Exception.S
index 59a3da2721e71d6ae2fb7ca1b3c5fa8d334989f7..43e40f97c3eed5ff0b116e8431267a7ca7473d82 100644 (file)
--- a/ArmPlatformPkg/PrePeiCore/AArch64/Exception.S
+++ b/ArmPlatformPkg/PrePeiCore/AArch64/Exception.S
@@ -1,5 +1,5 @@
 #\r
-#  Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
+#  Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>\r
 #\r
 #  SPDX-License-Identifier: BSD-2-Clause-Patent\r
 #\r
@@ -51,22 +51,22 @@ _DefaultSError_t:
   mov  x0, #EXCEPT_AARCH64_SERROR\r
   TO_HANDLER\r
 \r
-VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_SYNC)\r
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPX_SYNC)\r
 _DefaultSyncExceptHandler_h:\r
   mov  x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS\r
   TO_HANDLER\r
 \r
-VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_IRQ)\r
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPX_IRQ)\r
 _DefaultIrq_h:\r
   mov  x0, #EXCEPT_AARCH64_IRQ\r
   TO_HANDLER\r
 \r
-VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_FIQ)\r
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPX_FIQ)\r
 _DefaultFiq_h:\r
   mov  x0, #EXCEPT_AARCH64_FIQ\r
   TO_HANDLER\r
 \r
-VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_SERR)\r
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPX_SERR)\r
 _DefaultSError_h:\r
   mov  x0, #EXCEPT_AARCH64_SERROR\r
   TO_HANDLER\r