3 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
4 Copyright (c) 2011 - 2015, ARM Ltd. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 #include <Uefi/UefiBaseType.h>
22 #include <Chipset/ArmV7.h>
23 #elif defined(MDE_CPU_AARCH64)
24 #include <Chipset/AArch64.h>
26 #error "Unknown chipset."
30 * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
32 * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
33 * be used in Secure World to distinguished Secure to Non-Secure memory.
36 ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
= 0,
37 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED
,
38 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
,
39 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK
,
40 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH
,
41 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH
,
42 ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
,
43 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
44 } ARM_MEMORY_REGION_ATTRIBUTES
;
46 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
49 EFI_PHYSICAL_ADDRESS PhysicalBase
;
50 EFI_VIRTUAL_ADDRESS VirtualBase
;
52 ARM_MEMORY_REGION_ATTRIBUTES Attributes
;
53 } ARM_MEMORY_REGION_DESCRIPTOR
;
55 typedef VOID (*CACHE_OPERATION
)(VOID
);
56 typedef VOID (*LINE_OPERATION
)(UINTN
);
62 ARM_PROCESSOR_MODE_USER
= 0x10,
63 ARM_PROCESSOR_MODE_FIQ
= 0x11,
64 ARM_PROCESSOR_MODE_IRQ
= 0x12,
65 ARM_PROCESSOR_MODE_SUPERVISOR
= 0x13,
66 ARM_PROCESSOR_MODE_ABORT
= 0x17,
67 ARM_PROCESSOR_MODE_HYP
= 0x1A,
68 ARM_PROCESSOR_MODE_UNDEFINED
= 0x1B,
69 ARM_PROCESSOR_MODE_SYSTEM
= 0x1F,
70 ARM_PROCESSOR_MODE_MASK
= 0x1F
76 #define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)
77 #define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)
78 #define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)
79 #define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)
80 #define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)
81 #define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)
83 #define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)
84 #define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)
85 #define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)
86 #define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)
87 #define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)
88 #define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)
93 #define ARM_CORE_AFF0 0xFF
94 #define ARM_CORE_AFF1 (0xFF << 8)
95 #define ARM_CORE_AFF2 (0xFF << 16)
96 #define ARM_CORE_AFF3 (0xFFULL << 32)
98 #define ARM_CORE_MASK ARM_CORE_AFF0
99 #define ARM_CLUSTER_MASK ARM_CORE_AFF1
100 #define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
101 #define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
102 #define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
103 #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
107 ArmDataCacheLineLength (
113 ArmInstructionCacheLineLength (
119 ArmCacheWritebackGranule (
125 ArmIsArchTimerImplemented (
155 ArmInvalidateDataCache (
162 ArmCleanInvalidateDataCache (
174 ArmInvalidateInstructionCache (
180 ArmInvalidateDataCacheEntryByMVA (
186 ArmCleanDataCacheEntryToPoUByMVA(
192 ArmCleanDataCacheEntryByMVA(
198 ArmCleanInvalidateDataCacheEntryByMVA (
204 ArmInvalidateDataCacheEntryBySetWay (
205 IN UINTN SetWayFormat
210 ArmCleanDataCacheEntryBySetWay (
211 IN UINTN SetWayFormat
216 ArmCleanInvalidateDataCacheEntryBySetWay (
217 IN UINTN SetWayFormat
228 ArmDisableDataCache (
234 ArmEnableInstructionCache (
240 ArmDisableInstructionCache (
258 ArmEnableCachesAndMmu (
264 ArmDisableCachesAndMmu (
270 ArmEnableInterrupts (
276 ArmDisableInterrupts (
282 ArmGetInterruptState (
288 ArmEnableAsynchronousAbort (
294 ArmDisableAsynchronousAbort (
329 * Invalidate Data and Instruction TLBs
339 ArmUpdateTranslationTableEntry (
340 IN VOID
*TranslationTableEntry
,
346 ArmSetDomainAccessControl (
353 IN VOID
*TranslationTableBase
358 ArmGetTTBR0BaseAddress (
365 IN ARM_MEMORY_REGION_DESCRIPTOR
*MemoryTable
,
366 OUT VOID
**TranslationTableBase OPTIONAL
,
367 OUT UINTN
*TranslationTableSize OPTIONAL
378 ArmEnableBranchPrediction (
384 ArmDisableBranchPrediction (
402 ArmDataMemoryBarrier (
408 ArmDataSynchronizationBarrier (
414 ArmInstructionSynchronizationBarrier (
504 Get the Secure Configuration Register value
506 @return Value read from the Secure Configuration Register
516 Set the Secure Configuration Register
518 @param Value Value to write to the Secure Configuration Register
536 IN UINT32 VectorMonitorBase
554 IN UINTN HypModeVectorBase
559 // Helper functions for accessing CPU ACTLR
582 ArmUnsetCpuActlrBit (
587 ArmSetMemoryRegionNoExec (
588 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
593 ArmClearMemoryRegionNoExec (
594 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
599 ArmSetMemoryRegionReadOnly (
600 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
605 ArmClearMemoryRegionReadOnly (
606 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
610 #endif // __ARM_LIB__