2 * File managing the MMU for ARMv8 architecture
4 * Copyright (c) 2011-2013, ARM Limited. All rights reserved.
6 * This program and the accompanying materials
7 * are licensed and made available under the terms and conditions of the BSD License
8 * which accompanies this distribution. The full text of the license may be found at
9 * http://opensource.org/licenses/bsd-license.php
11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 #include <Chipset/AArch64.h>
18 #include <Library/BaseMemoryLib.h>
19 #include <Library/MemoryAllocationLib.h>
20 #include <Library/ArmLib.h>
21 #include <Library/BaseLib.h>
22 #include <Library/DebugLib.h>
23 #include "AArch64Lib.h"
24 #include "ArmLibPrivate.h"
26 // We use this index definition to define an invalid block entry
27 #define TT_ATTR_INDX_INVALID ((UINT32)~0)
31 ArmMemoryAttributeToPageAttribute (
32 IN ARM_MEMORY_REGION_ATTRIBUTES Attributes
36 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
:
37 return TT_ATTR_INDX_MEMORY_WRITE_BACK
;
38 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH
:
39 return TT_ATTR_INDX_MEMORY_WRITE_THROUGH
;
40 case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
:
41 return TT_ATTR_INDX_DEVICE_MEMORY
;
42 case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
:
43 return TT_ATTR_INDX_MEMORY_NON_CACHEABLE
;
44 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK
:
45 return TT_ATTR_INDX_MEMORY_WRITE_BACK
;
46 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH
:
47 return TT_ATTR_INDX_MEMORY_WRITE_THROUGH
;
48 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
:
49 return TT_ATTR_INDX_DEVICE_MEMORY
;
50 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED
:
51 return TT_ATTR_INDX_MEMORY_NON_CACHEABLE
;
54 return TT_ATTR_INDX_DEVICE_MEMORY
;
59 PageAttributeToGcdAttribute (
60 IN UINT64 PageAttributes
65 switch (PageAttributes
& TT_ATTR_INDX_MASK
) {
66 case TT_ATTR_INDX_DEVICE_MEMORY
:
67 GcdAttributes
= EFI_MEMORY_UC
;
69 case TT_ATTR_INDX_MEMORY_NON_CACHEABLE
:
70 GcdAttributes
= EFI_MEMORY_WC
;
72 case TT_ATTR_INDX_MEMORY_WRITE_THROUGH
:
73 GcdAttributes
= EFI_MEMORY_WT
;
75 case TT_ATTR_INDX_MEMORY_WRITE_BACK
:
76 GcdAttributes
= EFI_MEMORY_WB
;
79 DEBUG ((EFI_D_ERROR
, "PageAttributeToGcdAttribute: PageAttributes:0x%lX not supported.\n", PageAttributes
));
81 // The Global Coherency Domain (GCD) value is defined as a bit set.
82 // Returning 0 means no attribute has been set.
86 // Determine protection attributes
87 if (((PageAttributes
& TT_AP_MASK
) == TT_AP_NO_RO
) || ((PageAttributes
& TT_AP_MASK
) == TT_AP_RO_RO
)) {
88 // Read only cases map to write-protect
89 GcdAttributes
|= EFI_MEMORY_WP
;
92 // Process eXecute Never attribute
93 if ((PageAttributes
& (TT_PXN_MASK
| TT_UXN_MASK
)) != 0 ) {
94 GcdAttributes
|= EFI_MEMORY_XP
;
101 GcdAttributeToPageAttribute (
102 IN UINT64 GcdAttributes
105 UINT64 PageAttributes
;
107 switch (GcdAttributes
& 0xFF) {
109 PageAttributes
= TT_ATTR_INDX_DEVICE_MEMORY
;
112 PageAttributes
= TT_ATTR_INDX_MEMORY_NON_CACHEABLE
;
115 PageAttributes
= TT_ATTR_INDX_MEMORY_WRITE_THROUGH
;
118 PageAttributes
= TT_ATTR_INDX_MEMORY_WRITE_BACK
;
121 DEBUG ((EFI_D_ERROR
, "GcdAttributeToPageAttribute: 0x%X attributes is not supported.\n", GcdAttributes
));
123 // If no match has been found then we mark the memory as device memory.
124 // The only side effect of using device memory should be a slow down in the performance.
125 PageAttributes
= TT_ATTR_INDX_DEVICE_MEMORY
;
128 // Determine protection attributes
129 if (GcdAttributes
& EFI_MEMORY_WP
) {
130 // Read only cases map to write-protect
131 PageAttributes
|= TT_AP_RO_RO
;
134 // Process eXecute Never attribute
135 if (GcdAttributes
& EFI_MEMORY_XP
) {
136 PageAttributes
|= (TT_PXN_MASK
| TT_UXN_MASK
);
139 return PageAttributes
;
142 ARM_MEMORY_REGION_ATTRIBUTES
143 GcdAttributeToArmAttribute (
144 IN UINT64 GcdAttributes
147 switch (GcdAttributes
& 0xFF) {
149 return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
;
151 return ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
;
153 return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH
;
155 return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
;
157 DEBUG ((EFI_D_ERROR
, "GcdAttributeToArmAttribute: 0x%lX attributes is not supported.\n", GcdAttributes
));
159 return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
;
163 // Describe the T0SZ values for each translation table level
167 UINTN LargestT0SZ
; // Generally (MaxT0SZ == LargestT0SZ) but at the Level3 Table
168 // the MaxT0SZ is not at the boundary of the table
169 } T0SZ_DESCRIPTION_PER_LEVEL
;
171 // Map table for the corresponding Level of Table
172 STATIC CONST T0SZ_DESCRIPTION_PER_LEVEL T0SZPerTableLevel
[] = {
173 { 16, 24, 24 }, // Table Level 0
174 { 25, 33, 33 }, // Table Level 1
175 { 34, 39, 42 } // Table Level 2
179 GetRootTranslationTableInfo (
181 OUT UINTN
*TableLevel
,
182 OUT UINTN
*TableEntryCount
187 // Identify the level of the root table from the given T0SZ
188 for (Index
= 0; Index
< sizeof (T0SZPerTableLevel
) / sizeof (T0SZ_DESCRIPTION_PER_LEVEL
); Index
++) {
189 if (T0SZ
<= T0SZPerTableLevel
[Index
].MaxT0SZ
) {
194 // If we have not found the corresponding maximum T0SZ then we use the last one
195 if (Index
== sizeof (T0SZPerTableLevel
) / sizeof (T0SZ_DESCRIPTION_PER_LEVEL
)) {
199 // Get the level of the root table
204 // The Size of the Table is 2^(T0SZ-LargestT0SZ)
205 if (TableEntryCount
) {
206 *TableEntryCount
= 1 << (T0SZPerTableLevel
[Index
].LargestT0SZ
- T0SZ
+ 1);
212 LookupAddresstoRootTable (
213 IN UINT64 MaxAddress
,
215 OUT UINTN
*TableEntryCount
220 // Check the parameters are not NULL
221 ASSERT ((T0SZ
!= NULL
) && (TableEntryCount
!= NULL
));
223 // Look for the highest bit set in MaxAddress
224 for (TopBit
= 63; TopBit
!= 0; TopBit
--) {
225 if ((1ULL << TopBit
) & MaxAddress
) {
226 // MaxAddress top bit is found
231 ASSERT (TopBit
!= 0);
233 // Calculate T0SZ from the top bit of the MaxAddress
236 // Get the Table info from T0SZ
237 GetRootTranslationTableInfo (*T0SZ
, NULL
, TableEntryCount
);
242 GetBlockEntryListFromAddress (
243 IN UINT64
*RootTable
,
244 IN UINT64 RegionStart
,
245 OUT UINTN
*TableLevel
,
246 IN OUT UINT64
*BlockEntrySize
,
247 IN OUT UINT64
**LastBlockEntry
250 UINTN RootTableLevel
;
251 UINTN RootTableEntryCount
;
252 UINT64
*TranslationTable
;
254 UINT64 BlockEntryAddress
;
255 UINTN BaseAddressAlignment
;
261 UINT64 TableAttributes
;
263 // Initialize variable
266 // Ensure the parameters are valid
267 ASSERT (TableLevel
&& BlockEntrySize
&& LastBlockEntry
);
269 // Ensure the Region is aligned on 4KB boundary
270 ASSERT ((RegionStart
& (SIZE_4KB
- 1)) == 0);
272 // Ensure the required size is aligned on 4KB boundary
273 ASSERT ((*BlockEntrySize
& (SIZE_4KB
- 1)) == 0);
276 // Calculate LastBlockEntry from T0SZ - this is the last block entry of the root Translation table
278 T0SZ
= ArmGetTCR () & TCR_T0SZ_MASK
;
279 // Get the Table info from T0SZ
280 GetRootTranslationTableInfo (T0SZ
, &RootTableLevel
, &RootTableEntryCount
);
281 // The last block of the root table depends on the number of entry in this table
282 *LastBlockEntry
= (UINT64
*)((UINTN
)RootTable
+ ((RootTableEntryCount
- 1) * sizeof(UINT64
)));
284 // If the start address is 0x0 then we use the size of the region to identify the alignment
285 if (RegionStart
== 0) {
286 // Identify the highest possible alignment for the Region Size
287 for (BaseAddressAlignment
= 0; BaseAddressAlignment
< 64; BaseAddressAlignment
++) {
288 if ((1 << BaseAddressAlignment
) & *BlockEntrySize
) {
293 // Identify the highest possible alignment for the Base Address
294 for (BaseAddressAlignment
= 0; BaseAddressAlignment
< 64; BaseAddressAlignment
++) {
295 if ((1 << BaseAddressAlignment
) & RegionStart
) {
301 // Identify the Page Level the RegionStart must belongs to
302 PageLevel
= 3 - ((BaseAddressAlignment
- 12) / 9);
304 // If the required size is smaller than the current block size then we need to go to the page below.
305 // The PageLevel was calculated on the Base Address alignment but did not take in account the alignment
306 // of the allocation size
307 if (*BlockEntrySize
< TT_BLOCK_ENTRY_SIZE_AT_LEVEL (PageLevel
)) {
308 // It does not fit so we need to go a page level above
312 // Expose the found PageLevel to the caller
313 *TableLevel
= PageLevel
;
315 // Now, we have the Table Level we can get the Block Size associated to this table
316 *BlockEntrySize
= TT_BLOCK_ENTRY_SIZE_AT_LEVEL (PageLevel
);
319 // Get the Table Descriptor for the corresponding PageLevel. We need to decompose RegionStart to get appropriate entries
322 TranslationTable
= RootTable
;
323 for (IndexLevel
= RootTableLevel
; IndexLevel
<= PageLevel
; IndexLevel
++) {
324 BlockEntry
= (UINT64
*)TT_GET_ENTRY_FOR_ADDRESS (TranslationTable
, IndexLevel
, RegionStart
);
326 if ((IndexLevel
!= 3) && ((*BlockEntry
& TT_TYPE_MASK
) == TT_TYPE_TABLE_ENTRY
)) {
327 // Go to the next table
328 TranslationTable
= (UINT64
*)(*BlockEntry
& TT_ADDRESS_MASK_DESCRIPTION_TABLE
);
330 // If we are at the last level then update the output
331 if (IndexLevel
== PageLevel
) {
332 // And get the appropriate BlockEntry at the next level
333 BlockEntry
= (UINT64
*)TT_GET_ENTRY_FOR_ADDRESS (TranslationTable
, IndexLevel
+ 1, RegionStart
);
335 // Set the last block for this new table
336 *LastBlockEntry
= (UINT64
*)((UINTN
)TranslationTable
+ ((TT_ENTRY_COUNT
- 1) * sizeof(UINT64
)));
338 } else if ((*BlockEntry
& TT_TYPE_MASK
) == TT_TYPE_BLOCK_ENTRY
) {
339 // If we are not at the last level then we need to split this BlockEntry
340 if (IndexLevel
!= PageLevel
) {
341 // Retrieve the attributes from the block entry
342 Attributes
= *BlockEntry
& TT_ATTRIBUTES_MASK
;
344 // Convert the block entry attributes into Table descriptor attributes
345 TableAttributes
= TT_TABLE_AP_NO_PERMISSION
;
346 if (Attributes
& TT_PXN_MASK
) {
347 TableAttributes
= TT_TABLE_PXN
;
349 if (Attributes
& TT_UXN_MASK
) {
350 TableAttributes
= TT_TABLE_XN
;
352 if (Attributes
& TT_NS
) {
353 TableAttributes
= TT_TABLE_NS
;
356 // Get the address corresponding at this entry
357 BlockEntryAddress
= RegionStart
;
358 BlockEntryAddress
= BlockEntryAddress
>> TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel
);
359 // Shift back to right to set zero before the effective address
360 BlockEntryAddress
= BlockEntryAddress
<< TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel
);
362 // Set the correct entry type for the next page level
363 if ((IndexLevel
+ 1) == 3) {
364 Attributes
|= TT_TYPE_BLOCK_ENTRY_LEVEL3
;
366 Attributes
|= TT_TYPE_BLOCK_ENTRY
;
369 // Create a new translation table
370 TranslationTable
= (UINT64
*)AllocatePages (EFI_SIZE_TO_PAGES((TT_ENTRY_COUNT
* sizeof(UINT64
)) + TT_ALIGNMENT_DESCRIPTION_TABLE
));
371 if (TranslationTable
== NULL
) {
374 TranslationTable
= (UINT64
*)((UINTN
)TranslationTable
& TT_ADDRESS_MASK_DESCRIPTION_TABLE
);
376 // Fill the BlockEntry with the new TranslationTable
377 *BlockEntry
= ((UINTN
)TranslationTable
& TT_ADDRESS_MASK_DESCRIPTION_TABLE
) | TableAttributes
| TT_TYPE_TABLE_ENTRY
;
378 // Update the last block entry with the newly created translation table
379 *LastBlockEntry
= (UINT64
*)((UINTN
)TranslationTable
+ ((TT_ENTRY_COUNT
- 1) * sizeof(UINT64
)));
381 // Populate the newly created lower level table
382 BlockEntry
= TranslationTable
;
383 for (Index
= 0; Index
< TT_ENTRY_COUNT
; Index
++) {
384 *BlockEntry
= Attributes
| (BlockEntryAddress
+ (Index
<< TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel
+ 1)));
387 // Block Entry points at the beginning of the Translation Table
388 BlockEntry
= TranslationTable
;
391 // Case of Invalid Entry and we are at a page level above of the one targetted.
392 if (IndexLevel
!= PageLevel
) {
393 // Create a new translation table
394 TranslationTable
= (UINT64
*)AllocatePages (EFI_SIZE_TO_PAGES((TT_ENTRY_COUNT
* sizeof(UINT64
)) + TT_ALIGNMENT_DESCRIPTION_TABLE
));
395 if (TranslationTable
== NULL
) {
398 TranslationTable
= (UINT64
*)((UINTN
)TranslationTable
& TT_ADDRESS_MASK_DESCRIPTION_TABLE
);
400 ZeroMem (TranslationTable
, TT_ENTRY_COUNT
* sizeof(UINT64
));
402 // Fill the new BlockEntry with the TranslationTable
403 *BlockEntry
= ((UINTN
)TranslationTable
& TT_ADDRESS_MASK_DESCRIPTION_TABLE
) | TT_TYPE_TABLE_ENTRY
;
413 FillTranslationTable (
414 IN UINT64
*RootTable
,
415 IN ARM_MEMORY_REGION_DESCRIPTOR
*MemoryRegion
421 UINT64 RemainingRegionLength
;
423 UINT64
*LastBlockEntry
;
424 UINT64 BlockEntrySize
;
427 // Ensure the Length is aligned on 4KB boundary
428 ASSERT ((MemoryRegion
->Length
> 0) && ((MemoryRegion
->Length
& (SIZE_4KB
- 1)) == 0));
430 // Variable initialization
431 Attributes
= ArmMemoryAttributeToPageAttribute (MemoryRegion
->Attributes
) | TT_AF
;
432 RemainingRegionLength
= MemoryRegion
->Length
;
433 RegionStart
= MemoryRegion
->VirtualBase
;
436 // Get the first Block Entry that matches the Virtual Address and also the information on the Table Descriptor
437 // such as the the size of the Block Entry and the address of the last BlockEntry of the Table Descriptor
438 BlockEntrySize
= RemainingRegionLength
;
439 BlockEntry
= GetBlockEntryListFromAddress (RootTable
, RegionStart
, &TableLevel
, &BlockEntrySize
, &LastBlockEntry
);
440 if (BlockEntry
== NULL
) {
441 // GetBlockEntryListFromAddress() return NULL when it fails to allocate new pages from the Translation Tables
442 return RETURN_OUT_OF_RESOURCES
;
445 if (TableLevel
!= 3) {
446 Type
= TT_TYPE_BLOCK_ENTRY
;
448 Type
= TT_TYPE_BLOCK_ENTRY_LEVEL3
;
452 // Fill the Block Entry with attribute and output block address
453 *BlockEntry
= (RegionStart
& TT_ADDRESS_MASK_BLOCK_ENTRY
) | Attributes
| Type
;
455 // Go to the next BlockEntry
456 RegionStart
+= BlockEntrySize
;
457 RemainingRegionLength
-= BlockEntrySize
;
459 } while ((RemainingRegionLength
>= BlockEntrySize
) && (BlockEntry
<= LastBlockEntry
));
460 } while (RemainingRegionLength
!= 0);
462 return RETURN_SUCCESS
;
466 SetMemoryAttributes (
467 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
469 IN UINT64 Attributes
,
470 IN EFI_PHYSICAL_ADDRESS VirtualMask
473 RETURN_STATUS Status
;
474 ARM_MEMORY_REGION_DESCRIPTOR MemoryRegion
;
475 UINT64
*TranslationTable
;
477 MemoryRegion
.PhysicalBase
= BaseAddress
;
478 MemoryRegion
.VirtualBase
= BaseAddress
;
479 MemoryRegion
.Length
= Length
;
480 MemoryRegion
.Attributes
= GcdAttributeToArmAttribute (Attributes
);
482 TranslationTable
= ArmGetTTBR0BaseAddress ();
484 Status
= FillTranslationTable (TranslationTable
, &MemoryRegion
);
485 if (RETURN_ERROR (Status
)) {
489 // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks
490 // flush and invalidate pages
491 ArmCleanInvalidateDataCache ();
493 ArmInvalidateInstructionCache ();
495 // Invalidate all TLB entries so changes are synced
498 return RETURN_SUCCESS
;
504 IN ARM_MEMORY_REGION_DESCRIPTOR
*MemoryTable
,
505 OUT VOID
**TranslationTableBase OPTIONAL
,
506 OUT UINTN
*TranslationTableSize OPTIONAL
509 VOID
* TranslationTable
;
510 UINTN TranslationTablePageCount
;
511 UINT32 TranslationTableAttribute
;
512 ARM_MEMORY_REGION_DESCRIPTOR
*MemoryTableEntry
;
516 UINTN RootTableEntryCount
;
518 RETURN_STATUS Status
;
520 ASSERT (MemoryTable
!= NULL
);
522 // Identify the highest address of the memory table
523 MaxAddress
= MemoryTable
->PhysicalBase
+ MemoryTable
->Length
- 1;
524 MemoryTableEntry
= MemoryTable
;
525 while (MemoryTableEntry
->Length
!= 0) {
526 TopAddress
= MemoryTableEntry
->PhysicalBase
+ MemoryTableEntry
->Length
- 1;
527 if (TopAddress
> MaxAddress
) {
528 MaxAddress
= TopAddress
;
533 // Lookup the Table Level to get the information
534 LookupAddresstoRootTable (MaxAddress
, &T0SZ
, &RootTableEntryCount
);
537 // Set TCR that allows us to retrieve T0SZ in the subsequent functions
539 // Ideally we will be running at EL2, but should support EL1 as well.
540 // UEFI should not run at EL3.
541 if (ArmReadCurrentEL () == AARCH64_EL2
) {
542 //Note: Bits 23 and 31 are reserved(RES1) bits in TCR_EL2
543 TCR
= T0SZ
| (1UL << 31) | (1UL << 23) | TCR_TG0_4KB
;
545 // Set the Physical Address Size using MaxAddress
546 if (MaxAddress
< SIZE_4GB
) {
548 } else if (MaxAddress
< SIZE_64GB
) {
550 } else if (MaxAddress
< SIZE_1TB
) {
552 } else if (MaxAddress
< SIZE_4TB
) {
554 } else if (MaxAddress
< SIZE_16TB
) {
556 } else if (MaxAddress
< SIZE_256TB
) {
559 DEBUG ((EFI_D_ERROR
, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", MaxAddress
));
560 ASSERT (0); // Bigger than 48-bit memory space are not supported
561 return RETURN_UNSUPPORTED
;
563 } else if (ArmReadCurrentEL () == AARCH64_EL1
) {
564 TCR
= T0SZ
| TCR_TG0_4KB
;
566 // Set the Physical Address Size using MaxAddress
567 if (MaxAddress
< SIZE_4GB
) {
569 } else if (MaxAddress
< SIZE_64GB
) {
571 } else if (MaxAddress
< SIZE_1TB
) {
573 } else if (MaxAddress
< SIZE_4TB
) {
575 } else if (MaxAddress
< SIZE_16TB
) {
577 } else if (MaxAddress
< SIZE_256TB
) {
578 TCR
|= TCR_IPS_256TB
;
580 DEBUG ((EFI_D_ERROR
, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", MaxAddress
));
581 ASSERT (0); // Bigger than 48-bit memory space are not supported
582 return RETURN_UNSUPPORTED
;
585 ASSERT (0); // UEFI is only expected to run at EL2 and EL1, not EL3.
586 return RETURN_UNSUPPORTED
;
592 // Allocate pages for translation table
593 TranslationTablePageCount
= EFI_SIZE_TO_PAGES((RootTableEntryCount
* sizeof(UINT64
)) + TT_ALIGNMENT_DESCRIPTION_TABLE
);
594 TranslationTable
= AllocatePages (TranslationTablePageCount
);
595 if (TranslationTable
== NULL
) {
596 return RETURN_OUT_OF_RESOURCES
;
598 TranslationTable
= (VOID
*)((UINTN
)TranslationTable
& TT_ADDRESS_MASK_DESCRIPTION_TABLE
);
599 // We set TTBR0 just after allocating the table to retrieve its location from the subsequent
600 // functions without needing to pass this value across the functions. The MMU is only enabled
601 // after the translation tables are populated.
602 ArmSetTTBR0 (TranslationTable
);
604 if (TranslationTableBase
!= NULL
) {
605 *TranslationTableBase
= TranslationTable
;
608 if (TranslationTableSize
!= NULL
) {
609 *TranslationTableSize
= RootTableEntryCount
* sizeof(UINT64
);
612 ZeroMem (TranslationTable
, RootTableEntryCount
* sizeof(UINT64
));
614 // Disable MMU and caches. ArmDisableMmu() also invalidates the TLBs
616 ArmDisableDataCache ();
617 ArmDisableInstructionCache ();
619 // Make sure nothing sneaked into the cache
620 ArmCleanInvalidateDataCache ();
621 ArmInvalidateInstructionCache ();
623 TranslationTableAttribute
= TT_ATTR_INDX_INVALID
;
624 while (MemoryTable
->Length
!= 0) {
625 // Find the memory attribute for the Translation Table
626 if (((UINTN
)TranslationTable
>= MemoryTable
->PhysicalBase
) &&
627 ((UINTN
)TranslationTable
<= MemoryTable
->PhysicalBase
- 1 + MemoryTable
->Length
)) {
628 TranslationTableAttribute
= MemoryTable
->Attributes
;
631 Status
= FillTranslationTable (TranslationTable
, MemoryTable
);
632 if (RETURN_ERROR (Status
)) {
633 goto FREE_TRANSLATION_TABLE
;
638 // Translate the Memory Attributes into Translation Table Register Attributes
639 if ((TranslationTableAttribute
== ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
) ||
640 (TranslationTableAttribute
== ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED
)) {
641 TCR
|= TCR_SH_NON_SHAREABLE
| TCR_RGN_OUTER_NON_CACHEABLE
| TCR_RGN_INNER_NON_CACHEABLE
;
642 } else if ((TranslationTableAttribute
== ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
) ||
643 (TranslationTableAttribute
== ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK
)) {
644 TCR
|= TCR_SH_INNER_SHAREABLE
| TCR_RGN_OUTER_WRITE_BACK_ALLOC
| TCR_RGN_INNER_WRITE_BACK_ALLOC
;
645 } else if ((TranslationTableAttribute
== ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH
) ||
646 (TranslationTableAttribute
== ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH
)) {
647 TCR
|= TCR_SH_NON_SHAREABLE
| TCR_RGN_OUTER_WRITE_THROUGH
| TCR_RGN_INNER_WRITE_THROUGH
;
649 // If we failed to find a mapping that contains the root translation table then it probably means the translation table
650 // is not mapped in the given memory map.
652 Status
= RETURN_UNSUPPORTED
;
653 goto FREE_TRANSLATION_TABLE
;
656 ArmSetMAIR (MAIR_ATTR(TT_ATTR_INDX_DEVICE_MEMORY
, MAIR_ATTR_DEVICE_MEMORY
) | // mapped to EFI_MEMORY_UC
657 MAIR_ATTR(TT_ATTR_INDX_MEMORY_NON_CACHEABLE
, MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE
) | // mapped to EFI_MEMORY_WC
658 MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_THROUGH
, MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH
) | // mapped to EFI_MEMORY_WT
659 MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_BACK
, MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK
)); // mapped to EFI_MEMORY_WB
661 ArmDisableAlignmentCheck ();
662 ArmEnableInstructionCache ();
663 ArmEnableDataCache ();
666 return RETURN_SUCCESS
;
668 FREE_TRANSLATION_TABLE
:
669 FreePages (TranslationTable
, TranslationTablePageCount
);