1 //------------------------------------------------------------------------------
3 // Copyright (c) 2008-2009 Apple Inc. All rights reserved.
5 // All rights reserved. This program and the accompanying materials
6 // are licensed and made available under the terms and conditions of the BSD License
7 // which accompanies this distribution. The full text of the license may be found at
8 // http://opensource.org/licenses/bsd-license.php
10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 //------------------------------------------------------------------------------
15 EXPORT ArmInvalidateInstructionCache
16 EXPORT ArmInvalidateDataCacheEntryByMVA
17 EXPORT ArmCleanDataCacheEntryByMVA
18 EXPORT ArmCleanInvalidateDataCacheEntryByMVA
19 EXPORT ArmInvalidateDataCacheEntryBySetWay
20 EXPORT ArmCleanDataCacheEntryBySetWay
21 EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
22 EXPORT ArmDrainWriteBuffer
26 EXPORT ArmEnableDataCache
27 EXPORT ArmDisableDataCache
28 EXPORT ArmEnableInstructionCache
29 EXPORT ArmDisableInstructionCache
30 EXPORT ArmEnableBranchPrediction
31 EXPORT ArmDisableBranchPrediction
32 EXPORT ArmV7AllDataCachesOperation
34 DC_ON EQU ( 0x1:SHL:2 )
35 IC_ON EQU ( 0x1:SHL:12 )
38 AREA ArmCacheLib, CODE, READONLY
42 ArmInvalidateDataCacheEntryByMVA
43 MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
49 ArmCleanDataCacheEntryByMVA
50 MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
56 ArmCleanInvalidateDataCacheEntryByMVA
57 MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
63 ArmInvalidateDataCacheEntryBySetWay
64 mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
70 ArmCleanInvalidateDataCacheEntryBySetWay
71 mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
77 ArmCleanDataCacheEntryBySetWay
78 mcr p15, 0, r0, c7, c10, 2 ; Clean this line
85 mcr p15, 0, r0, c7, c10, 4 ; Drain write buffer for sync
91 ArmInvalidateInstructionCache
93 MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
95 MCR p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
116 mcr p15,0,R0,c13,c0,0 ;FCSE PID register must be cleared before disabling MMU
119 mcr p15,0,R0,c1,c0,0 ;Disable MMU
126 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
127 ORR R0,R0,R1 ;Set C bit
128 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
135 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
136 BIC R0,R0,R1 ;Clear C bit
137 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
141 ArmEnableInstructionCache
143 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
144 ORR R0,R0,R1 ;Set I bit
145 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
149 ArmDisableInstructionCache
151 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
152 BIC R0,R0,R1 ;Clear I bit.
153 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
157 ArmEnableBranchPrediction
158 mrc p15, 0, r0, c1, c0, 0
159 orr r0, r0, #0x00000800
160 mcr p15, 0, r0, c1, c0, 0
164 ArmDisableBranchPrediction
165 mrc p15, 0, r0, c1, c0, 0
166 bic r0, r0, #0x00000800
167 mcr p15, 0, r0, c1, c0, 0
172 ArmV7AllDataCachesOperation
173 STMFD SP!,{r4-r12, LR}
174 MOV R1, R0 ; Save Function call in R1
175 MRC p15, 1, R6, c0, c0, 1 ; Read CLIDR
176 ANDS R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)
177 MOV R3, R3, LSR #23 ; Cache level value (naturally aligned)
182 ADD R2, R10, R10, LSR #1 ; Work out 3xcachelevel
183 MOV R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
184 AND R12, R12, #7 ; get those 3 bits alone
186 BLT Skip ; no cache or only instruction cache at this level
187 MCR p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
188 ISB ; ISB to sync the change to the CacheSizeID reg
189 MRC p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
190 AND R2, R12, #&7 ; extract the line length field
191 ADD R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)
193 ANDS R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
194 CLZ R5, R4 ; R5 is the bit position of the way size increment
196 ANDS R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)
199 MOV R9, R4 ; R9 working copy of the max way size (right aligned)
202 ORR R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11
203 ORR R0, R0, R7, LSL R2 ; factor in the index number
207 SUBS R9, R9, #1 ; decrement the way number
209 SUBS R7, R7, #1 ; decrement the index
212 ADD R10, R10, #2 ; increment the cache number
217 LDMFD SP!, {r4-r12, lr}