[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmV7Support.asm

//------------------------------------------------------------------------------ 
//
// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
//
// All rights reserved. This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution.  The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------

    EXPORT  ArmInvalidateInstructionCache
    EXPORT  ArmInvalidateDataCacheEntryByMVA
    EXPORT  ArmCleanDataCacheEntryByMVA
    EXPORT  ArmCleanInvalidateDataCacheEntryByMVA
    EXPORT  ArmInvalidateDataCacheEntryBySetWay
    EXPORT  ArmCleanDataCacheEntryBySetWay
    EXPORT  ArmCleanInvalidateDataCacheEntryBySetWay
    EXPORT  ArmDrainWriteBuffer
    EXPORT  ArmEnableMmu
    EXPORT  ArmDisableMmu
    EXPORT  ArmMmuEnabled
    EXPORT  ArmEnableDataCache
    EXPORT  ArmDisableDataCache
    EXPORT  ArmEnableInstructionCache
    EXPORT  ArmDisableInstructionCache
    EXPORT  ArmEnableBranchPrediction
    EXPORT  ArmDisableBranchPrediction
    EXPORT  ArmV7AllDataCachesOperation

DC_ON       EQU     ( 0x1:SHL:2 )
IC_ON       EQU     ( 0x1:SHL:12 )


    AREA    ArmCacheLib, CODE, READONLY
    PRESERVE8


ArmInvalidateDataCacheEntryByMVA
  MCR     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line       
  DSB
  ISB
  BX      lr


ArmCleanDataCacheEntryByMVA
  MCR     p15, 0, r0, c7, c10, 1  ; clean single data cache line     
  DSB
  ISB
  BX      lr


ArmCleanInvalidateDataCacheEntryByMVA
  MCR     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line
  DSB
  ISB
  BX      lr


ArmInvalidateDataCacheEntryBySetWay
  mcr     p15, 0, r0, c7, c6, 2        ; Invalidate this line		
  DSB
  ISB
  bx      lr


ArmCleanInvalidateDataCacheEntryBySetWay
  mcr     p15, 0, r0, c7, c14, 2       ; Clean and Invalidate this line		
  DSB
  ISB
  bx      lr


ArmCleanDataCacheEntryBySetWay
  mcr     p15, 0, r0, c7, c10, 2       ; Clean this line		
  DSB
  ISB
  bx      lr


ArmDrainWriteBuffer
  mcr     p15, 0, r0, c7, c10, 4       ; Drain write buffer for sync
  DSB
  ISB
  bx      lr


ArmInvalidateInstructionCache
  MOV     R0,#0
  MCR     p15,0,R0,c7,c5,0      ;Invalidate entire instruction cache
  MOV     R0,#0
  MCR     p15,0,R0,c7,c5,4      ;Instruction synchronization barrier
  DSB
  ISB
  BX      LR

ArmEnableMmu
  mrc     p15,0,R0,c1,c0,0
  orr     R0,R0,#1
  mcr     p15,0,R0,c1,c0,0
  DSB
  ISB
  bx      LR

ArmMmuEnabled
  mrc     p15,0,R0,c1,c0,0
  and     R0,R0,#1
  ISB
  bx      LR

ArmDisableMmu
  mov     R0,#0
  mcr     p15,0,R0,c13,c0,0     ;FCSE PID register must be cleared before disabling MMU
  mrc     p15,0,R0,c1,c0,0
  bic     R0,R0,#1
  mcr     p15,0,R0,c1,c0,0      ;Disable MMU
  DSB
  ISB
  bx      LR

ArmEnableDataCache
  LDR     R1,=DC_ON
  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
  ORR     R0,R0,R1              ;Set C bit
  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
  DSB
  ISB
  BX      LR
    
ArmDisableDataCache
  LDR     R1,=DC_ON
  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
  BIC     R0,R0,R1              ;Clear C bit
  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
  ISB
  BX      LR

ArmEnableInstructionCache
  LDR     R1,=IC_ON
  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
  ORR     R0,R0,R1              ;Set I bit
  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
  ISB
  BX      LR
  
ArmDisableInstructionCache
  LDR     R1,=IC_ON
  MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data
  BIC     R0,R0,R1             ;Clear I bit.
  MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data
  ISB
  BX      LR

ArmEnableBranchPrediction
  mrc     p15, 0, r0, c1, c0, 0
  orr     r0, r0, #0x00000800
  mcr     p15, 0, r0, c1, c0, 0
  ISB
  bx      LR

ArmDisableBranchPrediction
  mrc     p15, 0, r0, c1, c0, 0
  bic     r0, r0, #0x00000800
  mcr     p15, 0, r0, c1, c0, 0
  ISB
  bx      LR


ArmV7AllDataCachesOperation
  STMFD SP!,{r4-r12, LR}
  MOV   R1, R0                ; Save Function call in R1
  MRC   p15, 1, R6, c0, c0, 1 ; Read CLIDR
  ANDS  R3, R6, #&7000000     ; Mask out all but Level of Coherency (LoC)
  MOV   R3, R3, LSR #23       ; Cache level value (naturally aligned)
  BEQ   Finished
  MOV   R10, #0

Loop1   
  ADD   R2, R10, R10, LSR #1  ; Work out 3xcachelevel
  MOV   R12, R6, LSR R2       ; bottom 3 bits are the Cache type for this level
  AND   R12, R12, #7          ; get those 3 bits alone
  CMP   R12, #2
  BLT   Skip                    ; no cache or only instruction cache at this level
  MCR   p15, 2, R10, c0, c0, 0  ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
  ISB                           ; ISB to sync the change to the CacheSizeID reg 
  MRC   p15, 1, R12, c0, c0, 0  ; reads current Cache Size ID register (CCSIDR)
  AND   R2, R12, #&7            ; extract the line length field
  ADD   R2, R2, #4              ; add 4 for the line length offset (log2 16 bytes)
  LDR   R4, =0x3FF
  ANDS  R4, R4, R12, LSR #3     ; R4 is the max number on the way size (right aligned)
  CLZ   R5, R4                  ; R5 is the bit position of the way size increment
  LDR   R7, =0x00007FFF
  ANDS  R7, R7, R12, LSR #13    ; R7 is the max number of the index size (right aligned)

Loop2   
  MOV   R9, R4                  ; R9 working copy of the max way size (right aligned)

Loop3   
  ORR   R0, R10, R9, LSL R5     ; factor in the way number and cache number into R11
  ORR   R0, R0, R7, LSL R2      ; factor in the index number

  BLX   R1

  SUBS  R9, R9, #1              ; decrement the way number
  BGE   Loop3
  SUBS  R7, R7, #1              ; decrement the index
  BGE   Loop2
Skip  
  ADD   R10, R10, #2            ; increment the cache number
  CMP   R3, R10
  BGT   Loop1
  
Finished
  LDMFD SP!, {r4-r12, lr}
  BX    LR

    END
Commit	Line	Data
2ef2b01e A	1	//------------------------------------------------------------------------------
	2	//
	3	// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
	4	//
	5	// All rights reserved. This program and the accompanying materials
	6	// are licensed and made available under the terms and conditions of the BSD License
	7	// which accompanies this distribution. The full text of the license may be found at
	8	// http://opensource.org/licenses/bsd-license.php
	9	//
	10	// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
	11	// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
	12	//
	13	//------------------------------------------------------------------------------
	14
	15	EXPORT ArmInvalidateInstructionCache
	16	EXPORT ArmInvalidateDataCacheEntryByMVA
	17	EXPORT ArmCleanDataCacheEntryByMVA
	18	EXPORT ArmCleanInvalidateDataCacheEntryByMVA
	19	EXPORT ArmInvalidateDataCacheEntryBySetWay
	20	EXPORT ArmCleanDataCacheEntryBySetWay
	21	EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
	22	EXPORT ArmDrainWriteBuffer
	23	EXPORT ArmEnableMmu
	24	EXPORT ArmDisableMmu
c2b5ca8b	25	EXPORT ArmMmuEnabled
2ef2b01e A	26	EXPORT ArmEnableDataCache
	27	EXPORT ArmDisableDataCache
	28	EXPORT ArmEnableInstructionCache
	29	EXPORT ArmDisableInstructionCache
	30	EXPORT ArmEnableBranchPrediction
	31	EXPORT ArmDisableBranchPrediction
37b91c49	32	EXPORT ArmV7AllDataCachesOperation
2ef2b01e A	33
	34	DC_ON EQU ( 0x1:SHL:2 )
	35	IC_ON EQU ( 0x1:SHL:12 )
2ef2b01e A	36
	37
	38	AREA ArmCacheLib, CODE, READONLY
	39	PRESERVE8
	40
	41
	42	ArmInvalidateDataCacheEntryByMVA
98bc0c8c	43	MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
1a27eb48	44	DSB
1a27eb48	45	ISB
2ef2b01e A	46	BX lr
	47
	48
	49	ArmCleanDataCacheEntryByMVA
	50	MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
1a27eb48	51	DSB
1a27eb48	52	ISB
2ef2b01e A	53	BX lr
	54
	55
	56	ArmCleanInvalidateDataCacheEntryByMVA
	57	MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
1a27eb48	58	DSB
1a27eb48	59	ISB
2ef2b01e A	60	BX lr
	61
	62
	63	ArmInvalidateDataCacheEntryBySetWay
	64	mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
1a27eb48	65	DSB
1a27eb48	66	ISB
2ef2b01e A	67	bx lr
	68
	69
	70	ArmCleanInvalidateDataCacheEntryBySetWay
	71	mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
1a27eb48	72	DSB
1a27eb48	73	ISB
2ef2b01e A	74	bx lr
	75
	76
	77	ArmCleanDataCacheEntryBySetWay
	78	mcr p15, 0, r0, c7, c10, 2 ; Clean this line
1a27eb48	79	DSB
1a27eb48	80	ISB
2ef2b01e A	81	bx lr
	82
	83
	84	ArmDrainWriteBuffer
	85	mcr p15, 0, r0, c7, c10, 4 ; Drain write buffer for sync
1a27eb48	86	DSB
1a27eb48	87	ISB
2ef2b01e A	88	bx lr
	89
	90
	91	ArmInvalidateInstructionCache
	92	MOV R0,#0
	93	MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
	94	MOV R0,#0
	95	MCR p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
1a27eb48	96	DSB
1a27eb48	97	ISB
2ef2b01e A	98	BX LR
	99
	100	ArmEnableMmu
	101	mrc p15,0,R0,c1,c0,0
	102	orr R0,R0,#1
	103	mcr p15,0,R0,c1,c0,0
1a27eb48	104	DSB
1a27eb48	105	ISB
2ef2b01e A	106	bx LR
2ef2b01e A	107
c2b5ca8b A	108	ArmMmuEnabled
	109	mrc p15,0,R0,c1,c0,0
	110	and R0,R0,#1
1a27eb48	111	ISB
c2b5ca8b A	112	bx LR
c2b5ca8b A	113
2ef2b01e A	114	ArmDisableMmu
	115	mov R0,#0
	116	mcr p15,0,R0,c13,c0,0 ;FCSE PID register must be cleared before disabling MMU
	117	mrc p15,0,R0,c1,c0,0
	118	bic R0,R0,#1
	119	mcr p15,0,R0,c1,c0,0 ;Disable MMU
1a27eb48	120	DSB
1a27eb48	121	ISB
2ef2b01e A	122	bx LR
	123
	124	ArmEnableDataCache
	125	LDR R1,=DC_ON
	126	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
	127	ORR R0,R0,R1 ;Set C bit
	128	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
1a27eb48	129	DSB
1a27eb48	130	ISB
2ef2b01e A	131	BX LR
	132
	133	ArmDisableDataCache
	134	LDR R1,=DC_ON
	135	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
	136	BIC R0,R0,R1 ;Clear C bit
	137	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
1a27eb48	138	ISB
2ef2b01e A	139	BX LR
	140
	141	ArmEnableInstructionCache
	142	LDR R1,=IC_ON
	143	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
	144	ORR R0,R0,R1 ;Set I bit
	145	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
1a27eb48	146	ISB
2ef2b01e A	147	BX LR
	148
	149	ArmDisableInstructionCache
	150	LDR R1,=IC_ON
	151	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
	152	BIC R0,R0,R1 ;Clear I bit.
	153	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
1a27eb48	154	ISB
2ef2b01e A	155	BX LR
	156
	157	ArmEnableBranchPrediction
	158	mrc p15, 0, r0, c1, c0, 0
	159	orr r0, r0, #0x00000800
	160	mcr p15, 0, r0, c1, c0, 0
1a27eb48	161	ISB
2ef2b01e A	162	bx LR
	163
	164	ArmDisableBranchPrediction
	165	mrc p15, 0, r0, c1, c0, 0
	166	bic r0, r0, #0x00000800
	167	mcr p15, 0, r0, c1, c0, 0
1a27eb48	168	ISB
2ef2b01e A	169	bx LR
2ef2b01e A	170
98bc0c8c	171
	172	ArmV7AllDataCachesOperation
	173	STMFD SP!,{r4-r12, LR}
	174	MOV R1, R0 ; Save Function call in R1
	175	MRC p15, 1, R6, c0, c0, 1 ; Read CLIDR
	176	ANDS R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)
	177	MOV R3, R3, LSR #23 ; Cache level value (naturally aligned)
	178	BEQ Finished
	179	MOV R10, #0
	180
	181	Loop1
	182	ADD R2, R10, R10, LSR #1 ; Work out 3xcachelevel
	183	MOV R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
	184	AND R12, R12, #7 ; get those 3 bits alone
	185	CMP R12, #2
	186	BLT Skip ; no cache or only instruction cache at this level
	187	MCR p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
	188	ISB ; ISB to sync the change to the CacheSizeID reg
	189	MRC p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
	190	AND R2, R12, #&7 ; extract the line length field
	191	ADD R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)
	192	LDR R4, =0x3FF
	193	ANDS R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
	194	CLZ R5, R4 ; R5 is the bit position of the way size increment
	195	LDR R7, =0x00007FFF
	196	ANDS R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)
	197
	198	Loop2
	199	MOV R9, R4 ; R9 working copy of the max way size (right aligned)
	200
	201	Loop3
	202	ORR R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11
	203	ORR R0, R0, R7, LSL R2 ; factor in the index number
	204
	205	BLX R1
	206
	207	SUBS R9, R9, #1 ; decrement the way number
	208	BGE Loop3
	209	SUBS R7, R7, #1 ; decrement the index
	210	BGE Loop2
	211	Skip
	212	ADD R10, R10, #2 ; increment the cache number
	213	CMP R3, R10
	214	BGT Loop1
	215
	216	Finished
	217	LDMFD SP!, {r4-r12, lr}
	218	BX LR
	219
2ef2b01e	220	END