3 # Copyright (c) 2011-2015, ARM Limited. All rights reserved.
4 # Copyright (c) 2015, Intel Corporation. All rights reserved.
6 # This program and the accompanying materials
7 # are licensed and made available under the terms and conditions of the BSD License
8 # which accompanies this distribution. The full text of the license may be found at
9 # http://opensource.org/licenses/bsd-license.php
11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 DEC_SPECIFICATION = 0x00010005
18 PACKAGE_NAME = ArmPlatformPkg
19 PACKAGE_GUID = 3308e0a0-1d94-11e0-915c-0002a5d5c51b
22 ################################################################################
24 # Include Section - list of Include Paths that are provided by this package.
25 # Comments are used for Keywords and Module Types.
27 # Supported Module Types:
28 # BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
30 ################################################################################
32 Include # Root include for the package
35 gArmPlatformTokenSpaceGuid = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }
37 # Following Guid must match FILE_GUID in MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
39 gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } }
41 ## Include/Guid/ArmGlobalVariableHob.h
42 gArmGlobalVariableGuid = { 0xc3253c90, 0xa24f, 0x4599, { 0xa6, 0x64, 0x1f, 0x88, 0x13, 0x77, 0x8f, 0xc9} }
44 gArmBootMonFsFileInfoGuid = { 0x41e26b9c, 0xada6, 0x45b3, { 0x80, 0x8e, 0x23, 0x57, 0xa3, 0x5b, 0x60, 0xd6 } }
47 ## Include/Ppi/ArmGlobalVariable.h
48 gArmGlobalVariablePpiGuid = { 0xab1c1816, 0xd542, 0x4e6f, {0x9b, 0x1e, 0x8e, 0xcd, 0x92, 0x53, 0xe2, 0xe7} }
50 [PcdsFeatureFlag.common]
51 # Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0.
52 gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012
54 gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE|BOOLEAN|0x00000001
55 gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|FALSE|BOOLEAN|0x00000002
56 gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004
58 gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked|FALSE|BOOLEAN|0x0000003C
60 # Disable the GOP controller on ExitBootServices(). By default the value is FALSE,
61 # we assume the OS will handle the FrameBuffer from the UEFI GOP information.
62 gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D
64 # Enable Legacy Linux support in the BDS
65 gArmPlatformTokenSpaceGuid.PcdBdsLinuxSupport|TRUE|BOOLEAN|0x0000002E
67 [PcdsFixedAtBuild.common]
68 gArmPlatformTokenSpaceGuid.PcdCoreCount|1|UINT32|0x00000039
69 gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038
71 # Stack for CPU Cores in Secure Mode
72 gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT32|0x00000005
73 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000|UINT32|0x00000036
74 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006
76 # Stack for CPU Cores in Non Secure Mode
77 gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT64|0x00000009
78 gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037
79 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A
81 # Size of the region used by UEFI in permanent memory (Reserved 128MB by default)
82 gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015
84 # Size to reserve in the primary core stack for PEI Global Variables
85 # = sizeof(UINTN) /* PcdPeiServicePtr or HobListPtr */
86 gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize|0x4|UINT32|0x00000016
87 # PeiServicePtr and HobListPtr shares the same location in the PEI Global Variable list
88 # PeiServicePtr is only valid with PEI Core and HobListPtr only when the PEI Core is skipped.
89 gArmPlatformTokenSpaceGuid.PcdPeiServicePtrGlobalOffset|0x0|UINT32|0x00000017
91 ## gArmPlatformTokenSpaceGuid.PcdHobListPtrGlobalOffset|0x0|UINT32|0x00000018
93 # Size to reserve in the primary core stack for SEC Global Variables
94 gArmPlatformTokenSpaceGuid.PcdSecGlobalVariableSize|0x0|UINT32|0x00000031
96 # Boot Monitor FileSystem
97 gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L""|VOID*|0x0000003A
104 gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|1|UINT32|0x0000001D
105 gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|0|UINT32|0x0000001E
106 gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0|UINT32|0x0000002A
107 gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0|UINT32|0x0000002B
108 gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0|UINT32|0x0000002C
111 gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0|UINT32|0x00000023
112 gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021
115 gArmPlatformTokenSpaceGuid.PL011UartClkInHz|24000000|UINT32|0x0000001F
116 gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020
117 gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D
120 gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025
123 gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026
124 gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027
127 gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028
128 gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029
133 gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Platform"|VOID*|0x00000019
134 gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Default Boot Device"|VOID*|0x0000000C
135 gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L""|VOID*|0x0000000D
136 gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|L""|VOID*|0x000000F
138 gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B
139 gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C
141 [PcdsFixedAtBuild.common,PcdsDynamic.common]
142 ## PL031 RealTimeClock
143 gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024
144 gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022
147 # Inclusive range of allowed PCI buses.
149 gArmPlatformTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x0000003E
150 gArmPlatformTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000003F
153 # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.
154 # Note that "IO" is just another MMIO range that simulates IO space; there
155 # are no special instructions to access it.
157 # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are
158 # specific to their containing address spaces. In order to get the physical
159 # address for the CPU, for a given access, the respective translation value
162 # The translations always have to be initialized like this, using UINT64:
164 # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space
165 # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space
166 # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space
168 # PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;
169 # PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;
170 # PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;
172 # because (a) the target address space (ie. the cpu-physical space) is
173 # 64-bit, and (b) the translation values are meant as offsets for *modular*
176 # Accordingly, the translation itself needs to be implemented as:
178 # UINT64 UntranslatedIoAddress; // input parameter
179 # UINT32 UntranslatedMmio32Address; // input parameter
180 # UINT64 UntranslatedMmio64Address; // input parameter
182 # UINT64 TranslatedIoAddress; // output parameter
183 # UINT64 TranslatedMmio32Address; // output parameter
184 # UINT64 TranslatedMmio64Address; // output parameter
186 # TranslatedIoAddress = UntranslatedIoAddress +
187 # PcdPciIoTranslation;
188 # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +
189 # PcdPciMmio32Translation;
190 # TranslatedMmio64Address = UntranslatedMmio64Address +
191 # PcdPciMmio64Translation;
193 # The modular arithmetic performed in UINT64 ensures that the translation
194 # works correctly regardless of the relation between IoCpuBase and
195 # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and
198 gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000040
199 gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000041
200 gArmPlatformTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000042
201 gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000043
202 gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000044
203 gArmPlatformTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000045
204 gArmPlatformTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000046
205 gArmPlatformTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000047
206 gArmPlatformTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000048
208 [PcdsFixedAtBuild.ARM]
209 # Stack for CPU Cores in Secure Monitor Mode
210 gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007
211 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008
213 [PcdsFixedAtBuild.AARCH64]
214 # The Secure World is only running in EL3. Only one set of stacks is needed for AArch64.
215 # The Secure stacks are described by PcdCPUCoresSecStackBase, PcdCPUCoreSecPrimaryStackSize
216 # and PcdCPUCoreSecSecondaryStackSize
217 gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007
218 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x0|UINT32|0x00000008