ArmPlatformPkg/ArmPlatformPkg.dec

   1 #/** @file
   2 #
   3 #  Copyright (c) 2011-2021, ARM Limited. All rights reserved.
   4 #  Copyright (c) 2015, Intel Corporation. All rights reserved.
   5 #
   6 #  SPDX-License-Identifier: BSD-2-Clause-Patent
   7 #
   8 #**/
   9
  10 [Defines]
  11   DEC_SPECIFICATION              = 0x00010005
  12   PACKAGE_NAME                   = ArmPlatformPkg
  13   PACKAGE_GUID                   = 3308e0a0-1d94-11e0-915c-0002a5d5c51b
  14   PACKAGE_VERSION                = 0.1
  15
  16 ################################################################################
  17 #
  18 # Include Section - list of Include Paths that are provided by this package.
  19 #                   Comments are used for Keywords and Module Types.
  20 #
  21 # Supported Module Types:
  22 #  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
  23 #
  24 ################################################################################
  25 [Includes.common]
  26   Include                        # Root include for the package
  27
  28 [LibraryClasses]
  29   ##  @libraryclass  Provides an interface to query platform information.
  30   #
  31   ArmPlatformLib|Include/Library/ArmPlatformLib.h
  32
  33   ##  @libraryclass  Provides an interface to initialize/shutdown a LCD screen.
  34   #
  35   LcdHwLib|Include/Library/LcdHwLib.h
  36
  37   ##  @libraryclass  Provides an interface to configure a LCD screen.
  38   #
  39   LcdPlatformLib|Include/Library/LcdPlatformLib.h
  40
  41   ##  @libraryclass  Provides an interface to the clock of a PL011 device.
  42   #
  43   PL011UartClockLib|Include/Library/PL011UartClockLib.h
  44
  45   ##  @libraryclass  Provides an interface to a PL011 uart.
  46   #
  47   PL011UartLib|Include/Library/PL011UartLib.h
  48
  49 [Guids.common]
  50   gArmPlatformTokenSpaceGuid   = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }
  51
  52 [PcdsFeatureFlag.common]
  53   gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004
  54
  55   # Disable the GOP controller on ExitBootServices(). By default the value is FALSE,
  56   # we assume the OS will handle the FrameBuffer from the UEFI GOP information.
  57   gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D
  58
  59 [PcdsFixedAtBuild.common]
  60   gArmPlatformTokenSpaceGuid.PcdCoreCount|1|UINT32|0x00000039
  61   gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038
  62
  63   # Stack for CPU Cores in Non Secure Mode
  64   gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT64|0x00000009
  65   gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037
  66   gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A
  67
  68   # Size of the region used by UEFI in permanent memory (Reserved 128MB by default)
  69   gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015
  70
  71   #
  72   # ARM Primecells
  73   #
  74
  75   ## SP805 Watchdog
  76   gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0|UINT32|0x00000023
  77   gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021
  78   gArmPlatformTokenSpaceGuid.PcdSP805WatchdogInterrupt|0|UINT32|0x0000002E
  79
  80   ## PL011 UART
  81   gArmPlatformTokenSpaceGuid.PL011UartClkInHz|24000000|UINT32|0x0000001F
  82   gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020
  83   gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D
  84   gArmPlatformTokenSpaceGuid.PL011UartInterrupt|0x00000000|UINT32|0x0000002F
  85   gArmPlatformTokenSpaceGuid.PL011UartRegOffsetVariant|0|UINT8|0x0000003E
  86
  87   ## PL011 Serial Debug UART
  88   gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x00000000|UINT64|0x00000030
  89   gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|0x00000000|UINT64|0x00000031
  90   gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|0x00000000|UINT32|0x00000032
  91   gArmPlatformTokenSpaceGuid.PcdSerialDbgInterrupt|0x00000000|UINT32|0x00000041
  92
  93   ## PL061 GPIO
  94   gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025
  95
  96   ## PL111 Lcd & HdLcd
  97   gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026
  98   gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027
  99
 100   ## Default size for display modes upto 1920x1080 (1920 * 1080 * 4 Bytes Per Pixel)
 101   gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferSize|0x7E9000|UINT32|0x00000043
 102   ## If set, framebuffer memory will be reserved and mapped in the system RAM
 103   gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferBase|0x0|UINT64|0x00000044
 104
 105   ## ARM Mali Display Processor DP500/DP550/DP650
 106   gArmPlatformTokenSpaceGuid.PcdArmMaliDpBase|0x0|UINT64|0x00000050
 107   gArmPlatformTokenSpaceGuid.PcdArmMaliDpMemoryRegionLength|0x0|UINT32|0x00000051
 108
 109   # Graphics Output Pixel format
 110   # 0 : PixelRedGreenBlueReserved8BitPerColor
 111   # 1 : PixelBlueGreenRedReserved8BitPerColor
 112   # 2 : PixelBitMask
 113   # Default is set to UEFI console font format PixelBlueGreenRedReserved8BitPerColor
 114   gArmPlatformTokenSpaceGuid.PcdGopPixelFormat|0x00000001|UINT32|0x00000040
 115
 116   ## If set, this will swap settings for HDLCD RED_SELECT and BLUE_SELECT registers
 117   gArmPlatformTokenSpaceGuid.PcdArmHdLcdSwapBlueRedSelect|FALSE|BOOLEAN|0x00000045
 118
 119 [PcdsFixedAtBuild.common,PcdsDynamic.common]
 120   ## PL031 RealTimeClock
 121   gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024
 122   gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022
 123
 124   gArmPlatformTokenSpaceGuid.PcdWatchdogCount|0x0|UINT32|0x00000033