ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #include <PiPei.h>
  16
  17 #include <Library/ArmLib.h>
  18 #include <Library/ArmGicLib.h>
  19 #include <Library/ArmPlatformLib.h>
  20 #include <Library/ArmPlatformSecLib.h>
  21 #include <Library/DebugLib.h>
  22 #include <Library/PcdLib.h>
  23 #include <Library/PrintLib.h>
  24 #include <Library/SerialPortLib.h>
  25
  26 // When the firmware is built as not Standalone, the secondary cores need to wait the firmware
  27 // entirely written into DRAM. It is the firmware from DRAM which will wake up the secondary cores.
  28 VOID
  29 NonSecureWaitForFirmware (
  30   VOID
  31   )
  32 {
  33   VOID (*secondary_start)(VOID);
  34   UINTN Interrupt;
  35
  36   // The secondary cores will execute the firmware once wake from WFI.
  37   secondary_start = (VOID (*)())PcdGet32(PcdFvBaseAddress);
  38
  39   ArmCallWFI();
  40
  41   // Acknowledge the interrupt and send End of Interrupt signal.
  42   Interrupt = ArmGicAcknowledgeInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase));
  43   // Check if it is a valid interrupt ID
  44   if ((Interrupt & ARM_GIC_ICCIAR_ACKINTID) < ArmGicGetMaxNumInterrupts (PcdGet32 (PcdGicDistributorBase))) {
  45     // Got a valid SGI number hence signal End of Interrupt
  46     ArmGicEndOfInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), Interrupt);
  47   }
  48
  49   // Jump to secondary core entry point.
  50   secondary_start ();
  51
  52   // PEI Core should always load and never return
  53   ASSERT (FALSE);
  54 }
  55
  56 /**
  57   Call before jumping to Normal World
  58
  59   This function allows the firmware platform to do extra actions before
  60   jumping to the Normal World
  61
  62 **/
  63 VOID
  64 ArmPlatformSecExtraAction (
  65   IN  UINTN         MpId,
  66   OUT UINTN*        JumpAddress
  67   )
  68 {
  69   CHAR8           Buffer[100];
  70   UINTN           CharCount;
  71
  72   if (FeaturePcdGet (PcdStandalone) == FALSE) {
  73
  74     //
  75     // Warning: This code assumes the DRAM has already been initialized by ArmPlatformSecLib
  76     //
  77
  78     if (ArmPlatformIsPrimaryCore (MpId)) {
  79       UINTN*   StartAddress = (UINTN*)PcdGet32(PcdFvBaseAddress);
  80
  81       // Patch the DRAM to make an infinite loop at the start address
  82       *StartAddress = 0xEAFFFFFE; // opcode for while(1)
  83
  84       CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Waiting for firmware at 0x%08X ...\n\r",StartAddress);
  85       SerialPortWrite ((UINT8 *) Buffer, CharCount);
  86
  87       *JumpAddress = PcdGet32(PcdFvBaseAddress);
  88     } else {
  89       // When the primary core is stopped by the hardware debugger to copy the firmware
  90       // into DRAM. The secondary cores are still running. As soon as the first bytes of
  91       // the firmware are written into DRAM, the secondary cores will start to execute the
  92       // code even if the firmware is not entirely written into the memory.
  93       // That's why the secondary cores need to be parked in WFI and wake up once the
  94       // firmware is ready.
  95
  96       *JumpAddress = (UINTN)NonSecureWaitForFirmware;
  97     }
  98   } else if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) {
  99
 100     //
 101     // Warning: This code assumes the DRAM has already been initialized by ArmPlatformSecLib
 102     //
 103
 104     if (ArmPlatformIsPrimaryCore (MpId)) {
 105       // Signal the secondary cores they can jump to PEI phase
 106       ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));
 107
 108       // To enter into Non Secure state, we need to make a return from exception
 109       *JumpAddress = PcdGet32(PcdFvBaseAddress);
 110     } else {
 111       // We wait for the primary core to finish to initialize the System Memory. Otherwise the secondary
 112       // cores would make crash the system by setting their stacks in DRAM before the primary core has not
 113       // finished to initialize the system memory.
 114       *JumpAddress = (UINTN)NonSecureWaitForFirmware;
 115     }
 116   } else {
 117     *JumpAddress = PcdGet32(PcdFvBaseAddress);
 118   }
 119 }