3 * Copyright (c) 2011-2012, ARM Limited. All rights reserved.
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include <Library/ArmGicLib.h>
17 #include <Ppi/ArmMpCoreInfo.h>
19 #include "PrePeiCore.h"
22 * This is the main function for secondary cores. They loop around until a non Null value is written to
23 * SYS_FLAGS register.The SYS_FLAGS register is platform specific.
24 * Note:The secondary cores, while executing secondary_main, assumes that:
25 * : SGI 0 is configured as Non-secure interrupt
26 * : Priority Mask is configured to allow SGI 0
27 * : Interrupt Distributor and CPU interfaces are enabled
39 EFI_PEI_PPI_DESCRIPTOR
*PpiList
;
40 ARM_MP_CORE_INFO_PPI
*ArmMpCoreInfoPpi
;
43 ARM_CORE_INFO
*ArmCoreInfoTable
;
46 VOID (*SecondaryStart
)(VOID
);
47 UINTN SecondaryEntryAddr
;
48 UINTN AcknowledgedCoreId
;
50 ClusterId
= GET_CLUSTER_ID(MpId
);
51 CoreId
= GET_CORE_ID(MpId
);
53 // Get the gArmMpCoreInfoPpiGuid
55 ArmPlatformGetPlatformPpiList (&PpiListSize
, &PpiList
);
56 PpiListCount
= PpiListSize
/ sizeof(EFI_PEI_PPI_DESCRIPTOR
);
57 for (Index
= 0; Index
< PpiListCount
; Index
++, PpiList
++) {
58 if (CompareGuid (PpiList
->Guid
, &gArmMpCoreInfoPpiGuid
) == TRUE
) {
63 // On MP Core Platform we must implement the ARM MP Core Info PPI
64 ASSERT (Index
!= PpiListCount
);
66 ArmMpCoreInfoPpi
= PpiList
->Ppi
;
68 Status
= ArmMpCoreInfoPpi
->GetMpCoreInfo (&ArmCoreCount
, &ArmCoreInfoTable
);
69 ASSERT_EFI_ERROR (Status
);
71 // Find the core in the ArmCoreTable
72 for (Index
= 0; Index
< ArmCoreCount
; Index
++) {
73 if ((ArmCoreInfoTable
[Index
].ClusterId
== ClusterId
) && (ArmCoreInfoTable
[Index
].CoreId
== CoreId
)) {
78 // The ARM Core Info Table must define every core
79 ASSERT (Index
!= ArmCoreCount
);
81 // Clear Secondary cores MailBox
82 MmioWrite32 (ArmCoreInfoTable
[Index
].MailboxClearAddress
, ArmCoreInfoTable
[Index
].MailboxClearValue
);
88 SecondaryEntryAddr
= MmioRead32 (ArmCoreInfoTable
[Index
].MailboxGetAddress
);
90 // Acknowledge the interrupt and send End of Interrupt signal.
91 ArmGicAcknowledgeInterrupt (PcdGet32(PcdGicDistributorBase
), PcdGet32(PcdGicInterruptInterfaceBase
), &AcknowledgedCoreId
, NULL
);
92 } while ((SecondaryEntryAddr
== 0) && (AcknowledgedCoreId
!= PcdGet32 (PcdGicPrimaryCoreId
)));
94 // Jump to secondary core entry point.
95 SecondaryStart
= (VOID (*)())SecondaryEntryAddr
;
98 // The secondaries shouldn't reach here
105 IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
108 EFI_SEC_PEI_HAND_OFF SecCoreData
;
110 EFI_PEI_PPI_DESCRIPTOR
*PpiList
;
111 UINTN TemporaryRamBase
;
112 UINTN TemporaryRamSize
;
114 // Check PcdGicPrimaryCoreId has been set in case the Primary Core is not the core 0 of Cluster 0
116 if ((PcdGet32(PcdArmPrimaryCore
) != 0) && (PcdGet32 (PcdGicPrimaryCoreId
) == 0)) {
117 DEBUG((EFI_D_WARN
,"Warning: the PCD PcdGicPrimaryCoreId does not seem to be set up for the configuration.\n"));
121 CreatePpiList (&PpiListSize
, &PpiList
);
123 // Enable the GIC Distributor
124 ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase
));
126 // If ArmVe has not been built as Standalone then we need to wake up the secondary cores
127 if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores
)) {
128 // Sending SGI to all the Secondary CPU interfaces
129 ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase
), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE
, 0x0E, PcdGet32 (PcdGicSgiIntId
));
132 // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at
133 // the base of the primary core stack
134 PpiListSize
= ALIGN_VALUE(PpiListSize
, 0x4);
135 TemporaryRamBase
= (UINTN
)PcdGet32 (PcdCPUCoresStackBase
) + PpiListSize
;
136 TemporaryRamSize
= (UINTN
)PcdGet32 (PcdCPUCorePrimaryStackSize
) - PpiListSize
;
138 // Make sure the size is 8-byte aligned. Once divided by 2, the size should be 4-byte aligned
139 // to ensure the stack pointer is 4-byte aligned.
140 TemporaryRamSize
= TemporaryRamSize
- (TemporaryRamSize
& (0x8-1));
143 // Bind this information into the SEC hand-off state
144 // Note: this must be in sync with the stuff in the asm file
145 // Note also: HOBs (pei temp ram) MUST be above stack
147 SecCoreData
.DataSize
= sizeof(EFI_SEC_PEI_HAND_OFF
);
148 SecCoreData
.BootFirmwareVolumeBase
= (VOID
*)(UINTN
)PcdGet32 (PcdFvBaseAddress
);
149 SecCoreData
.BootFirmwareVolumeSize
= PcdGet32 (PcdFvSize
);
150 SecCoreData
.TemporaryRamBase
= (VOID
*)TemporaryRamBase
; // We run on the primary core (and so we use the first stack)
151 SecCoreData
.TemporaryRamSize
= TemporaryRamSize
;
152 SecCoreData
.PeiTemporaryRamBase
= SecCoreData
.TemporaryRamBase
;
153 SecCoreData
.PeiTemporaryRamSize
= SecCoreData
.TemporaryRamSize
/ 2;
154 SecCoreData
.StackBase
= (VOID
*)ALIGN_VALUE((UINTN
)(SecCoreData
.TemporaryRamBase
) + SecCoreData
.PeiTemporaryRamSize
, 0x4);
155 SecCoreData
.StackSize
= (TemporaryRamBase
+ TemporaryRamSize
) - (UINTN
)SecCoreData
.StackBase
;
157 // Jump to PEI core entry point
158 (PeiCoreEntryPoint
)(&SecCoreData
, PpiList
);