3 * Copyright (c) 2011, ARM Limited. All rights reserved.
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include <Library/ArmGicLib.h>
16 #include <Library/ArmMPCoreMailBoxLib.h>
17 #include <Chipset/ArmV7.h>
19 #include "PrePeiCore.h"
21 extern EFI_PEI_PPI_DESCRIPTOR
*gSecPpiTable
;
24 * This is the main function for secondary cores. They loop around until a non Null value is written to
25 * SYS_FLAGS register.The SYS_FLAGS register is platform specific.
26 * Note:The secondary cores, while executing secondary_main, assumes that:
27 * : SGI 0 is configured as Non-secure interrupt
28 * : Priority Mask is configured to allow SGI 0
29 * : Interrupt Distributor and CPU interfaces are enabled
38 // Function pointer to Secondary Core entry point
39 VOID (*secondary_start
)(VOID
);
40 UINTN secondary_entry_addr
=0;
42 // Clear Secondary cores MailBox
43 ArmClearMPCoreMailbox();
45 while (secondary_entry_addr
= ArmGetMPCoreMailbox(), secondary_entry_addr
== 0) {
47 // Acknowledge the interrupt and send End of Interrupt signal.
48 ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase
), PRIMARY_CORE_ID
);
51 secondary_start
= (VOID (*)())secondary_entry_addr
;
53 // Jump to secondary core entry point.
56 // The secondaries shouldn't reach here
63 IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
66 EFI_SEC_PEI_HAND_OFF SecCoreData
;
68 // Enable the GIC Distributor
69 ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase
));
71 // If ArmVe has not been built as Standalone then we need to wake up the secondary cores
72 if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores
)) {
73 // Sending SGI to all the Secondary CPU interfaces
74 ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase
), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE
, 0x0E);
78 // Bind this information into the SEC hand-off state
79 // Note: this must be in sync with the stuff in the asm file
80 // Note also: HOBs (pei temp ram) MUST be above stack
82 SecCoreData
.DataSize
= sizeof(EFI_SEC_PEI_HAND_OFF
);
83 SecCoreData
.BootFirmwareVolumeBase
= (VOID
*)(UINTN
)PcdGet32 (PcdNormalFvBaseAddress
);
84 SecCoreData
.BootFirmwareVolumeSize
= PcdGet32 (PcdNormalFvSize
);
85 SecCoreData
.TemporaryRamBase
= (VOID
*)(UINTN
)PcdGet32 (PcdCPUCoresNonSecStackBase
); // We consider we run on the primary core (and so we use the first stack)
86 SecCoreData
.TemporaryRamSize
= (UINTN
)(UINTN
)PcdGet32 (PcdCPUCoresNonSecStackSize
);
87 SecCoreData
.PeiTemporaryRamBase
= (VOID
*)((UINTN
)(SecCoreData
.TemporaryRamBase
) + (SecCoreData
.TemporaryRamSize
/ 2));
88 SecCoreData
.PeiTemporaryRamSize
= SecCoreData
.TemporaryRamSize
/ 2;
89 SecCoreData
.StackBase
= SecCoreData
.TemporaryRamBase
;
90 SecCoreData
.StackSize
= SecCoreData
.TemporaryRamSize
- SecCoreData
.PeiTemporaryRamSize
;
92 // Jump to PEI core entry point
93 (PeiCoreEntryPoint
)(&SecCoreData
, (VOID
*)&gSecPpiTable
);