3 * Copyright (c) 2011, ARM Limited. All rights reserved.
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 #include <Library/ArmGicLib.h>
19 #include <Ppi/ArmMpCoreInfo.h>
29 EFI_PEI_PPI_DESCRIPTOR
*PpiList
;
33 ArmPlatformGetPlatformPpiList (&PpiListSize
, &PpiList
);
34 PpiListCount
= PpiListSize
/ sizeof(EFI_PEI_PPI_DESCRIPTOR
);
35 for (Index
= 0; Index
< PpiListCount
; Index
++, PpiList
++) {
36 if (CompareGuid (PpiList
->Guid
, PpiGuid
) == TRUE
) {
47 IN UINTN UefiMemoryBase
,
49 IN UINTN GlobalVariableBase
,
50 IN UINT64 StartTimeStamp
53 // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)
56 ARM_MP_CORE_INFO_PPI
*ArmMpCoreInfoPpi
;
58 Status
= GetPlatformPpi (&gArmMpCoreInfoPpiGuid
, (VOID
**)&ArmMpCoreInfoPpi
);
59 ASSERT_EFI_ERROR (Status
);
62 // Enable the GIC Distributor
63 ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase
));
65 // In some cases, the secondary cores are waiting for an SGI from the next stage boot loader toresume their initialization
66 if (!FixedPcdGet32(PcdSendSgiToBringUpSecondaryCores
)) {
67 // Sending SGI to all the Secondary CPU interfaces
68 ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase
), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE
, 0x0E);
71 PrePiMain (UefiMemoryBase
, StacksBase
, GlobalVariableBase
, StartTimeStamp
);
73 // We must never return
83 ARM_MP_CORE_INFO_PPI
*ArmMpCoreInfoPpi
;
86 ARM_CORE_INFO
*ArmCoreInfoTable
;
89 VOID (*SecondaryStart
)(VOID
);
90 UINTN SecondaryEntryAddr
;
92 ClusterId
= GET_CLUSTER_ID(MpId
);
93 CoreId
= GET_CORE_ID(MpId
);
95 // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)
96 Status
= GetPlatformPpi (&gArmMpCoreInfoPpiGuid
, (VOID
**)&ArmMpCoreInfoPpi
);
97 ASSERT_EFI_ERROR (Status
);
100 Status
= ArmMpCoreInfoPpi
->GetMpCoreInfo (&ArmCoreCount
, &ArmCoreInfoTable
);
101 ASSERT_EFI_ERROR (Status
);
103 // Find the core in the ArmCoreTable
104 for (Index
= 0; Index
< ArmCoreCount
; Index
++) {
105 if ((ArmCoreInfoTable
[Index
].ClusterId
== ClusterId
) && (ArmCoreInfoTable
[Index
].CoreId
== CoreId
)) {
110 // The ARM Core Info Table must define every core
111 ASSERT (Index
!= ArmCoreCount
);
113 // Clear Secondary cores MailBox
114 MmioWrite32 (ArmCoreInfoTable
[Index
].MailboxClearAddress
, ArmCoreInfoTable
[Index
].MailboxClearValue
);
116 SecondaryEntryAddr
= 0;
117 while (SecondaryEntryAddr
= MmioRead32 (ArmCoreInfoTable
[Index
].MailboxGetAddress
), SecondaryEntryAddr
== 0) {
119 // Acknowledge the interrupt and send End of Interrupt signal.
120 ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase
), PRIMARY_CORE_ID
);
123 // Jump to secondary core entry point.
124 SecondaryStart
= (VOID (*)())SecondaryEntryAddr
;
127 // The secondaries shouldn't reach here