ArmPlatformPkg/Sec/AArch64/Helper.S

   1 #========================================================================================
   2 #  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
   3 #
   4 #  This program and the accompanying materials
   5 #  are licensed and made available under the terms and conditions of the BSD License
   6 #  which accompanies this distribution.  The full text of the license may be found at
   7 #  http:#opensource.org/licenses/bsd-license.php
   8 #
   9 #  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 #
  12 #=======================================================================================
  13
  14 #include <AsmMacroIoLibV8.h>
  15 #include <Chipset/AArch64.h>
  16
  17 #start of the code section
  18 .text
  19 .align 3
  20
  21 ASM_GLOBAL ASM_PFX(SetupExceptionLevel3)
  22 ASM_GLOBAL ASM_PFX(SwitchToNSExceptionLevel1)
  23 ASM_GLOBAL ASM_PFX(enter_monitor_mode)
  24 ASM_GLOBAL ASM_PFX(return_from_exception)
  25 ASM_GLOBAL ASM_PFX(copy_cpsr_into_spsr)
  26 ASM_GLOBAL ASM_PFX(set_non_secure_mode)
  27
  28 ASM_PFX(SetupExceptionLevel3):
  29    mrs    x0, scr_el3            // Read EL3 Secure Configuration Register
  30    orr    x0, x0, #1             // EL0 an EL1 cannot access secure memory
  31
  32    // Send all interrupts to their respective Exception levels for EL3
  33    bic    x0, x0, #(1 << 1)      // IRQ
  34    bic    x0, x0, #(1 << 2)      // FIQ
  35    bic    x0, x0, #(1 << 3)      // Serror and Abort
  36    orr    x0, x0, #(1 << 8)      // Enable HVC
  37    orr    x0, x0, #(1 << 10)     // Make next level down 64Bit. This is EL2 in the case of the Model.
  38                                  // We need a nice way to detect this.
  39    msr    scr_el3, x0            // Write back our settings
  40
  41    msr    cptr_el3, xzr          // Disable copro traps to EL3
  42
  43    // Check for the primary CPU to avoid a race on the distributor registers.
  44    mrs     x0, mpidr_el1
  45    tst     x0, #15
  46    b.ne    1f                              // secondary CPU
  47
  48    LoadConstantToReg (FixedPcdGet32(PcdGicInterruptInterfaceBase), x1)
  49    mov     w0, #3                          // EnableGrp0 | EnableGrp1
  50    str     w0, [x1]
  51
  52 1: LoadConstantToReg (FixedPcdGet32(PcdGicDistributorBase), x1)
  53    add     x1, x1, #0x80
  54    mov     w0, #~0                         // Grp1 interrupts
  55    str     w0, [x1], #4
  56    b.ne    2f                              // Only local interrupts for secondary CPUs
  57    str     w0, [x1], #4
  58    str     w0, [x1], #4
  59
  60 2: LoadConstantToReg (FixedPcdGet32(PcdGicInterruptInterfaceBase), x1)
  61    ldr     w0, [x1]
  62    mov     w0, #3                          // EnableGrp0 | EnableGrp1
  63    str     w0, [x1]
  64
  65    mov     w0, #1 << 7                     // allow NS access to GICC_PMR
  66    str     w0, [x1, #4]                    // GICC_PMR
  67
  68    ret
  69
  70 // Switch from EL3 to NS-EL1
  71 ASM_PFX(SwitchToNSExceptionLevel1):
  72    // Now setup our EL1. Controlled by EL2 config on Model
  73    mrs     x0, hcr_el2            // Read EL2 Hypervisor configuration Register
  74    orr     x0, x0, #(1 << 31)     // Set EL1 to be 64bit
  75
  76    // Send all interrupts to their respective Exception levels for EL2
  77    bic     x0, x0, #(1 << 3)      // Disable virtual FIQ
  78    bic     x0, x0, #(1 << 4)      // Disable virtual IRQ
  79    bic     x0, x0, #(1 << 5)      // Disable virtual SError and Abort
  80    msr     hcr_el2, x0            // Write back our settings
  81
  82    msr     cptr_el2, xzr          // Disable copro traps to EL2
  83
  84    msr     sctlr_el2, xzr
  85
  86    // Enable architected timer access
  87    mrs     x0, cnthctl_el2
  88    orr     x0, x0, #3             // Enable EL1 access to timers
  89    msr     cnthctl_el2, x0
  90
  91    mrs     x0, cntkctl_el1
  92    orr     x0, x0, #3             // EL0 access to counters
  93    msr     cntkctl_el1, x0
  94
  95    // Set ID regs
  96    mrs     x0, midr_el1
  97    mrs     x1, mpidr_el1
  98    msr     vpidr_el2, x0
  99    msr     vmpidr_el2, x1
 100
 101    ret
 102
 103
 104 // EL3 on AArch64 is Secure/monitor so this funtion is reduced vs ARMv7
 105 // we don't need a mode switch, just setup the Arguments and jump.
 106 // x0: Monitor World EntryPoint
 107 // x1: MpId
 108 // x2: SecBootMode
 109 // x3: Secure Monitor mode stack
 110 ASM_PFX(enter_monitor_mode):
 111    mov     x4, x0                 // Swap EntryPoint and MpId registers
 112    mov     x0, x1
 113    mov     x1, x2
 114    mov     x2, x3
 115    br      x4
 116
 117 // Put the address in correct ELR_ELx and do a eret.
 118 // We may need to do some config before we change to another Mode.
 119 ASM_PFX(return_from_exception):
 120    msr     elr_el3, x0
 121
 122    mrs     x7, spsr_el3
 123    ands    w7, w7, #0xC
 124    cmp     w7, #0xC       // EL3?
 125    b.eq    3f
 126    bl      ASM_PFX(SetupExceptionLevel3)
 127    cmp     w7, #0x8       // EL2?
 128    b.eq    2f
 129    cmp     w7, #0x4       // EL1?
 130    b.eq    1f
 131    b       dead           // We should never get here.
 132
 133 1: bl      ASM_PFX(SwitchToNSExceptionLevel1)
 134 2: // EL2: No more setup required.
 135 3: // EL3: Not sure why we would do this.
 136    eret
 137
 138 // For AArch64 we need to construct the spsr we want from individual bits and pieces.
 139 ASM_PFX(copy_cpsr_into_spsr):
 140    mrs     x0, CurrentEl  // Get the current exception level we  are running at.
 141    mrs     x1, SPSel      // Which Stack are we using
 142    orr     x0, x0, x1
 143    mrs     x1, daif       // Which interrupts are enabled
 144    orr     x0, x0, x1
 145    msr     spsr_el3, x0   // Write to spsr
 146    ret
 147
 148 // Get this from platform file.
 149 ASM_PFX(set_non_secure_mode):
 150    msr     spsr_el3, x0
 151    ret
 152
 153 dead:
 154    b       dead
 155
 156 ASM_FUNCTION_REMOVE_IF_UNREFERENCED