3 Copyright (c) 2005 - 2006, Intel Corporation. All rights reserved.<BR>
4 This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 The driver for the host to pci bridge (root bridge).
21 #ifndef _PCAT_PCI_ROOT_BRIDGE_H_
22 #define _PCAT_PCI_ROOT_BRIDGE_H_
25 #include <Protocol/PciRootBridgeIo.h>
26 #include <Protocol/DeviceIo.h>
27 #include <Protocol/CpuIo2.h>
29 #include <Library/UefiLib.h>
30 #include <Library/BaseLib.h>
31 #include <Library/MemoryAllocationLib.h>
32 #include <Library/UefiBootServicesTableLib.h>
33 #include <Library/DebugLib.h>
34 #include <Library/BaseMemoryLib.h>
35 #include <Library/DevicePathLib.h>
36 #include <Library/HobLib.h>
38 #include <Guid/PciOptionRomTable.h>
39 #include <Guid/HobList.h>
40 #include <Guid/PciExpressBaseAddress.h>
42 #include <IndustryStandard/Acpi.h>
43 #include <IndustryStandard/Pci.h>
45 #define PCI_MAX_SEGMENT 0
47 // Driver Instance Data Prototypes
49 #define PCAT_PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32('p', 'c', 'r', 'b')
55 EFI_DEVICE_PATH_PROTOCOL
*DevicePath
;
56 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io
;
57 EFI_CPU_IO2_PROTOCOL
*CpuIo
;
59 UINT32 RootBridgeNumber
;
61 UINT32 SubordinateBus
;
63 UINT64 MemBase
; // Offsets host to bus memory addr.
64 UINT64 MemLimit
; // Max allowable memory access
66 UINT64 IoBase
; // Offsets host to bus io addr.
67 UINT64 IoLimit
; // Max allowable io access
72 UINT64 PhysicalMemoryBase
;
73 UINT64 PhysicalIoBase
;
88 UINT64 PciExpressBaseAddress
;
90 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Configuration
;
93 } PCAT_PCI_ROOT_BRIDGE_INSTANCE
;
96 // Driver Instance Data Macros
98 #define DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) \
99 CR(a, PCAT_PCI_ROOT_BRIDGE_INSTANCE, Io, PCAT_PCI_ROOT_BRIDGE_SIGNATURE)
102 // Private data types
107 UINT16
volatile *ui16
;
108 UINT32
volatile *ui32
;
109 UINT64
volatile *ui64
;
114 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation
;
117 EFI_PHYSICAL_ADDRESS HostAddress
;
118 EFI_PHYSICAL_ADDRESS MappedHostAddress
;
128 (*EFI_PCI_BUS_SCAN_CALLBACK
) (
129 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
143 UINT16
*CommandRegisterBuffer
;
144 UINT32 PpbMemoryWindow
;
145 } PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT
;
156 // Driver Protocol Constructor Prototypes
159 ConstructConfiguration(
160 IN OUT PCAT_PCI_ROOT_BRIDGE_INSTANCE
*PrivateData
164 PcatPciRootBridgeParseBars (
165 IN PCAT_PCI_ROOT_BRIDGE_INSTANCE
*PrivateData
,
173 ScanPciRootBridgeForRoms(
174 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
178 PcatRootBridgeDevicePathConstructor (
179 IN EFI_DEVICE_PATH_PROTOCOL
**Protocol
,
180 IN UINTN RootBridgeNumber
,
181 IN BOOLEAN IsPciExpress
185 PcatRootBridgeIoConstructor (
186 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*Protocol
,
187 IN UINTN SegmentNumber
191 PcatRootBridgeIoGetIoPortMapping (
192 OUT EFI_PHYSICAL_ADDRESS
*IoPortMapping
,
193 OUT EFI_PHYSICAL_ADDRESS
*MemoryPortMapping
197 PcatRootBridgeIoPciRW (
198 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
200 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
201 IN UINT64 UserAddress
,
203 IN OUT VOID
*UserBuffer
207 GetPciExpressBaseAddressForRootBridge (
208 IN UINTN HostBridgeNumber
,
209 IN UINTN RootBridgeNumber
214 PcatRootBridgeIoIoRead (
215 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
216 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
217 IN UINT64 UserAddress
,
219 IN OUT VOID
*UserBuffer
224 PcatRootBridgeIoIoWrite (
225 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
226 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
227 IN UINT64 UserAddress
,
229 IN OUT VOID
*UserBuffer
233 // Driver entry point prototype
237 InitializePcatPciRootBridge (
238 IN EFI_HANDLE ImageHandle
,
239 IN EFI_SYSTEM_TABLE
*SystemTable
242 extern EFI_CPU_IO2_PROTOCOL
*gCpuIo
;