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git.proxmox.com Git - mirror_edk2.git/blob - IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.h
2 PCI command register operations supporting functions declaration for PCI Bus module.
4 Copyright (c) 2006 - 2009, Intel Corporation
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #ifndef _EFI_PCI_COMMAND_H_
17 #define _EFI_PCI_COMMAND_H_
20 // The PCI Command register bits owned by PCI Bus driver.
22 // They should be cleared at the beginning. The other registers
23 // are owned by chipset, we should not touch them.
25 #define EFI_PCI_COMMAND_BITS_OWNED ( \
26 EFI_PCI_COMMAND_IO_SPACE | \
27 EFI_PCI_COMMAND_MEMORY_SPACE | \
28 EFI_PCI_COMMAND_BUS_MASTER | \
29 EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE | \
30 EFI_PCI_COMMAND_VGA_PALETTE_SNOOP | \
31 EFI_PCI_COMMAND_FAST_BACK_TO_BACK \
35 // The PCI Bridge Control register bits owned by PCI Bus driver.
37 // They should be cleared at the beginning. The other registers
38 // are owned by chipset, we should not touch them.
40 #define EFI_PCI_BRIDGE_CONTROL_BITS_OWNED ( \
41 EFI_PCI_BRIDGE_CONTROL_ISA | \
42 EFI_PCI_BRIDGE_CONTROL_VGA | \
43 EFI_PCI_BRIDGE_CONTROL_VGA_16 | \
44 EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK \
48 // The PCCard Bridge Control register bits owned by PCI Bus driver.
50 // They should be cleared at the beginning. The other registers
51 // are owned by chipset, we should not touch them.
53 #define EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED ( \
54 EFI_PCI_BRIDGE_CONTROL_ISA | \
55 EFI_PCI_BRIDGE_CONTROL_VGA | \
56 EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK \
60 #define EFI_GET_REGISTER 1
61 #define EFI_SET_REGISTER 2
62 #define EFI_ENABLE_REGISTER 3
63 #define EFI_DISABLE_REGISTER 4
66 Operate the PCI register via PciIo function interface.
68 @param PciIoDevice Pointer to instance of PCI_IO_DEVICE.
69 @param Command Operator command.
70 @param Offset The address within the PCI configuration space for the PCI controller.
71 @param Operation Type of Operation.
72 @param PtrCommand Return buffer holding old PCI command, if operation is not EFI_SET_REGISTER.
74 @return Status of PciIo operation.
79 IN PCI_IO_DEVICE
*PciIoDevice
,
83 OUT UINT16
*PtrCommand
87 Check the cpability supporting by given device.
89 @param PciIoDevice Pointer to instance of PCI_IO_DEVICE.
91 @retval TRUE Cpability supportted.
92 @retval FALSE Cpability not supportted.
96 PciCapabilitySupport (
97 IN PCI_IO_DEVICE
*PciIoDevice
101 Locate capability register block per capability ID.
103 @param PciIoDevice A pointer to the PCI_IO_DEVICE.
104 @param CapId The capability ID.
105 @param Offset A pointer to the offset returned.
106 @param NextRegBlock A pointer to the next block returned.
108 @retval EFI_SUCCESS Successfuly located capability register block.
109 @retval EFI_UNSUPPORTED Pci device does not support capability.
110 @retval EFI_NOT_FOUND Pci device support but can not find register block.
114 LocateCapabilityRegBlock (
115 IN PCI_IO_DEVICE
*PciIoDevice
,
117 IN OUT UINT8
*Offset
,
118 OUT UINT8
*NextRegBlock OPTIONAL
122 Macro that reads command register.
124 @param a[in] Pointer to instance of PCI_IO_DEVICE.
125 @param b[out] Pointer to the 16-bit value read from command register.
127 @return status of PciIo operation
130 #define PCI_READ_COMMAND_REGISTER(a,b) \
131 PciOperateRegister (a, 0, PCI_COMMAND_OFFSET, EFI_GET_REGISTER, b)
134 Macro that writes command register.
136 @param a[in] Pointer to instance of PCI_IO_DEVICE.
137 @param b[in] The 16-bit value written into command register.
139 @return status of PciIo operation
142 #define PCI_SET_COMMAND_REGISTER(a,b) \
143 PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_SET_REGISTER, NULL)
146 Macro that enables command register.
148 @param a[in] Pointer to instance of PCI_IO_DEVICE.
149 @param b[in] The enabled value written into command register.
151 @return status of PciIo operation
154 #define PCI_ENABLE_COMMAND_REGISTER(a,b) \
155 PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_ENABLE_REGISTER, NULL)
158 Macro that disalbes command register.
160 @param a[in] Pointer to instance of PCI_IO_DEVICE.
161 @param b[in] The disabled value written into command register.
163 @return status of PciIo operation
166 #define PCI_DISABLE_COMMAND_REGISTER(a,b) \
167 PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_DISABLE_REGISTER, NULL)
170 Macro that reads PCI bridge control register.
172 @param a[in] Pointer to instance of PCI_IO_DEVICE.
173 @param b[out] The 16-bit value read from control register.
175 @return status of PciIo operation
178 #define PCI_READ_BRIDGE_CONTROL_REGISTER(a,b) \
179 PciOperateRegister (a, 0, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_GET_REGISTER, b)
182 Macro that writes PCI bridge control register.
184 @param a[in] Pointer to instance of PCI_IO_DEVICE.
185 @param b[in] The 16-bit value written into control register.
187 @return status of PciIo operation
190 #define PCI_SET_BRIDGE_CONTROL_REGISTER(a,b) \
191 PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_SET_REGISTER, NULL)
194 Macro that enables PCI bridge control register.
196 @param a[in] Pointer to instance of PCI_IO_DEVICE.
197 @param b[in] The enabled value written into command register.
199 @return status of PciIo operation
202 #define PCI_ENABLE_BRIDGE_CONTROL_REGISTER(a,b) \
203 PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_ENABLE_REGISTER, NULL)
206 Macro that disalbes PCI bridge control register.
208 @param a[in] Pointer to instance of PCI_IO_DEVICE.
209 @param b[in] The disabled value written into command register.
211 @return status of PciIo operation
214 #define PCI_DISABLE_BRIDGE_CONTROL_REGISTER(a,b) \
215 PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_DISABLE_REGISTER, NULL)