2 Header file for FSP-M Arch Config PPI for Dispatch mode
4 Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
10 #ifndef _FSPM_ARCH_CONFIG_PPI_H_
11 #define _FSPM_ARCH_CONFIG_PPI_H_
13 #define FSPM_ARCH_CONFIG_PPI_REVISION 0x1
16 /// Global ID for the FSPM_ARCH_CONFIG_PPI.
18 #define FSPM_ARCH_CONFIG_GUID \
20 0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb } \
24 /// This PPI provides FSP-M Arch Config PPI.
28 /// Revision of the structure
33 /// Pointer to the non-volatile storage (NVS) data buffer.
34 /// If it is NULL it indicates the NVS data is not available.
38 /// Size of memory to be reserved by FSP below "top
39 /// of low usable memory" for bootloader usage.
41 UINT32 BootLoaderTolumSize
;
43 } FSPM_ARCH_CONFIG_PPI
;
45 extern EFI_GUID gFspmArchConfigPpiGuid
;
47 #endif // _FSPM_ARCH_CONFIG_PPI_H_