1 ;------------------------------------------------------------------------------
3 ; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
4 ; This program and the accompanying materials
5 ; are licensed and made available under the terms and conditions of the BSD License
6 ; which accompanies this distribution. The full text of the license may be found at
7 ; http://opensource.org/licenses/bsd-license.php.
9 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 ; This is the code that goes from real-mode to protected mode.
19 ; It consumes the reset vector, calls TempRamInit API from FSP binary.
21 ;------------------------------------------------------------------------------
27 extern ASM_PFX(CallPeiCoreEntryPoint)
28 extern ASM_PFX(FsptUpdDataPtr)
31 extern ASM_PFX(PcdGet32 (PcdFsptBaseAddress))
33 ;----------------------------------------------------------------------------
35 ; Procedure: _ModuleEntryPoint
41 ; Destroys: Assume all registers
45 ; Transition to non-paged flat-model protected mode from a
46 ; hard-coded GDT that provides exactly two descriptors.
47 ; This is a bare bones transition to protected mode only
48 ; used for a while in PEI and possibly DXE.
50 ; After enabling protected mode, a far jump is executed to
51 ; transfer to PEI using the newly loaded GDT.
57 ; MM5 = Save time-stamp counter value high32bit
58 ; MM6 = Save time-stamp counter value low32bit.
60 ;----------------------------------------------------------------------------
64 global ASM_PFX(ModuleEntryPoint)
65 ASM_PFX(ModuleEntryPoint):
66 fninit ; clear any pending Floating point exceptions
68 ; Store the BIST value in mm0
73 ; Save time-stamp counter value
74 ; rdtsc load 64bit time-stamp counter to EDX:EAX
81 ; Load the GDT table in GdtDesc
88 ; Transition to 16 bit protected mode
90 mov eax, cr0 ; Get control register 0
91 or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #1)
92 mov cr0, eax ; Activate protected mode
94 mov eax, cr4 ; Get control register 4
95 or eax, 00000600h ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
99 ; Now we're in 16 bit protected mode
100 ; Set up the selectors for 32 bit protected mode entry
110 ; Transition to Flat 32 bit protected mode
111 ; The jump to a far pointer causes the transition to 32 bit mode
113 mov esi, ProtectedModeEntryLinearAddress
114 jmp dword far [cs:si]
116 ;----------------------------------------------------------------------------
118 ; Procedure: ProtectedModeEntryPoint
124 ; Destroys: Assume all registers
128 ; This function handles:
129 ; Call two basic APIs from FSP binary
130 ; Initializes stack with some early data (BIST, PEI entry, etc)
134 ;----------------------------------------------------------------------------
138 ProtectedModeEntryPoint:
140 ; Find the fsp info header
141 mov edi, [ASM_PFX(PcdGet32 (PcdFsptBaseAddress))]
143 mov eax, dword [edi + FVH_SIGINATURE_OFFSET]
144 cmp eax, FVH_SIGINATURE_VALID_VALUE
145 jnz FspHeaderNotFound
148 mov ax, word [edi + FVH_EXTHEADER_OFFSET_OFFSET]
150 jnz FspFvExtHeaderExist
153 mov ax, word [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header
155 jmp FspCheckFfsHeader
159 mov eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv Header
162 ; Round up to 8 byte alignment
173 cmp eax, FSP_HEADER_GUID_DWORD1
174 jnz FspHeaderNotFound
176 mov eax, dword [edi + 4]
177 cmp eax, FSP_HEADER_GUID_DWORD2
178 jnz FspHeaderNotFound
180 mov eax, dword [edi + 8]
181 cmp eax, FSP_HEADER_GUID_DWORD3
182 jnz FspHeaderNotFound
184 mov eax, dword [edi + 0Ch]
185 cmp eax, FSP_HEADER_GUID_DWORD4
186 jnz FspHeaderNotFound
188 add edi, FFS_HEADER_SIZE_VALUE ; Bypass the ffs header
190 ; Check the section type as raw section
191 mov al, byte [edi + SECTION_HEADER_TYPE_OFFSET]
193 jnz FspHeaderNotFound
195 add edi, RAW_SECTION_HEADER_SIZE_VALUE ; Bypass the section header
202 ; Get the fsp TempRamInit Api address
203 mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET]
204 add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]
206 ; Setup the hardcode stack
207 mov esp, TempRamInitStack
209 ; Call the fsp TempRamInit Api
213 cmp eax, 8000000Eh ;Check if EFI_NOT_FOUND returned. Error code for Microcode Update not found.
214 je CallSecFspInit ;If microcode not found, don't hang, but continue.
216 cmp eax, 0 ;Check if EFI_SUCCESS retuned.
219 ; ECX: start of range
225 ; Align the stack at DWORD
231 push eax ; zero - no hob list yet
232 call ASM_PFX(CallPeiCoreEntryPoint)
240 DD ASM_PFX(FsptUpdDataPtr); TempRamInitParams
243 ; ROM-based Global-Descriptor Table for the Tiano PEI Phase
246 global ASM_PFX(BootGdtTable)
249 ; GDT[0]: 0x00: Null entry, never used.
251 NULL_SEL EQU $ - GDT_BASE ; Selector [0]
253 ASM_PFX(BootGdtTable):
257 ; Linear data segment descriptor
259 LINEAR_SEL EQU $ - GDT_BASE ; Selector [0x8]
260 DW 0FFFFh ; limit 0xFFFFF
263 DB 092h ; present, ring 0, data, expand-up, writable
264 DB 0CFh ; page-granular, 32-bit
267 ; Linear code segment descriptor
269 LINEAR_CODE_SEL EQU $ - GDT_BASE ; Selector [0x10]
270 DW 0FFFFh ; limit 0xFFFFF
273 DB 09Bh ; present, ring 0, data, expand-up, not-writable
274 DB 0CFh ; page-granular, 32-bit
277 ; System data segment descriptor
279 SYS_DATA_SEL EQU $ - GDT_BASE ; Selector [0x18]
280 DW 0FFFFh ; limit 0xFFFFF
283 DB 093h ; present, ring 0, data, expand-up, not-writable
284 DB 0CFh ; page-granular, 32-bit
288 ; System code segment descriptor
290 SYS_CODE_SEL EQU $ - GDT_BASE ; Selector [0x20]
291 DW 0FFFFh ; limit 0xFFFFF
294 DB 09Ah ; present, ring 0, data, expand-up, writable
295 DB 0CFh ; page-granular, 32-bit
298 ; Spare segment descriptor
300 SYS16_CODE_SEL EQU $ - GDT_BASE ; Selector [0x28]
301 DW 0FFFFh ; limit 0xFFFFF
303 DB 0Eh ; Changed from F000 to E000.
304 DB 09Bh ; present, ring 0, code, expand-up, writable
305 DB 00h ; byte-granular, 16-bit
308 ; Spare segment descriptor
310 SYS16_DATA_SEL EQU $ - GDT_BASE ; Selector [0x30]
311 DW 0FFFFh ; limit 0xFFFF
314 DB 093h ; present, ring 0, data, expand-up, not-writable
315 DB 00h ; byte-granular, 16-bit
319 ; Spare segment descriptor
321 SPARE5_SEL EQU $ - GDT_BASE ; Selector [0x38]
325 DB 0 ; present, ring 0, data, expand-up, writable
326 DB 0 ; page-granular, 32-bit
328 GDT_SIZE EQU $ - GDT_BASE ; Size, in bytes
333 GdtDesc: ; GDT descriptor
334 DW GDT_SIZE - 1 ; GDT limit
335 DD GDT_BASE ; GDT base address
338 ProtectedModeEntryLinearAddress:
339 ProtectedModeEntryLinear:
340 DD ProtectedModeEntryPoint ; Offset of our 32 bit code