]> git.proxmox.com Git - mirror_edk2.git/blob - MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c
projects / mirror_edk2.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
MdeModulePkg/AtaAtapiPassThru: Add SATA error recovery flow
[mirror_edk2.git] / MdeModulePkg / Bus / Ata / AtaAtapiPassThru / AhciMode.c
1 /** @file
2 The file for AHCI mode of ATA host controller.
3
4 Copyright (c) 2010 - 2020, Intel Corporation. All rights reserved.<BR>
5 (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
7
8 **/
9
10 #include "AtaAtapiPassThru.h"
11
12 /**
13 Read AHCI Operation register.
14
15 @param PciIo The PCI IO protocol instance.
16 @param Offset The operation register offset.
17
18 @return The register content read.
19
20 **/
21 UINT32
22 EFIAPI
23 AhciReadReg (
24 IN EFI_PCI_IO_PROTOCOL *PciIo,
25 IN UINT32 Offset
26 )
27 {
28 UINT32 Data;
29
30 ASSERT (PciIo != NULL);
31
32 Data = 0;
33
34 PciIo->Mem.Read (
35 PciIo,
36 EfiPciIoWidthUint32,
37 EFI_AHCI_BAR_INDEX,
38 (UINT64) Offset,
39 1,
40 &Data
41 );
42
43 return Data;
44 }
45
46 /**
47 Write AHCI Operation register.
48
49 @param PciIo The PCI IO protocol instance.
50 @param Offset The operation register offset.
51 @param Data The data used to write down.
52
53 **/
54 VOID
55 EFIAPI
56 AhciWriteReg (
57 IN EFI_PCI_IO_PROTOCOL *PciIo,
58 IN UINT32 Offset,
59 IN UINT32 Data
60 )
61 {
62 ASSERT (PciIo != NULL);
63
64 PciIo->Mem.Write (
65 PciIo,
66 EfiPciIoWidthUint32,
67 EFI_AHCI_BAR_INDEX,
68 (UINT64) Offset,
69 1,
70 &Data
71 );
72
73 return ;
74 }
75
76 /**
77 Do AND operation with the value of AHCI Operation register.
78
79 @param PciIo The PCI IO protocol instance.
80 @param Offset The operation register offset.
81 @param AndData The data used to do AND operation.
82
83 **/
84 VOID
85 EFIAPI
86 AhciAndReg (
87 IN EFI_PCI_IO_PROTOCOL *PciIo,
88 IN UINT32 Offset,
89 IN UINT32 AndData
90 )
91 {
92 UINT32 Data;
93
94 ASSERT (PciIo != NULL);
95
96 Data = AhciReadReg (PciIo, Offset);
97
98 Data &= AndData;
99
100 AhciWriteReg (PciIo, Offset, Data);
101 }
102
103 /**
104 Do OR operation with the value of AHCI Operation register.
105
106 @param PciIo The PCI IO protocol instance.
107 @param Offset The operation register offset.
108 @param OrData The data used to do OR operation.
109
110 **/
111 VOID
112 EFIAPI
113 AhciOrReg (
114 IN EFI_PCI_IO_PROTOCOL *PciIo,
115 IN UINT32 Offset,
116 IN UINT32 OrData
117 )
118 {
119 UINT32 Data;
120
121 ASSERT (PciIo != NULL);
122
123 Data = AhciReadReg (PciIo, Offset);
124
125 Data |= OrData;
126
127 AhciWriteReg (PciIo, Offset, Data);
128 }
129
130 /**
131 Wait for the value of the specified MMIO register set to the test value.
132
133 @param PciIo The PCI IO protocol instance.
134 @param Offset The MMIO address to test.
135 @param MaskValue The mask value of memory.
136 @param TestValue The test value of memory.
137 @param Timeout The time out value for wait memory set, uses 100ns as a unit.
138
139 @retval EFI_TIMEOUT The MMIO setting is time out.
140 @retval EFI_SUCCESS The MMIO is correct set.
141
142 **/
143 EFI_STATUS
144 EFIAPI
145 AhciWaitMmioSet (
146 IN EFI_PCI_IO_PROTOCOL *PciIo,
147 IN UINTN Offset,
148 IN UINT32 MaskValue,
149 IN UINT32 TestValue,
150 IN UINT64 Timeout
151 )
152 {
153 UINT32 Value;
154 UINT64 Delay;
155 BOOLEAN InfiniteWait;
156
157 if (Timeout == 0) {
158 InfiniteWait = TRUE;
159 } else {
160 InfiniteWait = FALSE;
161 }
162
163 Delay = DivU64x32 (Timeout, 1000) + 1;
164
165 do {
166 //
167 // Access PCI MMIO space to see if the value is the tested one.
168 //
169 Value = AhciReadReg (PciIo, (UINT32) Offset) & MaskValue;
170
171 if (Value == TestValue) {
172 return EFI_SUCCESS;
173 }
174
175 //
176 // Stall for 100 microseconds.
177 //
178 MicroSecondDelay (100);
179
180 Delay--;
181
182 } while (InfiniteWait || (Delay > 0));
183
184 return EFI_TIMEOUT;
185 }
186
187 /**
188 Wait for the value of the specified system memory set to the test value.
189
190 @param Address The system memory address to test.
191 @param MaskValue The mask value of memory.
192 @param TestValue The test value of memory.
193 @param Timeout The time out value for wait memory set, uses 100ns as a unit.
194
195 @retval EFI_TIMEOUT The system memory setting is time out.
196 @retval EFI_SUCCESS The system memory is correct set.
197
198 **/
199 EFI_STATUS
200 EFIAPI
201 AhciWaitMemSet (
202 IN EFI_PHYSICAL_ADDRESS Address,
203 IN UINT32 MaskValue,
204 IN UINT32 TestValue,
205 IN UINT64 Timeout
206 )
207 {
208 UINT32 Value;
209 UINT64 Delay;
210 BOOLEAN InfiniteWait;
211
212 if (Timeout == 0) {
213 InfiniteWait = TRUE;
214 } else {
215 InfiniteWait = FALSE;
216 }
217
218 Delay = DivU64x32 (Timeout, 1000) + 1;
219
220 do {
221 //
222 // Access system memory to see if the value is the tested one.
223 //
224 // The system memory pointed by Address will be updated by the
225 // SATA Host Controller, "volatile" is introduced to prevent
226 // compiler from optimizing the access to the memory address
227 // to only read once.
228 //
229 Value = *(volatile UINT32 *) (UINTN) Address;
230 Value &= MaskValue;
231
232 if (Value == TestValue) {
233 return EFI_SUCCESS;
234 }
235
236 //
237 // Stall for 100 microseconds.
238 //
239 MicroSecondDelay (100);
240
241 Delay--;
242
243 } while (InfiniteWait || (Delay > 0));
244
245 return EFI_TIMEOUT;
246 }
247
248 /**
249 Check the memory status to the test value.
250
251 @param[in] Address The memory address to test.
252 @param[in] MaskValue The mask value of memory.
253 @param[in] TestValue The test value of memory.
254
255 @retval EFI_NOT_READY The memory is not set.
256 @retval EFI_SUCCESS The memory is correct set.
257 **/
258 EFI_STATUS
259 EFIAPI
260 AhciCheckMemSet (
261 IN UINTN Address,
262 IN UINT32 MaskValue,
263 IN UINT32 TestValue
264 )
265 {
266 UINT32 Value;
267
268 Value = *(volatile UINT32 *) Address;
269 Value &= MaskValue;
270
271 if (Value == TestValue) {
272 return EFI_SUCCESS;
273 }
274
275 return EFI_NOT_READY;
276 }
277
278
279 /**
280
281 Clear the port interrupt and error status. It will also clear
282 HBA interrupt status.
283
284 @param PciIo The PCI IO protocol instance.
285 @param Port The number of port.
286
287 **/
288 VOID
289 EFIAPI
290 AhciClearPortStatus (
291 IN EFI_PCI_IO_PROTOCOL *PciIo,
292 IN UINT8 Port
293 )
294 {
295 UINT32 Offset;
296
297 //
298 // Clear any error status
299 //
300 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SERR;
301 AhciWriteReg (PciIo, Offset, AhciReadReg (PciIo, Offset));
302
303 //
304 // Clear any port interrupt status
305 //
306 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_IS;
307 AhciWriteReg (PciIo, Offset, AhciReadReg (PciIo, Offset));
308
309 //
310 // Clear any HBA interrupt status
311 //
312 AhciWriteReg (PciIo, EFI_AHCI_IS_OFFSET, AhciReadReg (PciIo, EFI_AHCI_IS_OFFSET));
313 }
314
315 /**
316 This function is used to dump the Status Registers and if there is ERR bit set
317 in the Status Register, the Error Register's value is also be dumped.
318
319 @param PciIo The PCI IO protocol instance.
320 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
321 @param Port The number of port.
322 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
323
324 **/
325 VOID
326 EFIAPI
327 AhciDumpPortStatus (
328 IN EFI_PCI_IO_PROTOCOL *PciIo,
329 IN EFI_AHCI_REGISTERS *AhciRegisters,
330 IN UINT8 Port,
331 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
332 )
333 {
334 UINTN Offset;
335 UINT32 Data;
336 UINTN FisBaseAddr;
337 EFI_STATUS Status;
338
339 ASSERT (PciIo != NULL);
340
341 if (AtaStatusBlock != NULL) {
342 ZeroMem (AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
343
344 FisBaseAddr = (UINTN)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);
345 Offset = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;
346
347 Status = AhciCheckMemSet (Offset, EFI_AHCI_FIS_TYPE_MASK, EFI_AHCI_FIS_REGISTER_D2H);
348 if (!EFI_ERROR (Status)) {
349 //
350 // If D2H FIS is received, update StatusBlock with its content.
351 //
352 CopyMem (AtaStatusBlock, (UINT8 *)Offset, sizeof (EFI_ATA_STATUS_BLOCK));
353 } else {
354 //
355 // If D2H FIS is not received, only update Status & Error field through PxTFD
356 // as there is no other way to get the content of the Shadow Register Block.
357 //
358 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
359 Data = AhciReadReg (PciIo, (UINT32)Offset);
360
361 AtaStatusBlock->AtaStatus = (UINT8)Data;
362 if ((AtaStatusBlock->AtaStatus & BIT0) != 0) {
363 AtaStatusBlock->AtaError = (UINT8)(Data >> 8);
364 }
365 }
366 }
367 }
368
369
370 /**
371 Enable the FIS running for giving port.
372
373 @param PciIo The PCI IO protocol instance.
374 @param Port The number of port.
375 @param Timeout The timeout value of enabling FIS, uses 100ns as a unit.
376
377 @retval EFI_DEVICE_ERROR The FIS enable setting fails.
378 @retval EFI_TIMEOUT The FIS enable setting is time out.
379 @retval EFI_SUCCESS The FIS enable successfully.
380
381 **/
382 EFI_STATUS
383 EFIAPI
384 AhciEnableFisReceive (
385 IN EFI_PCI_IO_PROTOCOL *PciIo,
386 IN UINT8 Port,
387 IN UINT64 Timeout
388 )
389 {
390 UINT32 Offset;
391
392 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
393 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_FRE);
394
395 return EFI_SUCCESS;
396 }
397
398 /**
399 Disable the FIS running for giving port.
400
401 @param PciIo The PCI IO protocol instance.
402 @param Port The number of port.
403 @param Timeout The timeout value of disabling FIS, uses 100ns as a unit.
404
405 @retval EFI_DEVICE_ERROR The FIS disable setting fails.
406 @retval EFI_TIMEOUT The FIS disable setting is time out.
407 @retval EFI_UNSUPPORTED The port is in running state.
408 @retval EFI_SUCCESS The FIS disable successfully.
409
410 **/
411 EFI_STATUS
412 EFIAPI
413 AhciDisableFisReceive (
414 IN EFI_PCI_IO_PROTOCOL *PciIo,
415 IN UINT8 Port,
416 IN UINT64 Timeout
417 )
418 {
419 UINT32 Offset;
420 UINT32 Data;
421
422 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
423 Data = AhciReadReg (PciIo, Offset);
424
425 //
426 // Before disabling Fis receive, the DMA engine of the port should NOT be in running status.
427 //
428 if ((Data & (EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_CR)) != 0) {
429 return EFI_UNSUPPORTED;
430 }
431
432 //
433 // Check if the Fis receive DMA engine for the port is running.
434 //
435 if ((Data & EFI_AHCI_PORT_CMD_FR) != EFI_AHCI_PORT_CMD_FR) {
436 return EFI_SUCCESS;
437 }
438
439 AhciAndReg (PciIo, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_FRE));
440
441 return AhciWaitMmioSet (
442 PciIo,
443 Offset,
444 EFI_AHCI_PORT_CMD_FR,
445 0,
446 Timeout
447 );
448 }
449
450
451
452 /**
453 Build the command list, command table and prepare the fis receiver.
454
455 @param PciIo The PCI IO protocol instance.
456 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
457 @param Port The number of port.
458 @param PortMultiplier The timeout value of stop.
459 @param CommandFis The control fis will be used for the transfer.
460 @param CommandList The command list will be used for the transfer.
461 @param AtapiCommand The atapi command will be used for the transfer.
462 @param AtapiCommandLength The length of the atapi command.
463 @param CommandSlotNumber The command slot will be used for the transfer.
464 @param DataPhysicalAddr The pointer to the data buffer pci bus master address.
465 @param DataLength The data count to be transferred.
466
467 **/
468 VOID
469 EFIAPI
470 AhciBuildCommand (
471 IN EFI_PCI_IO_PROTOCOL *PciIo,
472 IN EFI_AHCI_REGISTERS *AhciRegisters,
473 IN UINT8 Port,
474 IN UINT8 PortMultiplier,
475 IN EFI_AHCI_COMMAND_FIS *CommandFis,
476 IN EFI_AHCI_COMMAND_LIST *CommandList,
477 IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,
478 IN UINT8 AtapiCommandLength,
479 IN UINT8 CommandSlotNumber,
480 IN OUT VOID *DataPhysicalAddr,
481 IN UINT32 DataLength
482 )
483 {
484 UINT64 BaseAddr;
485 UINT32 PrdtNumber;
486 UINT32 PrdtIndex;
487 UINTN RemainedData;
488 UINTN MemAddr;
489 DATA_64 Data64;
490 UINT32 Offset;
491
492 //
493 // Filling the PRDT
494 //
495 PrdtNumber = (UINT32)DivU64x32 (((UINT64)DataLength + EFI_AHCI_MAX_DATA_PER_PRDT - 1), EFI_AHCI_MAX_DATA_PER_PRDT);
496
497 //
498 // According to AHCI 1.3 spec, a PRDT entry can point to a maximum 4MB data block.
499 // It also limits that the maximum amount of the PRDT entry in the command table
500 // is 65535.
501 //
502 ASSERT (PrdtNumber <= 65535);
503
504 Data64.Uint64 = (UINTN) (AhciRegisters->AhciRFis) + sizeof (EFI_AHCI_RECEIVED_FIS) * Port;
505
506 BaseAddr = Data64.Uint64;
507
508 ZeroMem ((VOID *)((UINTN) BaseAddr), sizeof (EFI_AHCI_RECEIVED_FIS));
509
510 ZeroMem (AhciRegisters->AhciCommandTable, sizeof (EFI_AHCI_COMMAND_TABLE));
511
512 CommandFis->AhciCFisPmNum = PortMultiplier;
513
514 CopyMem (&AhciRegisters->AhciCommandTable->CommandFis, CommandFis, sizeof (EFI_AHCI_COMMAND_FIS));
515
516 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
517 if (AtapiCommand != NULL) {
518 CopyMem (
519 &AhciRegisters->AhciCommandTable->AtapiCmd,
520 AtapiCommand,
521 AtapiCommandLength
522 );
523
524 CommandList->AhciCmdA = 1;
525 CommandList->AhciCmdP = 1;
526
527 AhciOrReg (PciIo, Offset, (EFI_AHCI_PORT_CMD_DLAE | EFI_AHCI_PORT_CMD_ATAPI));
528 } else {
529 AhciAndReg (PciIo, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_DLAE | EFI_AHCI_PORT_CMD_ATAPI));
530 }
531
532 RemainedData = (UINTN) DataLength;
533 MemAddr = (UINTN) DataPhysicalAddr;
534 CommandList->AhciCmdPrdtl = PrdtNumber;
535
536 for (PrdtIndex = 0; PrdtIndex < PrdtNumber; PrdtIndex++) {
537 if (RemainedData < EFI_AHCI_MAX_DATA_PER_PRDT) {
538 AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDbc = (UINT32)RemainedData - 1;
539 } else {
540 AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDbc = EFI_AHCI_MAX_DATA_PER_PRDT - 1;
541 }
542
543 Data64.Uint64 = (UINT64)MemAddr;
544 AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDba = Data64.Uint32.Lower32;
545 AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDbau = Data64.Uint32.Upper32;
546 RemainedData -= EFI_AHCI_MAX_DATA_PER_PRDT;
547 MemAddr += EFI_AHCI_MAX_DATA_PER_PRDT;
548 }
549
550 //
551 // Set the last PRDT to Interrupt On Complete
552 //
553 if (PrdtNumber > 0) {
554 AhciRegisters->AhciCommandTable->PrdtTable[PrdtNumber - 1].AhciPrdtIoc = 1;
555 }
556
557 CopyMem (
558 (VOID *) ((UINTN) AhciRegisters->AhciCmdList + (UINTN) CommandSlotNumber * sizeof (EFI_AHCI_COMMAND_LIST)),
559 CommandList,
560 sizeof (EFI_AHCI_COMMAND_LIST)
561 );
562
563 Data64.Uint64 = (UINT64)(UINTN) AhciRegisters->AhciCommandTablePciAddr;
564 AhciRegisters->AhciCmdList[CommandSlotNumber].AhciCmdCtba = Data64.Uint32.Lower32;
565 AhciRegisters->AhciCmdList[CommandSlotNumber].AhciCmdCtbau = Data64.Uint32.Upper32;
566 AhciRegisters->AhciCmdList[CommandSlotNumber].AhciCmdPmp = PortMultiplier;
567
568 }
569
570 /**
571 Build a command FIS.
572
573 @param CmdFis A pointer to the EFI_AHCI_COMMAND_FIS data structure.
574 @param AtaCommandBlock A pointer to the AhciBuildCommandFis data structure.
575
576 **/
577 VOID
578 EFIAPI
579 AhciBuildCommandFis (
580 IN OUT EFI_AHCI_COMMAND_FIS *CmdFis,
581 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock
582 )
583 {
584 ZeroMem (CmdFis, sizeof (EFI_AHCI_COMMAND_FIS));
585
586 CmdFis->AhciCFisType = EFI_AHCI_FIS_REGISTER_H2D;
587 //
588 // Indicator it's a command
589 //
590 CmdFis->AhciCFisCmdInd = 0x1;
591 CmdFis->AhciCFisCmd = AtaCommandBlock->AtaCommand;
592
593 CmdFis->AhciCFisFeature = AtaCommandBlock->AtaFeatures;
594 CmdFis->AhciCFisFeatureExp = AtaCommandBlock->AtaFeaturesExp;
595
596 CmdFis->AhciCFisSecNum = AtaCommandBlock->AtaSectorNumber;
597 CmdFis->AhciCFisSecNumExp = AtaCommandBlock->AtaSectorNumberExp;
598
599 CmdFis->AhciCFisClyLow = AtaCommandBlock->AtaCylinderLow;
600 CmdFis->AhciCFisClyLowExp = AtaCommandBlock->AtaCylinderLowExp;
601
602 CmdFis->AhciCFisClyHigh = AtaCommandBlock->AtaCylinderHigh;
603 CmdFis->AhciCFisClyHighExp = AtaCommandBlock->AtaCylinderHighExp;
604
605 CmdFis->AhciCFisSecCount = AtaCommandBlock->AtaSectorCount;
606 CmdFis->AhciCFisSecCountExp = AtaCommandBlock->AtaSectorCountExp;
607
608 CmdFis->AhciCFisDevHead = (UINT8) (AtaCommandBlock->AtaDeviceHead | 0xE0);
609 }
610
611 /**
612 Wait until SATA device reports it is ready for operation.
613
614 @param[in] PciIo Pointer to AHCI controller PciIo.
615 @param[in] Port SATA port index on which to reset.
616
617 @retval EFI_SUCCESS Device ready for operation.
618 @retval EFI_TIMEOUT Device failed to get ready within required period.
619 **/
620 EFI_STATUS
621 AhciWaitDeviceReady (
622 IN EFI_PCI_IO_PROTOCOL *PciIo,
623 IN UINT8 Port
624 )
625 {
626 UINT32 PhyDetectDelay;
627 UINT32 Data;
628 UINT32 Offset;
629
630 //
631 // According to SATA1.0a spec section 5.2, we need to wait for PxTFD.BSY and PxTFD.DRQ
632 // and PxTFD.ERR to be zero. The maximum wait time is 16s which is defined at ATA spec.
633 //
634 PhyDetectDelay = 16 * 1000;
635 do {
636 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SERR;
637 if (AhciReadReg(PciIo, Offset) != 0) {
638 AhciWriteReg (PciIo, Offset, AhciReadReg(PciIo, Offset));
639 }
640 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
641
642 Data = AhciReadReg (PciIo, Offset) & EFI_AHCI_PORT_TFD_MASK;
643 if (Data == 0) {
644 break;
645 }
646
647 MicroSecondDelay (1000);
648 PhyDetectDelay--;
649 } while (PhyDetectDelay > 0);
650
651 if (PhyDetectDelay == 0) {
652 DEBUG ((DEBUG_ERROR, "Port %d Device not ready (TFD=0x%X)\n", Port, Data));
653 return EFI_TIMEOUT;
654 } else {
655 return EFI_SUCCESS;
656 }
657 }
658
659
660 /**
661 Reset the SATA port. Algorithm follows AHCI spec 1.3.1 section 10.4.2
662
663 @param[in] PciIo Pointer to AHCI controller PciIo.
664 @param[in] Port SATA port index on which to reset.
665
666 @retval EFI_SUCCESS Port reset.
667 @retval Others Failed to reset the port.
668 **/
669 EFI_STATUS
670 AhciResetPort (
671 IN EFI_PCI_IO_PROTOCOL *PciIo,
672 IN UINT8 Port
673 )
674 {
675 UINT32 Offset;
676 EFI_STATUS Status;
677
678 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SCTL;
679 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_SCTL_DET_INIT);
680 //
681 // SW is required to keep DET set to 0x1 at least for 1 milisecond to ensure that
682 // at least one COMRESET signal is sent.
683 //
684 MicroSecondDelay(1000);
685 AhciAndReg (PciIo, Offset, ~(UINT32)EFI_AHCI_PORT_SSTS_DET_MASK);
686
687 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SSTS;
688 Status = AhciWaitMmioSet (PciIo, Offset, EFI_AHCI_PORT_SSTS_DET_MASK, EFI_AHCI_PORT_SSTS_DET_PCE, ATA_ATAPI_TIMEOUT);
689 if (EFI_ERROR (Status)) {
690 return Status;
691 }
692
693 return AhciWaitDeviceReady (PciIo, Port);
694 }
695
696 /**
697 Recovers the SATA port from error condition.
698 This function implements algorithm described in
699 AHCI spec 1.3.1 section 6.2.2
700
701 @param[in] PciIo Pointer to AHCI controller PciIo.
702 @param[in] Port SATA port index on which to check.
703
704 @retval EFI_SUCCESS Port recovered.
705 @retval Others Failed to recover port.
706 **/
707 EFI_STATUS
708 AhciRecoverPortError (
709 IN EFI_PCI_IO_PROTOCOL *PciIo,
710 IN UINT8 Port
711 )
712 {
713 UINT32 Offset;
714 UINT32 PortInterrupt;
715 UINT32 PortTfd;
716 EFI_STATUS Status;
717
718 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_IS;
719 PortInterrupt = AhciReadReg (PciIo, Offset);
720 if ((PortInterrupt & EFI_AHCI_PORT_IS_FATAL_ERROR_MASK) == 0) {
721 //
722 // No fatal error detected. Exit with success as port should still be operational.
723 // No need to clear IS as it will be cleared when the next command starts.
724 //
725 return EFI_SUCCESS;
726 }
727
728 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
729 AhciAndReg (PciIo, Offset, ~(UINT32)EFI_AHCI_PORT_CMD_ST);
730
731 Status = AhciWaitMmioSet (PciIo, Offset, EFI_AHCI_PORT_CMD_CR, 0, ATA_ATAPI_TIMEOUT);
732 if (EFI_ERROR (Status)) {
733 DEBUG ((DEBUG_ERROR, "Ahci port %d is in hung state, aborting recovery\n", Port));
734 return Status;
735 }
736
737 //
738 // If TFD.BSY or TFD.DRQ is still set it means that drive is hung and software has
739 // to reset it before sending any additional commands.
740 //
741 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
742 PortTfd = AhciReadReg (PciIo, Offset);
743 if ((PortTfd & (EFI_AHCI_PORT_TFD_BSY | EFI_AHCI_PORT_TFD_DRQ)) != 0) {
744 Status = AhciResetPort (PciIo, Port);
745 if (EFI_ERROR (Status)) {
746 DEBUG ((DEBUG_ERROR, "Failed to reset the port %d\n", Port));
747 }
748 }
749
750 return EFI_SUCCESS;
751 }
752
753 /**
754 Checks if specified FIS has been received.
755
756 @param[in] PciIo Pointer to AHCI controller PciIo.
757 @param[in] Port SATA port index on which to check.
758 @param[in] FisType FIS type for which to check.
759
760 @retval EFI_SUCCESS FIS received.
761 @retval EFI_NOT_READY FIS not received yet.
762 @retval EFI_DEVICE_ERROR AHCI controller reported an error on port.
763 **/
764 EFI_STATUS
765 AhciCheckFisReceived (
766 IN EFI_PCI_IO_PROTOCOL *PciIo,
767 IN UINT8 Port,
768 IN SATA_FIS_TYPE FisType
769 )
770 {
771 UINT32 Offset;
772 UINT32 PortInterrupt;
773 UINT32 PortTfd;
774
775 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_IS;
776 PortInterrupt = AhciReadReg (PciIo, Offset);
777 if ((PortInterrupt & EFI_AHCI_PORT_IS_ERROR_MASK) != 0) {
778 DEBUG ((DEBUG_ERROR, "AHCI: Error interrupt reported PxIS: %X\n", PortInterrupt));
779 return EFI_DEVICE_ERROR;
780 }
781 //
782 // For PIO setup FIS - According to SATA 2.6 spec section 11.7, D2h FIS means an error encountered.
783 // But Qemu and Marvel 9230 sata controller may just receive a D2h FIS from device
784 // after the transaction is finished successfully.
785 // To get better device compatibilities, we further check if the PxTFD's ERR bit is set.
786 // By this way, we can know if there is a real error happened.
787 //
788 if (((FisType == SataFisD2H) && ((PortInterrupt & EFI_AHCI_PORT_IS_DHRS) != 0)) ||
789 ((FisType == SataFisPioSetup) && (PortInterrupt & (EFI_AHCI_PORT_IS_PSS | EFI_AHCI_PORT_IS_DHRS)) != 0) ||
790 ((FisType == SataFisDmaSetup) && (PortInterrupt & (EFI_AHCI_PORT_IS_DSS | EFI_AHCI_PORT_IS_DHRS)) != 0)) {
791 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
792 PortTfd = AhciReadReg (PciIo, (UINT32) Offset);
793 if ((PortTfd & EFI_AHCI_PORT_TFD_ERR) != 0) {
794 return EFI_DEVICE_ERROR;
795 } else {
796 return EFI_SUCCESS;
797 }
798 }
799
800 return EFI_NOT_READY;
801 }
802
803 /**
804 Waits until specified FIS has been received.
805
806 @param[in] PciIo Pointer to AHCI controller PciIo.
807 @param[in] Port SATA port index on which to check.
808 @param[in] Timeout Time after which function should stop polling.
809 @param[in] FisType FIS type for which to check.
810
811 @retval EFI_SUCCESS FIS received.
812 @retval EFI_TIMEOUT FIS failed to arrive within a specified time period.
813 @retval EFI_DEVICE_ERROR AHCI controller reported an error on port.
814 **/
815 EFI_STATUS
816 AhciWaitUntilFisReceived (
817 IN EFI_PCI_IO_PROTOCOL *PciIo,
818 IN UINT8 Port,
819 IN UINT64 Timeout,
820 IN SATA_FIS_TYPE FisType
821 )
822 {
823 EFI_STATUS Status;
824 BOOLEAN InfiniteWait;
825 UINT64 Delay;
826
827 Delay = DivU64x32 (Timeout, 1000) + 1;
828 if (Timeout == 0) {
829 InfiniteWait = TRUE;
830 } else {
831 InfiniteWait = FALSE;
832 }
833
834 do {
835 Status = AhciCheckFisReceived (PciIo, Port, FisType);
836 if (Status != EFI_NOT_READY) {
837 return Status;
838 }
839 //
840 // Stall for 100 microseconds.
841 //
842 MicroSecondDelay (100);
843 Delay--;
844 } while (InfiniteWait || (Delay > 0));
845
846 return EFI_TIMEOUT;
847 }
848
849 /**
850 Start a PIO data transfer on specific port.
851
852 @param[in] PciIo The PCI IO protocol instance.
853 @param[in] AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
854 @param[in] Port The number of port.
855 @param[in] PortMultiplier The timeout value of stop.
856 @param[in] AtapiCommand The atapi command will be used for the
857 transfer.
858 @param[in] AtapiCommandLength The length of the atapi command.
859 @param[in] Read The transfer direction.
860 @param[in] AtaCommandBlock The EFI_ATA_COMMAND_BLOCK data.
861 @param[in, out] AtaStatusBlock The EFI_ATA_STATUS_BLOCK data.
862 @param[in, out] MemoryAddr The pointer to the data buffer.
863 @param[in] DataCount The data count to be transferred.
864 @param[in] Timeout The timeout value of non data transfer, uses 100ns as a unit.
865 @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
866 used by non-blocking mode.
867
868 @retval EFI_DEVICE_ERROR The PIO data transfer abort with error occurs.
869 @retval EFI_TIMEOUT The operation is time out.
870 @retval EFI_UNSUPPORTED The device is not ready for transfer.
871 @retval EFI_SUCCESS The PIO data transfer executes successfully.
872
873 **/
874 EFI_STATUS
875 EFIAPI
876 AhciPioTransfer (
877 IN EFI_PCI_IO_PROTOCOL *PciIo,
878 IN EFI_AHCI_REGISTERS *AhciRegisters,
879 IN UINT8 Port,
880 IN UINT8 PortMultiplier,
881 IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,
882 IN UINT8 AtapiCommandLength,
883 IN BOOLEAN Read,
884 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
885 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
886 IN OUT VOID *MemoryAddr,
887 IN UINT32 DataCount,
888 IN UINT64 Timeout,
889 IN ATA_NONBLOCK_TASK *Task
890 )
891 {
892 EFI_STATUS Status;
893 EFI_PHYSICAL_ADDRESS PhyAddr;
894 VOID *Map;
895 UINTN MapLength;
896 EFI_PCI_IO_PROTOCOL_OPERATION Flag;
897 EFI_AHCI_COMMAND_FIS CFis;
898 EFI_AHCI_COMMAND_LIST CmdList;
899 UINT32 PrdCount;
900
901 if (Read) {
902 Flag = EfiPciIoOperationBusMasterWrite;
903 } else {
904 Flag = EfiPciIoOperationBusMasterRead;
905 }
906
907 //
908 // construct command list and command table with pci bus address
909 //
910 MapLength = DataCount;
911 Status = PciIo->Map (
912 PciIo,
913 Flag,
914 MemoryAddr,
915 &MapLength,
916 &PhyAddr,
917 &Map
918 );
919
920 if (EFI_ERROR (Status) || (DataCount != MapLength)) {
921 return EFI_BAD_BUFFER_SIZE;
922 }
923
924 //
925 // Package read needed
926 //
927 AhciBuildCommandFis (&CFis, AtaCommandBlock);
928
929 ZeroMem (&CmdList, sizeof (EFI_AHCI_COMMAND_LIST));
930
931 CmdList.AhciCmdCfl = EFI_AHCI_FIS_REGISTER_H2D_LENGTH / 4;
932 CmdList.AhciCmdW = Read ? 0 : 1;
933
934 AhciBuildCommand (
935 PciIo,
936 AhciRegisters,
937 Port,
938 PortMultiplier,
939 &CFis,
940 &CmdList,
941 AtapiCommand,
942 AtapiCommandLength,
943 0,
944 (VOID *)(UINTN)PhyAddr,
945 DataCount
946 );
947
948 Status = AhciStartCommand (
949 PciIo,
950 Port,
951 0,
952 Timeout
953 );
954 if (EFI_ERROR (Status)) {
955 goto Exit;
956 }
957
958 if (Read && (AtapiCommand == 0)) {
959 Status = AhciWaitUntilFisReceived (PciIo, Port, Timeout, SataFisPioSetup);
960 if (Status == EFI_SUCCESS) {
961 PrdCount = *(volatile UINT32 *) (&(AhciRegisters->AhciCmdList[0].AhciCmdPrdbc));
962 if (PrdCount == DataCount) {
963 Status = EFI_SUCCESS;
964 } else {
965 Status = EFI_DEVICE_ERROR;
966 }
967 }
968 } else {
969 Status = AhciWaitUntilFisReceived (PciIo, Port, Timeout, SataFisD2H);
970 }
971
972 if (Status == EFI_DEVICE_ERROR) {
973 AhciRecoverPortError (PciIo, Port);
974 }
975
976 Exit:
977 AhciStopCommand (
978 PciIo,
979 Port,
980 Timeout
981 );
982
983 AhciDisableFisReceive (
984 PciIo,
985 Port,
986 Timeout
987 );
988
989 PciIo->Unmap (
990 PciIo,
991 Map
992 );
993
994 AhciDumpPortStatus (PciIo, AhciRegisters, Port, AtaStatusBlock);
995
996 return Status;
997 }
998
999 /**
1000 Start a DMA data transfer on specific port
1001
1002 @param[in] Instance The ATA_ATAPI_PASS_THRU_INSTANCE protocol instance.
1003 @param[in] AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
1004 @param[in] Port The number of port.
1005 @param[in] PortMultiplier The timeout value of stop.
1006 @param[in] AtapiCommand The atapi command will be used for the
1007 transfer.
1008 @param[in] AtapiCommandLength The length of the atapi command.
1009 @param[in] Read The transfer direction.
1010 @param[in] AtaCommandBlock The EFI_ATA_COMMAND_BLOCK data.
1011 @param[in, out] AtaStatusBlock The EFI_ATA_STATUS_BLOCK data.
1012 @param[in, out] MemoryAddr The pointer to the data buffer.
1013 @param[in] DataCount The data count to be transferred.
1014 @param[in] Timeout The timeout value of non data transfer, uses 100ns as a unit.
1015 @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
1016 used by non-blocking mode.
1017
1018 @retval EFI_DEVICE_ERROR The DMA data transfer abort with error occurs.
1019 @retval EFI_TIMEOUT The operation is time out.
1020 @retval EFI_UNSUPPORTED The device is not ready for transfer.
1021 @retval EFI_SUCCESS The DMA data transfer executes successfully.
1022
1023 **/
1024 EFI_STATUS
1025 EFIAPI
1026 AhciDmaTransfer (
1027 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
1028 IN EFI_AHCI_REGISTERS *AhciRegisters,
1029 IN UINT8 Port,
1030 IN UINT8 PortMultiplier,
1031 IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,
1032 IN UINT8 AtapiCommandLength,
1033 IN BOOLEAN Read,
1034 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
1035 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
1036 IN OUT VOID *MemoryAddr,
1037 IN UINT32 DataCount,
1038 IN UINT64 Timeout,
1039 IN ATA_NONBLOCK_TASK *Task
1040 )
1041 {
1042 EFI_STATUS Status;
1043 EFI_PHYSICAL_ADDRESS PhyAddr;
1044 VOID *Map;
1045 UINTN MapLength;
1046 EFI_PCI_IO_PROTOCOL_OPERATION Flag;
1047 EFI_AHCI_COMMAND_FIS CFis;
1048 EFI_AHCI_COMMAND_LIST CmdList;
1049
1050 EFI_PCI_IO_PROTOCOL *PciIo;
1051 EFI_TPL OldTpl;
1052
1053 Map = NULL;
1054 PciIo = Instance->PciIo;
1055
1056 if (PciIo == NULL) {
1057 return EFI_INVALID_PARAMETER;
1058 }
1059
1060 //
1061 // Before starting the Blocking BlockIO operation, push to finish all non-blocking
1062 // BlockIO tasks.
1063 // Delay 100us to simulate the blocking time out checking.
1064 //
1065 OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
1066 while ((Task == NULL) && (!IsListEmpty (&Instance->NonBlockingTaskList))) {
1067 AsyncNonBlockingTransferRoutine (NULL, Instance);
1068 //
1069 // Stall for 100us.
1070 //
1071 MicroSecondDelay (100);
1072 }
1073 gBS->RestoreTPL (OldTpl);
1074
1075 if ((Task == NULL) || ((Task != NULL) && (!Task->IsStart))) {
1076 //
1077 // Mark the Task to indicate that it has been started.
1078 //
1079 if (Task != NULL) {
1080 Task->IsStart = TRUE;
1081 }
1082 if (Read) {
1083 Flag = EfiPciIoOperationBusMasterWrite;
1084 } else {
1085 Flag = EfiPciIoOperationBusMasterRead;
1086 }
1087
1088 //
1089 // Construct command list and command table with pci bus address.
1090 //
1091 MapLength = DataCount;
1092 Status = PciIo->Map (
1093 PciIo,
1094 Flag,
1095 MemoryAddr,
1096 &MapLength,
1097 &PhyAddr,
1098 &Map
1099 );
1100
1101 if (EFI_ERROR (Status) || (DataCount != MapLength)) {
1102 return EFI_BAD_BUFFER_SIZE;
1103 }
1104
1105 if (Task != NULL) {
1106 Task->Map = Map;
1107 }
1108 //
1109 // Package read needed
1110 //
1111 AhciBuildCommandFis (&CFis, AtaCommandBlock);
1112
1113 ZeroMem (&CmdList, sizeof (EFI_AHCI_COMMAND_LIST));
1114
1115 CmdList.AhciCmdCfl = EFI_AHCI_FIS_REGISTER_H2D_LENGTH / 4;
1116 CmdList.AhciCmdW = Read ? 0 : 1;
1117
1118 AhciBuildCommand (
1119 PciIo,
1120 AhciRegisters,
1121 Port,
1122 PortMultiplier,
1123 &CFis,
1124 &CmdList,
1125 AtapiCommand,
1126 AtapiCommandLength,
1127 0,
1128 (VOID *)(UINTN)PhyAddr,
1129 DataCount
1130 );
1131
1132 Status = AhciStartCommand (
1133 PciIo,
1134 Port,
1135 0,
1136 Timeout
1137 );
1138 if (EFI_ERROR (Status)) {
1139 goto Exit;
1140 }
1141 }
1142
1143 if (Task != NULL) {
1144 Status = AhciCheckFisReceived (PciIo, Port, SataFisD2H);
1145 if (Status == EFI_NOT_READY) {
1146 if (!Task->InfiniteWait && Task->RetryTimes == 0) {
1147 Status = EFI_TIMEOUT;
1148 } else {
1149 Task->RetryTimes--;
1150 }
1151 }
1152 } else {
1153 Status = AhciWaitUntilFisReceived (PciIo, Port, Timeout, SataFisD2H);
1154 }
1155
1156 if (Status == EFI_DEVICE_ERROR) {
1157 AhciRecoverPortError (PciIo, Port);
1158 }
1159
1160 Exit:
1161 //
1162 // For Blocking mode, the command should be stopped, the Fis should be disabled
1163 // and the PciIo should be unmapped.
1164 // For non-blocking mode, only when a error is happened (if the return status is
1165 // EFI_NOT_READY that means the command doesn't finished, try again.), first do the
1166 // context cleanup, then set the packet's Asb status.
1167 //
1168 if (Task == NULL ||
1169 ((Task != NULL) && (Status != EFI_NOT_READY))
1170 ) {
1171 AhciStopCommand (
1172 PciIo,
1173 Port,
1174 Timeout
1175 );
1176
1177 AhciDisableFisReceive (
1178 PciIo,
1179 Port,
1180 Timeout
1181 );
1182
1183 PciIo->Unmap (
1184 PciIo,
1185 (Task != NULL) ? Task->Map : Map
1186 );
1187
1188 if (Task != NULL) {
1189 Task->Packet->Asb->AtaStatus = 0x01;
1190 }
1191 }
1192
1193 AhciDumpPortStatus (PciIo, AhciRegisters, Port, AtaStatusBlock);
1194 return Status;
1195 }
1196
1197 /**
1198 Start a non data transfer on specific port.
1199
1200 @param[in] PciIo The PCI IO protocol instance.
1201 @param[in] AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
1202 @param[in] Port The number of port.
1203 @param[in] PortMultiplier The timeout value of stop.
1204 @param[in] AtapiCommand The atapi command will be used for the
1205 transfer.
1206 @param[in] AtapiCommandLength The length of the atapi command.
1207 @param[in] AtaCommandBlock The EFI_ATA_COMMAND_BLOCK data.
1208 @param[in, out] AtaStatusBlock The EFI_ATA_STATUS_BLOCK data.
1209 @param[in] Timeout The timeout value of non data transfer, uses 100ns as a unit.
1210 @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
1211 used by non-blocking mode.
1212
1213 @retval EFI_DEVICE_ERROR The non data transfer abort with error occurs.
1214 @retval EFI_TIMEOUT The operation is time out.
1215 @retval EFI_UNSUPPORTED The device is not ready for transfer.
1216 @retval EFI_SUCCESS The non data transfer executes successfully.
1217
1218 **/
1219 EFI_STATUS
1220 EFIAPI
1221 AhciNonDataTransfer (
1222 IN EFI_PCI_IO_PROTOCOL *PciIo,
1223 IN EFI_AHCI_REGISTERS *AhciRegisters,
1224 IN UINT8 Port,
1225 IN UINT8 PortMultiplier,
1226 IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,
1227 IN UINT8 AtapiCommandLength,
1228 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
1229 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
1230 IN UINT64 Timeout,
1231 IN ATA_NONBLOCK_TASK *Task
1232 )
1233 {
1234 EFI_STATUS Status;
1235 EFI_AHCI_COMMAND_FIS CFis;
1236 EFI_AHCI_COMMAND_LIST CmdList;
1237
1238 //
1239 // Package read needed
1240 //
1241 AhciBuildCommandFis (&CFis, AtaCommandBlock);
1242
1243 ZeroMem (&CmdList, sizeof (EFI_AHCI_COMMAND_LIST));
1244
1245 CmdList.AhciCmdCfl = EFI_AHCI_FIS_REGISTER_H2D_LENGTH / 4;
1246
1247 AhciBuildCommand (
1248 PciIo,
1249 AhciRegisters,
1250 Port,
1251 PortMultiplier,
1252 &CFis,
1253 &CmdList,
1254 AtapiCommand,
1255 AtapiCommandLength,
1256 0,
1257 NULL,
1258 0
1259 );
1260
1261 Status = AhciStartCommand (
1262 PciIo,
1263 Port,
1264 0,
1265 Timeout
1266 );
1267 if (EFI_ERROR (Status)) {
1268 goto Exit;
1269 }
1270
1271 Status = AhciWaitUntilFisReceived (PciIo, Port, Timeout, SataFisD2H);
1272 if (Status == EFI_DEVICE_ERROR) {
1273 AhciRecoverPortError (PciIo, Port);
1274 }
1275
1276 Exit:
1277 AhciStopCommand (
1278 PciIo,
1279 Port,
1280 Timeout
1281 );
1282
1283 AhciDisableFisReceive (
1284 PciIo,
1285 Port,
1286 Timeout
1287 );
1288
1289 AhciDumpPortStatus (PciIo, AhciRegisters, Port, AtaStatusBlock);
1290
1291 return Status;
1292 }
1293
1294 /**
1295 Stop command running for giving port
1296
1297 @param PciIo The PCI IO protocol instance.
1298 @param Port The number of port.
1299 @param Timeout The timeout value of stop, uses 100ns as a unit.
1300
1301 @retval EFI_DEVICE_ERROR The command stop unsuccessfully.
1302 @retval EFI_TIMEOUT The operation is time out.
1303 @retval EFI_SUCCESS The command stop successfully.
1304
1305 **/
1306 EFI_STATUS
1307 EFIAPI
1308 AhciStopCommand (
1309 IN EFI_PCI_IO_PROTOCOL *PciIo,
1310 IN UINT8 Port,
1311 IN UINT64 Timeout
1312 )
1313 {
1314 UINT32 Offset;
1315 UINT32 Data;
1316
1317 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
1318 Data = AhciReadReg (PciIo, Offset);
1319
1320 if ((Data & (EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_CR)) == 0) {
1321 return EFI_SUCCESS;
1322 }
1323
1324 if ((Data & EFI_AHCI_PORT_CMD_ST) != 0) {
1325 AhciAndReg (PciIo, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_ST));
1326 }
1327
1328 return AhciWaitMmioSet (
1329 PciIo,
1330 Offset,
1331 EFI_AHCI_PORT_CMD_CR,
1332 0,
1333 Timeout
1334 );
1335 }
1336
1337 /**
1338 Start command for give slot on specific port.
1339
1340 @param PciIo The PCI IO protocol instance.
1341 @param Port The number of port.
1342 @param CommandSlot The number of Command Slot.
1343 @param Timeout The timeout value of start, uses 100ns as a unit.
1344
1345 @retval EFI_DEVICE_ERROR The command start unsuccessfully.
1346 @retval EFI_TIMEOUT The operation is time out.
1347 @retval EFI_SUCCESS The command start successfully.
1348
1349 **/
1350 EFI_STATUS
1351 EFIAPI
1352 AhciStartCommand (
1353 IN EFI_PCI_IO_PROTOCOL *PciIo,
1354 IN UINT8 Port,
1355 IN UINT8 CommandSlot,
1356 IN UINT64 Timeout
1357 )
1358 {
1359 UINT32 CmdSlotBit;
1360 EFI_STATUS Status;
1361 UINT32 PortStatus;
1362 UINT32 StartCmd;
1363 UINT32 PortTfd;
1364 UINT32 Offset;
1365 UINT32 Capability;
1366
1367 //
1368 // Collect AHCI controller information
1369 //
1370 Capability = AhciReadReg(PciIo, EFI_AHCI_CAPABILITY_OFFSET);
1371
1372 CmdSlotBit = (UINT32) (1 << CommandSlot);
1373
1374 AhciClearPortStatus (
1375 PciIo,
1376 Port
1377 );
1378
1379 Status = AhciEnableFisReceive (
1380 PciIo,
1381 Port,
1382 Timeout
1383 );
1384
1385 if (EFI_ERROR (Status)) {
1386 return Status;
1387 }
1388
1389 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
1390 PortStatus = AhciReadReg (PciIo, Offset);
1391
1392 StartCmd = 0;
1393 if ((PortStatus & EFI_AHCI_PORT_CMD_ALPE) != 0) {
1394 StartCmd = AhciReadReg (PciIo, Offset);
1395 StartCmd &= ~EFI_AHCI_PORT_CMD_ICC_MASK;
1396 StartCmd |= EFI_AHCI_PORT_CMD_ACTIVE;
1397 }
1398
1399 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
1400 PortTfd = AhciReadReg (PciIo, Offset);
1401
1402 if ((PortTfd & (EFI_AHCI_PORT_TFD_BSY | EFI_AHCI_PORT_TFD_DRQ)) != 0) {
1403 if ((Capability & BIT24) != 0) {
1404 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
1405 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_CLO);
1406
1407 AhciWaitMmioSet (
1408 PciIo,
1409 Offset,
1410 EFI_AHCI_PORT_CMD_CLO,
1411 0,
1412 Timeout
1413 );
1414 }
1415 }
1416
1417 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
1418 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_ST | StartCmd);
1419
1420 //
1421 // Setting the command
1422 //
1423 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CI;
1424 AhciAndReg (PciIo, Offset, 0);
1425 AhciOrReg (PciIo, Offset, CmdSlotBit);
1426
1427 return EFI_SUCCESS;
1428 }
1429
1430
1431 /**
1432 Do AHCI HBA reset.
1433
1434 @param PciIo The PCI IO protocol instance.
1435 @param Timeout The timeout value of reset, uses 100ns as a unit.
1436
1437 @retval EFI_DEVICE_ERROR AHCI controller is failed to complete hardware reset.
1438 @retval EFI_TIMEOUT The reset operation is time out.
1439 @retval EFI_SUCCESS AHCI controller is reset successfully.
1440
1441 **/
1442 EFI_STATUS
1443 EFIAPI
1444 AhciReset (
1445 IN EFI_PCI_IO_PROTOCOL *PciIo,
1446 IN UINT64 Timeout
1447 )
1448 {
1449 UINT64 Delay;
1450 UINT32 Value;
1451
1452 //
1453 // Make sure that GHC.AE bit is set before accessing any AHCI registers.
1454 //
1455 Value = AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET);
1456
1457 if ((Value & EFI_AHCI_GHC_ENABLE) == 0) {
1458 AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);
1459 }
1460
1461 AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_RESET);
1462
1463 Delay = DivU64x32(Timeout, 1000) + 1;
1464
1465 do {
1466 Value = AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET);
1467
1468 if ((Value & EFI_AHCI_GHC_RESET) == 0) {
1469 break;
1470 }
1471
1472 //
1473 // Stall for 100 microseconds.
1474 //
1475 MicroSecondDelay(100);
1476
1477 Delay--;
1478 } while (Delay > 0);
1479
1480 if (Delay == 0) {
1481 return EFI_TIMEOUT;
1482 }
1483
1484 return EFI_SUCCESS;
1485 }
1486
1487 /**
1488 Send SMART Return Status command to check if the execution of SMART cmd is successful or not.
1489
1490 @param PciIo The PCI IO protocol instance.
1491 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
1492 @param Port The number of port.
1493 @param PortMultiplier The port multiplier port number.
1494 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
1495
1496 @retval EFI_SUCCESS Successfully get the return status of S.M.A.R.T command execution.
1497 @retval Others Fail to get return status data.
1498
1499 **/
1500 EFI_STATUS
1501 EFIAPI
1502 AhciAtaSmartReturnStatusCheck (
1503 IN EFI_PCI_IO_PROTOCOL *PciIo,
1504 IN EFI_AHCI_REGISTERS *AhciRegisters,
1505 IN UINT8 Port,
1506 IN UINT8 PortMultiplier,
1507 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
1508 )
1509 {
1510 EFI_STATUS Status;
1511 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
1512 UINT8 LBAMid;
1513 UINT8 LBAHigh;
1514 UINTN FisBaseAddr;
1515 UINT32 Value;
1516
1517 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1518
1519 AtaCommandBlock.AtaCommand = ATA_CMD_SMART;
1520 AtaCommandBlock.AtaFeatures = ATA_SMART_RETURN_STATUS;
1521 AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;
1522 AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;
1523
1524 //
1525 // Send S.M.A.R.T Read Return Status command to device
1526 //
1527 Status = AhciNonDataTransfer (
1528 PciIo,
1529 AhciRegisters,
1530 (UINT8)Port,
1531 (UINT8)PortMultiplier,
1532 NULL,
1533 0,
1534 &AtaCommandBlock,
1535 AtaStatusBlock,
1536 ATA_ATAPI_TIMEOUT,
1537 NULL
1538 );
1539
1540 if (EFI_ERROR (Status)) {
1541 REPORT_STATUS_CODE (
1542 EFI_ERROR_CODE | EFI_ERROR_MINOR,
1543 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_DISABLED)
1544 );
1545 return EFI_DEVICE_ERROR;
1546 }
1547
1548 REPORT_STATUS_CODE (
1549 EFI_PROGRESS_CODE,
1550 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_ENABLE)
1551 );
1552
1553 FisBaseAddr = (UINTN)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);
1554
1555 Value = *(UINT32 *) (FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET);
1556
1557 if ((Value & EFI_AHCI_FIS_TYPE_MASK) == EFI_AHCI_FIS_REGISTER_D2H) {
1558 LBAMid = ((UINT8 *)(UINTN)(FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET))[5];
1559 LBAHigh = ((UINT8 *)(UINTN)(FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET))[6];
1560
1561 if ((LBAMid == 0x4f) && (LBAHigh == 0xc2)) {
1562 //
1563 // The threshold exceeded condition is not detected by the device
1564 //
1565 DEBUG ((EFI_D_INFO, "The S.M.A.R.T threshold exceeded condition is not detected\n"));
1566 REPORT_STATUS_CODE (
1567 EFI_PROGRESS_CODE,
1568 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_UNDERTHRESHOLD)
1569 );
1570 } else if ((LBAMid == 0xf4) && (LBAHigh == 0x2c)) {
1571 //
1572 // The threshold exceeded condition is detected by the device
1573 //
1574 DEBUG ((EFI_D_INFO, "The S.M.A.R.T threshold exceeded condition is detected\n"));
1575 REPORT_STATUS_CODE (
1576 EFI_PROGRESS_CODE,
1577 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_OVERTHRESHOLD)
1578 );
1579 }
1580 }
1581
1582 return EFI_SUCCESS;
1583 }
1584
1585 /**
1586 Enable SMART command of the disk if supported.
1587
1588 @param PciIo The PCI IO protocol instance.
1589 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
1590 @param Port The number of port.
1591 @param PortMultiplier The port multiplier port number.
1592 @param IdentifyData A pointer to data buffer which is used to contain IDENTIFY data.
1593 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
1594
1595 **/
1596 VOID
1597 EFIAPI
1598 AhciAtaSmartSupport (
1599 IN EFI_PCI_IO_PROTOCOL *PciIo,
1600 IN EFI_AHCI_REGISTERS *AhciRegisters,
1601 IN UINT8 Port,
1602 IN UINT8 PortMultiplier,
1603 IN EFI_IDENTIFY_DATA *IdentifyData,
1604 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
1605 )
1606 {
1607 EFI_STATUS Status;
1608 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
1609
1610 //
1611 // Detect if the device supports S.M.A.R.T.
1612 //
1613 if ((IdentifyData->AtaData.command_set_supported_82 & 0x0001) != 0x0001) {
1614 //
1615 // S.M.A.R.T is not supported by the device
1616 //
1617 DEBUG ((EFI_D_INFO, "S.M.A.R.T feature is not supported at port [%d] PortMultiplier [%d]!\n",
1618 Port, PortMultiplier));
1619 REPORT_STATUS_CODE (
1620 EFI_ERROR_CODE | EFI_ERROR_MINOR,
1621 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_NOTSUPPORTED)
1622 );
1623 } else {
1624 //
1625 // Check if the feature is enabled. If not, then enable S.M.A.R.T.
1626 //
1627 if ((IdentifyData->AtaData.command_set_feature_enb_85 & 0x0001) != 0x0001) {
1628
1629 REPORT_STATUS_CODE (
1630 EFI_PROGRESS_CODE,
1631 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_DISABLE)
1632 );
1633
1634 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1635
1636 AtaCommandBlock.AtaCommand = ATA_CMD_SMART;
1637 AtaCommandBlock.AtaFeatures = ATA_SMART_ENABLE_OPERATION;
1638 AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;
1639 AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;
1640
1641 //
1642 // Send S.M.A.R.T Enable command to device
1643 //
1644 Status = AhciNonDataTransfer (
1645 PciIo,
1646 AhciRegisters,
1647 (UINT8)Port,
1648 (UINT8)PortMultiplier,
1649 NULL,
1650 0,
1651 &AtaCommandBlock,
1652 AtaStatusBlock,
1653 ATA_ATAPI_TIMEOUT,
1654 NULL
1655 );
1656
1657
1658 if (!EFI_ERROR (Status)) {
1659 //
1660 // Send S.M.A.R.T AutoSave command to device
1661 //
1662 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1663
1664 AtaCommandBlock.AtaCommand = ATA_CMD_SMART;
1665 AtaCommandBlock.AtaFeatures = 0xD2;
1666 AtaCommandBlock.AtaSectorCount = 0xF1;
1667 AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;
1668 AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;
1669
1670 Status = AhciNonDataTransfer (
1671 PciIo,
1672 AhciRegisters,
1673 (UINT8)Port,
1674 (UINT8)PortMultiplier,
1675 NULL,
1676 0,
1677 &AtaCommandBlock,
1678 AtaStatusBlock,
1679 ATA_ATAPI_TIMEOUT,
1680 NULL
1681 );
1682
1683 if (!EFI_ERROR (Status)) {
1684 Status = AhciAtaSmartReturnStatusCheck (
1685 PciIo,
1686 AhciRegisters,
1687 (UINT8)Port,
1688 (UINT8)PortMultiplier,
1689 AtaStatusBlock
1690 );
1691 }
1692 }
1693 }
1694 DEBUG ((EFI_D_INFO, "Enabled S.M.A.R.T feature at port [%d] PortMultiplier [%d]!\n",
1695 Port, PortMultiplier));
1696 }
1697
1698 return ;
1699 }
1700
1701 /**
1702 Send Buffer cmd to specific device.
1703
1704 @param PciIo The PCI IO protocol instance.
1705 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
1706 @param Port The number of port.
1707 @param PortMultiplier The port multiplier port number.
1708 @param Buffer The data buffer to store IDENTIFY PACKET data.
1709
1710 @retval EFI_DEVICE_ERROR The cmd abort with error occurs.
1711 @retval EFI_TIMEOUT The operation is time out.
1712 @retval EFI_UNSUPPORTED The device is not ready for executing.
1713 @retval EFI_SUCCESS The cmd executes successfully.
1714
1715 **/
1716 EFI_STATUS
1717 EFIAPI
1718 AhciIdentify (
1719 IN EFI_PCI_IO_PROTOCOL *PciIo,
1720 IN EFI_AHCI_REGISTERS *AhciRegisters,
1721 IN UINT8 Port,
1722 IN UINT8 PortMultiplier,
1723 IN OUT EFI_IDENTIFY_DATA *Buffer
1724 )
1725 {
1726 EFI_STATUS Status;
1727 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
1728 EFI_ATA_STATUS_BLOCK AtaStatusBlock;
1729
1730 if (PciIo == NULL || AhciRegisters == NULL || Buffer == NULL) {
1731 return EFI_INVALID_PARAMETER;
1732 }
1733
1734 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1735 ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
1736
1737 AtaCommandBlock.AtaCommand = ATA_CMD_IDENTIFY_DRIVE;
1738 AtaCommandBlock.AtaSectorCount = 1;
1739
1740 Status = AhciPioTransfer (
1741 PciIo,
1742 AhciRegisters,
1743 Port,
1744 PortMultiplier,
1745 NULL,
1746 0,
1747 TRUE,
1748 &AtaCommandBlock,
1749 &AtaStatusBlock,
1750 Buffer,
1751 sizeof (EFI_IDENTIFY_DATA),
1752 ATA_ATAPI_TIMEOUT,
1753 NULL
1754 );
1755
1756 return Status;
1757 }
1758
1759 /**
1760 Send Buffer cmd to specific device.
1761
1762 @param PciIo The PCI IO protocol instance.
1763 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
1764 @param Port The number of port.
1765 @param PortMultiplier The port multiplier port number.
1766 @param Buffer The data buffer to store IDENTIFY PACKET data.
1767
1768 @retval EFI_DEVICE_ERROR The cmd abort with error occurs.
1769 @retval EFI_TIMEOUT The operation is time out.
1770 @retval EFI_UNSUPPORTED The device is not ready for executing.
1771 @retval EFI_SUCCESS The cmd executes successfully.
1772
1773 **/
1774 EFI_STATUS
1775 EFIAPI
1776 AhciIdentifyPacket (
1777 IN EFI_PCI_IO_PROTOCOL *PciIo,
1778 IN EFI_AHCI_REGISTERS *AhciRegisters,
1779 IN UINT8 Port,
1780 IN UINT8 PortMultiplier,
1781 IN OUT EFI_IDENTIFY_DATA *Buffer
1782 )
1783 {
1784 EFI_STATUS Status;
1785 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
1786 EFI_ATA_STATUS_BLOCK AtaStatusBlock;
1787
1788 if (PciIo == NULL || AhciRegisters == NULL) {
1789 return EFI_INVALID_PARAMETER;
1790 }
1791
1792 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1793 ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
1794
1795 AtaCommandBlock.AtaCommand = ATA_CMD_IDENTIFY_DEVICE;
1796 AtaCommandBlock.AtaSectorCount = 1;
1797
1798 Status = AhciPioTransfer (
1799 PciIo,
1800 AhciRegisters,
1801 Port,
1802 PortMultiplier,
1803 NULL,
1804 0,
1805 TRUE,
1806 &AtaCommandBlock,
1807 &AtaStatusBlock,
1808 Buffer,
1809 sizeof (EFI_IDENTIFY_DATA),
1810 ATA_ATAPI_TIMEOUT,
1811 NULL
1812 );
1813
1814 return Status;
1815 }
1816
1817 /**
1818 Send SET FEATURE cmd on specific device.
1819
1820 @param PciIo The PCI IO protocol instance.
1821 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
1822 @param Port The number of port.
1823 @param PortMultiplier The port multiplier port number.
1824 @param Feature The data to send Feature register.
1825 @param FeatureSpecificData The specific data for SET FEATURE cmd.
1826 @param Timeout The timeout value of SET FEATURE cmd, uses 100ns as a unit.
1827
1828 @retval EFI_DEVICE_ERROR The cmd abort with error occurs.
1829 @retval EFI_TIMEOUT The operation is time out.
1830 @retval EFI_UNSUPPORTED The device is not ready for executing.
1831 @retval EFI_SUCCESS The cmd executes successfully.
1832
1833 **/
1834 EFI_STATUS
1835 EFIAPI
1836 AhciDeviceSetFeature (
1837 IN EFI_PCI_IO_PROTOCOL *PciIo,
1838 IN EFI_AHCI_REGISTERS *AhciRegisters,
1839 IN UINT8 Port,
1840 IN UINT8 PortMultiplier,
1841 IN UINT16 Feature,
1842 IN UINT32 FeatureSpecificData,
1843 IN UINT64 Timeout
1844 )
1845 {
1846 EFI_STATUS Status;
1847 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
1848 EFI_ATA_STATUS_BLOCK AtaStatusBlock;
1849
1850 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1851 ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
1852
1853 AtaCommandBlock.AtaCommand = ATA_CMD_SET_FEATURES;
1854 AtaCommandBlock.AtaFeatures = (UINT8) Feature;
1855 AtaCommandBlock.AtaFeaturesExp = (UINT8) (Feature >> 8);
1856 AtaCommandBlock.AtaSectorCount = (UINT8) FeatureSpecificData;
1857 AtaCommandBlock.AtaSectorNumber = (UINT8) (FeatureSpecificData >> 8);
1858 AtaCommandBlock.AtaCylinderLow = (UINT8) (FeatureSpecificData >> 16);
1859 AtaCommandBlock.AtaCylinderHigh = (UINT8) (FeatureSpecificData >> 24);
1860
1861 Status = AhciNonDataTransfer (
1862 PciIo,
1863 AhciRegisters,
1864 (UINT8)Port,
1865 (UINT8)PortMultiplier,
1866 NULL,
1867 0,
1868 &AtaCommandBlock,
1869 &AtaStatusBlock,
1870 Timeout,
1871 NULL
1872 );
1873
1874 return Status;
1875 }
1876
1877 /**
1878 This function is used to send out ATAPI commands conforms to the Packet Command
1879 with PIO Protocol.
1880
1881 @param PciIo The PCI IO protocol instance.
1882 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
1883 @param Port The number of port.
1884 @param PortMultiplier The number of port multiplier.
1885 @param Packet A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET structure.
1886
1887 @retval EFI_SUCCESS send out the ATAPI packet command successfully
1888 and device sends data successfully.
1889 @retval EFI_DEVICE_ERROR the device failed to send data.
1890
1891 **/
1892 EFI_STATUS
1893 EFIAPI
1894 AhciPacketCommandExecute (
1895 IN EFI_PCI_IO_PROTOCOL *PciIo,
1896 IN EFI_AHCI_REGISTERS *AhciRegisters,
1897 IN UINT8 Port,
1898 IN UINT8 PortMultiplier,
1899 IN EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet
1900 )
1901 {
1902 EFI_STATUS Status;
1903 VOID *Buffer;
1904 UINT32 Length;
1905 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
1906 EFI_ATA_STATUS_BLOCK AtaStatusBlock;
1907 BOOLEAN Read;
1908
1909 if (Packet == NULL || Packet->Cdb == NULL) {
1910 return EFI_INVALID_PARAMETER;
1911 }
1912
1913 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1914 ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
1915 AtaCommandBlock.AtaCommand = ATA_CMD_PACKET;
1916 //
1917 // No OVL; No DMA
1918 //
1919 AtaCommandBlock.AtaFeatures = 0x00;
1920 //
1921 // set the transfersize to ATAPI_MAX_BYTE_COUNT to let the device
1922 // determine how many data should be transferred.
1923 //
1924 AtaCommandBlock.AtaCylinderLow = (UINT8) (ATAPI_MAX_BYTE_COUNT & 0x00ff);
1925 AtaCommandBlock.AtaCylinderHigh = (UINT8) (ATAPI_MAX_BYTE_COUNT >> 8);
1926
1927 if (Packet->DataDirection == EFI_EXT_SCSI_DATA_DIRECTION_READ) {
1928 Buffer = Packet->InDataBuffer;
1929 Length = Packet->InTransferLength;
1930 Read = TRUE;
1931 } else {
1932 Buffer = Packet->OutDataBuffer;
1933 Length = Packet->OutTransferLength;
1934 Read = FALSE;
1935 }
1936
1937 if (Length == 0) {
1938 Status = AhciNonDataTransfer (
1939 PciIo,
1940 AhciRegisters,
1941 Port,
1942 PortMultiplier,
1943 Packet->Cdb,
1944 Packet->CdbLength,
1945 &AtaCommandBlock,
1946 &AtaStatusBlock,
1947 Packet->Timeout,
1948 NULL
1949 );
1950 } else {
1951 Status = AhciPioTransfer (
1952 PciIo,
1953 AhciRegisters,
1954 Port,
1955 PortMultiplier,
1956 Packet->Cdb,
1957 Packet->CdbLength,
1958 Read,
1959 &AtaCommandBlock,
1960 &AtaStatusBlock,
1961 Buffer,
1962 Length,
1963 Packet->Timeout,
1964 NULL
1965 );
1966 }
1967 return Status;
1968 }
1969
1970 /**
1971 Allocate transfer-related data struct which is used at AHCI mode.
1972
1973 @param PciIo The PCI IO protocol instance.
1974 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
1975
1976 **/
1977 EFI_STATUS
1978 EFIAPI
1979 AhciCreateTransferDescriptor (
1980 IN EFI_PCI_IO_PROTOCOL *PciIo,
1981 IN OUT EFI_AHCI_REGISTERS *AhciRegisters
1982 )
1983 {
1984 EFI_STATUS Status;
1985 UINTN Bytes;
1986 VOID *Buffer;
1987
1988 UINT32 Capability;
1989 UINT32 PortImplementBitMap;
1990 UINT8 MaxPortNumber;
1991 UINT8 MaxCommandSlotNumber;
1992 BOOLEAN Support64Bit;
1993 UINT64 MaxReceiveFisSize;
1994 UINT64 MaxCommandListSize;
1995 UINT64 MaxCommandTableSize;
1996 EFI_PHYSICAL_ADDRESS AhciRFisPciAddr;
1997 EFI_PHYSICAL_ADDRESS AhciCmdListPciAddr;
1998 EFI_PHYSICAL_ADDRESS AhciCommandTablePciAddr;
1999
2000 Buffer = NULL;
2001 //
2002 // Collect AHCI controller information
2003 //
2004 Capability = AhciReadReg(PciIo, EFI_AHCI_CAPABILITY_OFFSET);
2005 //
2006 // Get the number of command slots per port supported by this HBA.
2007 //
2008 MaxCommandSlotNumber = (UINT8) (((Capability & 0x1F00) >> 8) + 1);
2009 Support64Bit = (BOOLEAN) (((Capability & BIT31) != 0) ? TRUE : FALSE);
2010
2011 PortImplementBitMap = AhciReadReg(PciIo, EFI_AHCI_PI_OFFSET);
2012 //
2013 // Get the highest bit of implemented ports which decides how many bytes are allocated for received FIS.
2014 //
2015 MaxPortNumber = (UINT8)(UINTN)(HighBitSet32(PortImplementBitMap) + 1);
2016 if (MaxPortNumber == 0) {
2017 return EFI_DEVICE_ERROR;
2018 }
2019
2020 MaxReceiveFisSize = MaxPortNumber * sizeof (EFI_AHCI_RECEIVED_FIS);
2021 Status = PciIo->AllocateBuffer (
2022 PciIo,
2023 AllocateAnyPages,
2024 EfiBootServicesData,
2025 EFI_SIZE_TO_PAGES ((UINTN) MaxReceiveFisSize),
2026 &Buffer,
2027 0
2028 );
2029
2030 if (EFI_ERROR (Status)) {
2031 return EFI_OUT_OF_RESOURCES;
2032 }
2033
2034 ZeroMem (Buffer, (UINTN)MaxReceiveFisSize);
2035
2036 AhciRegisters->AhciRFis = Buffer;
2037 AhciRegisters->MaxReceiveFisSize = MaxReceiveFisSize;
2038 Bytes = (UINTN)MaxReceiveFisSize;
2039
2040 Status = PciIo->Map (
2041 PciIo,
2042 EfiPciIoOperationBusMasterCommonBuffer,
2043 Buffer,
2044 &Bytes,
2045 &AhciRFisPciAddr,
2046 &AhciRegisters->MapRFis
2047 );
2048
2049 if (EFI_ERROR (Status) || (Bytes != MaxReceiveFisSize)) {
2050 //
2051 // Map error or unable to map the whole RFis buffer into a contiguous region.
2052 //
2053 Status = EFI_OUT_OF_RESOURCES;
2054 goto Error6;
2055 }
2056
2057 if ((!Support64Bit) && (AhciRFisPciAddr > 0x100000000ULL)) {
2058 //
2059 // The AHCI HBA doesn't support 64bit addressing, so should not get a >4G pci bus master address.
2060 //
2061 Status = EFI_DEVICE_ERROR;
2062 goto Error5;
2063 }
2064 AhciRegisters->AhciRFisPciAddr = (EFI_AHCI_RECEIVED_FIS *)(UINTN)AhciRFisPciAddr;
2065
2066 //
2067 // Allocate memory for command list
2068 // Note that the implementation is a single task model which only use a command list for all ports.
2069 //
2070 Buffer = NULL;
2071 MaxCommandListSize = MaxCommandSlotNumber * sizeof (EFI_AHCI_COMMAND_LIST);
2072 Status = PciIo->AllocateBuffer (
2073 PciIo,
2074 AllocateAnyPages,
2075 EfiBootServicesData,
2076 EFI_SIZE_TO_PAGES ((UINTN) MaxCommandListSize),
2077 &Buffer,
2078 0
2079 );
2080
2081 if (EFI_ERROR (Status)) {
2082 //
2083 // Free mapped resource.
2084 //
2085 Status = EFI_OUT_OF_RESOURCES;
2086 goto Error5;
2087 }
2088
2089 ZeroMem (Buffer, (UINTN)MaxCommandListSize);
2090
2091 AhciRegisters->AhciCmdList = Buffer;
2092 AhciRegisters->MaxCommandListSize = MaxCommandListSize;
2093 Bytes = (UINTN)MaxCommandListSize;
2094
2095 Status = PciIo->Map (
2096 PciIo,
2097 EfiPciIoOperationBusMasterCommonBuffer,
2098 Buffer,
2099 &Bytes,
2100 &AhciCmdListPciAddr,
2101 &AhciRegisters->MapCmdList
2102 );
2103
2104 if (EFI_ERROR (Status) || (Bytes != MaxCommandListSize)) {
2105 //
2106 // Map error or unable to map the whole cmd list buffer into a contiguous region.
2107 //
2108 Status = EFI_OUT_OF_RESOURCES;
2109 goto Error4;
2110 }
2111
2112 if ((!Support64Bit) && (AhciCmdListPciAddr > 0x100000000ULL)) {
2113 //
2114 // The AHCI HBA doesn't support 64bit addressing, so should not get a >4G pci bus master address.
2115 //
2116 Status = EFI_DEVICE_ERROR;
2117 goto Error3;
2118 }
2119 AhciRegisters->AhciCmdListPciAddr = (EFI_AHCI_COMMAND_LIST *)(UINTN)AhciCmdListPciAddr;
2120
2121 //
2122 // Allocate memory for command table
2123 // According to AHCI 1.3 spec, a PRD table can contain maximum 65535 entries.
2124 //
2125 Buffer = NULL;
2126 MaxCommandTableSize = sizeof (EFI_AHCI_COMMAND_TABLE);
2127
2128 Status = PciIo->AllocateBuffer (
2129 PciIo,
2130 AllocateAnyPages,
2131 EfiBootServicesData,
2132 EFI_SIZE_TO_PAGES ((UINTN) MaxCommandTableSize),
2133 &Buffer,
2134 0
2135 );
2136
2137 if (EFI_ERROR (Status)) {
2138 //
2139 // Free mapped resource.
2140 //
2141 Status = EFI_OUT_OF_RESOURCES;
2142 goto Error3;
2143 }
2144
2145 ZeroMem (Buffer, (UINTN)MaxCommandTableSize);
2146
2147 AhciRegisters->AhciCommandTable = Buffer;
2148 AhciRegisters->MaxCommandTableSize = MaxCommandTableSize;
2149 Bytes = (UINTN)MaxCommandTableSize;
2150
2151 Status = PciIo->Map (
2152 PciIo,
2153 EfiPciIoOperationBusMasterCommonBuffer,
2154 Buffer,
2155 &Bytes,
2156 &AhciCommandTablePciAddr,
2157 &AhciRegisters->MapCommandTable
2158 );
2159
2160 if (EFI_ERROR (Status) || (Bytes != MaxCommandTableSize)) {
2161 //
2162 // Map error or unable to map the whole cmd list buffer into a contiguous region.
2163 //
2164 Status = EFI_OUT_OF_RESOURCES;
2165 goto Error2;
2166 }
2167
2168 if ((!Support64Bit) && (AhciCommandTablePciAddr > 0x100000000ULL)) {
2169 //
2170 // The AHCI HBA doesn't support 64bit addressing, so should not get a >4G pci bus master address.
2171 //
2172 Status = EFI_DEVICE_ERROR;
2173 goto Error1;
2174 }
2175 AhciRegisters->AhciCommandTablePciAddr = (EFI_AHCI_COMMAND_TABLE *)(UINTN)AhciCommandTablePciAddr;
2176
2177 return EFI_SUCCESS;
2178 //
2179 // Map error or unable to map the whole CmdList buffer into a contiguous region.
2180 //
2181 Error1:
2182 PciIo->Unmap (
2183 PciIo,
2184 AhciRegisters->MapCommandTable
2185 );
2186 Error2:
2187 PciIo->FreeBuffer (
2188 PciIo,
2189 EFI_SIZE_TO_PAGES ((UINTN) MaxCommandTableSize),
2190 AhciRegisters->AhciCommandTable
2191 );
2192 Error3:
2193 PciIo->Unmap (
2194 PciIo,
2195 AhciRegisters->MapCmdList
2196 );
2197 Error4:
2198 PciIo->FreeBuffer (
2199 PciIo,
2200 EFI_SIZE_TO_PAGES ((UINTN) MaxCommandListSize),
2201 AhciRegisters->AhciCmdList
2202 );
2203 Error5:
2204 PciIo->Unmap (
2205 PciIo,
2206 AhciRegisters->MapRFis
2207 );
2208 Error6:
2209 PciIo->FreeBuffer (
2210 PciIo,
2211 EFI_SIZE_TO_PAGES ((UINTN) MaxReceiveFisSize),
2212 AhciRegisters->AhciRFis
2213 );
2214
2215 return Status;
2216 }
2217
2218 /**
2219 Read logs from SATA device.
2220
2221 @param PciIo The PCI IO protocol instance.
2222 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
2223 @param Port The number of port.
2224 @param PortMultiplier The multiplier of port.
2225 @param Buffer The data buffer to store SATA logs.
2226 @param LogNumber The address of the log.
2227 @param PageNumber The page number of the log.
2228
2229 @retval EFI_INVALID_PARAMETER PciIo, AhciRegisters or Buffer is NULL.
2230 @retval others Return status of AhciPioTransfer().
2231 **/
2232 EFI_STATUS
2233 AhciReadLogExt (
2234 IN EFI_PCI_IO_PROTOCOL *PciIo,
2235 IN EFI_AHCI_REGISTERS *AhciRegisters,
2236 IN UINT8 Port,
2237 IN UINT8 PortMultiplier,
2238 IN OUT UINT8 *Buffer,
2239 IN UINT8 LogNumber,
2240 IN UINT8 PageNumber
2241 )
2242 {
2243 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
2244 EFI_ATA_STATUS_BLOCK AtaStatusBlock;
2245
2246 if (PciIo == NULL || AhciRegisters == NULL || Buffer == NULL) {
2247 return EFI_INVALID_PARAMETER;
2248 }
2249
2250 ///
2251 /// Read log from device
2252 ///
2253 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
2254 ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
2255 ZeroMem (Buffer, 512);
2256
2257 AtaCommandBlock.AtaCommand = ATA_CMD_READ_LOG_EXT;
2258 AtaCommandBlock.AtaSectorCount = 1;
2259 AtaCommandBlock.AtaSectorNumber = LogNumber;
2260 AtaCommandBlock.AtaCylinderLow = PageNumber;
2261
2262 return AhciPioTransfer (
2263 PciIo,
2264 AhciRegisters,
2265 Port,
2266 PortMultiplier,
2267 NULL,
2268 0,
2269 TRUE,
2270 &AtaCommandBlock,
2271 &AtaStatusBlock,
2272 Buffer,
2273 512,
2274 ATA_ATAPI_TIMEOUT,
2275 NULL
2276 );
2277 }
2278
2279 /**
2280 Enable DEVSLP of the disk if supported.
2281
2282 @param PciIo The PCI IO protocol instance.
2283 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
2284 @param Port The number of port.
2285 @param PortMultiplier The multiplier of port.
2286 @param IdentifyData A pointer to data buffer which is used to contain IDENTIFY data.
2287
2288 @retval EFI_SUCCESS The DEVSLP is enabled per policy successfully.
2289 @retval EFI_UNSUPPORTED The DEVSLP isn't supported by the controller/device and policy requires to enable it.
2290 **/
2291 EFI_STATUS
2292 AhciEnableDevSlp (
2293 IN EFI_PCI_IO_PROTOCOL *PciIo,
2294 IN EFI_AHCI_REGISTERS *AhciRegisters,
2295 IN UINT8 Port,
2296 IN UINT8 PortMultiplier,
2297 IN EFI_IDENTIFY_DATA *IdentifyData
2298 )
2299 {
2300 EFI_STATUS Status;
2301 UINT32 Offset;
2302 UINT32 Capability2;
2303 UINT8 LogData[512];
2304 DEVSLP_TIMING_VARIABLES DevSlpTiming;
2305 UINT32 PortCmd;
2306 UINT32 PortDevSlp;
2307
2308 if (mAtaAtapiPolicy->DeviceSleepEnable != 1) {
2309 return EFI_SUCCESS;
2310 }
2311
2312 //
2313 // Do not enable DevSlp if DevSlp is not supported.
2314 //
2315 Capability2 = AhciReadReg (PciIo, AHCI_CAPABILITY2_OFFSET);
2316 DEBUG ((DEBUG_INFO, "AHCI CAPABILITY2 = %08x\n", Capability2));
2317 if ((Capability2 & AHCI_CAP2_SDS) == 0) {
2318 return EFI_UNSUPPORTED;
2319 }
2320
2321 //
2322 // Do not enable DevSlp if DevSlp is not present
2323 // Do not enable DevSlp if Hot Plug or Mechanical Presence Switch is supported
2324 //
2325 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH;
2326 PortCmd = AhciReadReg (PciIo, Offset + EFI_AHCI_PORT_CMD);
2327 PortDevSlp = AhciReadReg (PciIo, Offset + AHCI_PORT_DEVSLP);
2328 DEBUG ((DEBUG_INFO, "Port CMD/DEVSLP = %08x / %08x\n", PortCmd, PortDevSlp));
2329 if (((PortDevSlp & AHCI_PORT_DEVSLP_DSP) == 0) ||
2330 ((PortCmd & (EFI_AHCI_PORT_CMD_HPCP | EFI_AHCI_PORT_CMD_MPSP)) != 0)
2331 ) {
2332 return EFI_UNSUPPORTED;
2333 }
2334
2335 //
2336 // Do not enable DevSlp if the device doesn't support DevSlp
2337 //
2338 DEBUG ((DEBUG_INFO, "IDENTIFY DEVICE: [77] = %04x, [78] = %04x, [79] = %04x\n",
2339 IdentifyData->AtaData.reserved_77,
2340 IdentifyData->AtaData.serial_ata_features_supported, IdentifyData->AtaData.serial_ata_features_enabled));
2341 if ((IdentifyData->AtaData.serial_ata_features_supported & BIT8) == 0) {
2342 DEBUG ((DEBUG_INFO, "DevSlp feature is not supported for device at port [%d] PortMultiplier [%d]!\n",
2343 Port, PortMultiplier));
2344 return EFI_UNSUPPORTED;
2345 }
2346
2347 //
2348 // Enable DevSlp when it is not enabled.
2349 //
2350 if ((IdentifyData->AtaData.serial_ata_features_enabled & BIT8) != 0) {
2351 Status = AhciDeviceSetFeature (
2352 PciIo, AhciRegisters, Port, 0, ATA_SUB_CMD_ENABLE_SATA_FEATURE, 0x09, ATA_ATAPI_TIMEOUT
2353 );
2354 DEBUG ((DEBUG_INFO, "DevSlp set feature for device at port [%d] PortMultiplier [%d] - %r\n",
2355 Port, PortMultiplier, Status));
2356 if (EFI_ERROR (Status)) {
2357 return Status;
2358 }
2359 }
2360
2361 Status = AhciReadLogExt(PciIo, AhciRegisters, Port, PortMultiplier, LogData, 0x30, 0x08);
2362
2363 //
2364 // Clear PxCMD.ST and PxDEVSLP.ADSE before updating PxDEVSLP.DITO and PxDEVSLP.MDAT.
2365 //
2366 AhciWriteReg (PciIo, Offset + EFI_AHCI_PORT_CMD, PortCmd & ~EFI_AHCI_PORT_CMD_ST);
2367 PortDevSlp &= ~AHCI_PORT_DEVSLP_ADSE;
2368 AhciWriteReg (PciIo, Offset + AHCI_PORT_DEVSLP, PortDevSlp);
2369
2370 //
2371 // Set PxDEVSLP.DETO and PxDEVSLP.MDAT to 0.
2372 //
2373 PortDevSlp &= ~AHCI_PORT_DEVSLP_DETO_MASK;
2374 PortDevSlp &= ~AHCI_PORT_DEVSLP_MDAT_MASK;
2375 AhciWriteReg (PciIo, Offset + AHCI_PORT_DEVSLP, PortDevSlp);
2376 DEBUG ((DEBUG_INFO, "Read Log Ext at port [%d] PortMultiplier [%d] - %r\n", Port, PortMultiplier, Status));
2377 if (EFI_ERROR (Status)) {
2378 //
2379 // Assume DEVSLP TIMING VARIABLES is not supported if the Identify Device Data log (30h, 8) fails
2380 //
2381 ZeroMem (&DevSlpTiming, sizeof (DevSlpTiming));
2382 } else {
2383 CopyMem (&DevSlpTiming, &LogData[48], sizeof (DevSlpTiming));
2384 DEBUG ((DEBUG_INFO, "DevSlpTiming: Supported(%d), Deto(%d), Madt(%d)\n",
2385 DevSlpTiming.Supported, DevSlpTiming.Deto, DevSlpTiming.Madt));
2386 }
2387
2388 //
2389 // Use 20ms as default DETO when DEVSLP TIMING VARIABLES is not supported or the DETO is 0.
2390 //
2391 if ((DevSlpTiming.Supported == 0) || (DevSlpTiming.Deto == 0)) {
2392 DevSlpTiming.Deto = 20;
2393 }
2394
2395 //
2396 // Use 10ms as default MADT when DEVSLP TIMING VARIABLES is not supported or the MADT is 0.
2397 //
2398 if ((DevSlpTiming.Supported == 0) || (DevSlpTiming.Madt == 0)) {
2399 DevSlpTiming.Madt = 10;
2400 }
2401
2402 PortDevSlp |= DevSlpTiming.Deto << 2;
2403 PortDevSlp |= DevSlpTiming.Madt << 10;
2404 AhciOrReg (PciIo, Offset + AHCI_PORT_DEVSLP, PortDevSlp);
2405
2406 if (mAtaAtapiPolicy->AggressiveDeviceSleepEnable == 1) {
2407 if ((Capability2 & AHCI_CAP2_SADM) != 0) {
2408 PortDevSlp &= ~AHCI_PORT_DEVSLP_DITO_MASK;
2409 PortDevSlp |= (625 << 15);
2410 AhciWriteReg (PciIo, Offset + AHCI_PORT_DEVSLP, PortDevSlp);
2411
2412 PortDevSlp |= AHCI_PORT_DEVSLP_ADSE;
2413 AhciWriteReg (PciIo, Offset + AHCI_PORT_DEVSLP, PortDevSlp);
2414 }
2415 }
2416
2417
2418 AhciWriteReg (PciIo, Offset + EFI_AHCI_PORT_CMD, PortCmd);
2419
2420 DEBUG ((DEBUG_INFO, "Enabled DevSlp feature at port [%d] PortMultiplier [%d], Port CMD/DEVSLP = %08x / %08x\n",
2421 Port, PortMultiplier, PortCmd, PortDevSlp));
2422
2423 return EFI_SUCCESS;
2424 }
2425
2426 /**
2427 Spin-up disk if IDD was incomplete or PUIS feature is enabled
2428
2429 @param PciIo The PCI IO protocol instance.
2430 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
2431 @param Port The number of port.
2432 @param PortMultiplier The multiplier of port.
2433 @param IdentifyData A pointer to data buffer which is used to contain IDENTIFY data.
2434
2435 **/
2436 EFI_STATUS
2437 AhciSpinUpDisk (
2438 IN EFI_PCI_IO_PROTOCOL *PciIo,
2439 IN EFI_AHCI_REGISTERS *AhciRegisters,
2440 IN UINT8 Port,
2441 IN UINT8 PortMultiplier,
2442 IN OUT EFI_IDENTIFY_DATA *IdentifyData
2443 )
2444 {
2445 EFI_STATUS Status;
2446 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
2447 EFI_ATA_STATUS_BLOCK AtaStatusBlock;
2448 UINT8 Buffer[512];
2449
2450 if (IdentifyData->AtaData.specific_config == ATA_SPINUP_CFG_REQUIRED_IDD_INCOMPLETE) {
2451 //
2452 // Use SET_FEATURE subcommand to spin up the device.
2453 //
2454 Status = AhciDeviceSetFeature (
2455 PciIo, AhciRegisters, Port, PortMultiplier,
2456 ATA_SUB_CMD_PUIS_SET_DEVICE_SPINUP, 0x00, ATA_SPINUP_TIMEOUT
2457 );
2458 DEBUG ((DEBUG_INFO, "CMD_PUIS_SET_DEVICE_SPINUP for device at port [%d] PortMultiplier [%d] - %r!\n",
2459 Port, PortMultiplier, Status));
2460 if (EFI_ERROR (Status)) {
2461 return Status;
2462 }
2463 } else {
2464 ASSERT (IdentifyData->AtaData.specific_config == ATA_SPINUP_CFG_NOT_REQUIRED_IDD_INCOMPLETE);
2465
2466 //
2467 // Use READ_SECTORS to spin up the device if SpinUp SET FEATURE subcommand is not supported
2468 //
2469 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
2470 ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
2471 //
2472 // Perform READ SECTORS PIO Data-In command to Read LBA 0
2473 //
2474 AtaCommandBlock.AtaCommand = ATA_CMD_READ_SECTORS;
2475 AtaCommandBlock.AtaSectorCount = 0x1;
2476
2477 Status = AhciPioTransfer (
2478 PciIo,
2479 AhciRegisters,
2480 Port,
2481 PortMultiplier,
2482 NULL,
2483 0,
2484 TRUE,
2485 &AtaCommandBlock,
2486 &AtaStatusBlock,
2487 &Buffer,
2488 sizeof (Buffer),
2489 ATA_SPINUP_TIMEOUT,
2490 NULL
2491 );
2492 DEBUG ((DEBUG_INFO, "Read LBA 0 for device at port [%d] PortMultiplier [%d] - %r!\n",
2493 Port, PortMultiplier, Status));
2494 if (EFI_ERROR (Status)) {
2495 return Status;
2496 }
2497 }
2498
2499 //
2500 // Read the complete IDENTIFY DEVICE data.
2501 //
2502 ZeroMem (IdentifyData, sizeof (*IdentifyData));
2503 Status = AhciIdentify (PciIo, AhciRegisters, Port, PortMultiplier, IdentifyData);
2504 if (EFI_ERROR (Status)) {
2505 DEBUG ((DEBUG_ERROR, "Read IDD failed for device at port [%d] PortMultiplier [%d] - %r!\n",
2506 Port, PortMultiplier, Status));
2507 return Status;
2508 }
2509
2510 DEBUG ((DEBUG_INFO, "IDENTIFY DEVICE: [0] = %016x, [2] = %016x, [83] = %016x, [86] = %016x\n",
2511 IdentifyData->AtaData.config, IdentifyData->AtaData.specific_config,
2512 IdentifyData->AtaData.command_set_supported_83, IdentifyData->AtaData.command_set_feature_enb_86));
2513 //
2514 // Check if IDD is incomplete
2515 //
2516 if ((IdentifyData->AtaData.config & BIT2) != 0) {
2517 return EFI_DEVICE_ERROR;
2518 }
2519
2520 return EFI_SUCCESS;
2521 }
2522
2523 /**
2524 Enable/disable/skip PUIS of the disk according to policy.
2525
2526 @param PciIo The PCI IO protocol instance.
2527 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
2528 @param Port The number of port.
2529 @param PortMultiplier The multiplier of port.
2530
2531 **/
2532 EFI_STATUS
2533 AhciPuisEnable (
2534 IN EFI_PCI_IO_PROTOCOL *PciIo,
2535 IN EFI_AHCI_REGISTERS *AhciRegisters,
2536 IN UINT8 Port,
2537 IN UINT8 PortMultiplier
2538 )
2539 {
2540 EFI_STATUS Status;
2541
2542 Status = EFI_SUCCESS;
2543 if (mAtaAtapiPolicy->PuisEnable == 0) {
2544 Status = AhciDeviceSetFeature (PciIo, AhciRegisters, Port, PortMultiplier, ATA_SUB_CMD_DISABLE_PUIS, 0x00, ATA_ATAPI_TIMEOUT);
2545 } else if (mAtaAtapiPolicy->PuisEnable == 1) {
2546 Status = AhciDeviceSetFeature (PciIo, AhciRegisters, Port, PortMultiplier, ATA_SUB_CMD_ENABLE_PUIS, 0x00, ATA_ATAPI_TIMEOUT);
2547 }
2548 DEBUG ((DEBUG_INFO, "%a PUIS feature at port [%d] PortMultiplier [%d] - %r!\n",
2549 (mAtaAtapiPolicy->PuisEnable == 0) ? "Disable" : (
2550 (mAtaAtapiPolicy->PuisEnable == 1) ? "Enable" : "Skip"
2551 ), Port, PortMultiplier, Status));
2552 return Status;
2553 }
2554
2555 /**
2556 Initialize ATA host controller at AHCI mode.
2557
2558 The function is designed to initialize ATA host controller.
2559
2560 @param[in] Instance A pointer to the ATA_ATAPI_PASS_THRU_INSTANCE instance.
2561
2562 **/
2563 EFI_STATUS
2564 EFIAPI
2565 AhciModeInitialization (
2566 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance
2567 )
2568 {
2569 EFI_STATUS Status;
2570 EFI_PCI_IO_PROTOCOL *PciIo;
2571 EFI_IDE_CONTROLLER_INIT_PROTOCOL *IdeInit;
2572 UINT32 Capability;
2573 UINT8 MaxPortNumber;
2574 UINT32 PortImplementBitMap;
2575
2576 EFI_AHCI_REGISTERS *AhciRegisters;
2577
2578 UINT8 Port;
2579 DATA_64 Data64;
2580 UINT32 Offset;
2581 UINT32 Data;
2582 EFI_IDENTIFY_DATA Buffer;
2583 EFI_ATA_DEVICE_TYPE DeviceType;
2584 EFI_ATA_COLLECTIVE_MODE *SupportedModes;
2585 EFI_ATA_TRANSFER_MODE TransferMode;
2586 UINT32 PhyDetectDelay;
2587 UINT32 Value;
2588
2589 if (Instance == NULL) {
2590 return EFI_INVALID_PARAMETER;
2591 }
2592
2593 PciIo = Instance->PciIo;
2594 IdeInit = Instance->IdeControllerInit;
2595
2596 Status = AhciReset (PciIo, EFI_AHCI_BUS_RESET_TIMEOUT);
2597
2598 if (EFI_ERROR (Status)) {
2599 return EFI_DEVICE_ERROR;
2600 }
2601
2602 //
2603 // Collect AHCI controller information
2604 //
2605 Capability = AhciReadReg (PciIo, EFI_AHCI_CAPABILITY_OFFSET);
2606
2607 //
2608 // Make sure that GHC.AE bit is set before accessing any AHCI registers.
2609 //
2610 Value = AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET);
2611
2612 if ((Value & EFI_AHCI_GHC_ENABLE) == 0) {
2613 AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);
2614 }
2615
2616 //
2617 // Enable 64-bit DMA support in the PCI layer if this controller
2618 // supports it.
2619 //
2620 if ((Capability & EFI_AHCI_CAP_S64A) != 0) {
2621 Status = PciIo->Attributes (
2622 PciIo,
2623 EfiPciIoAttributeOperationEnable,
2624 EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE,
2625 NULL
2626 );
2627 if (EFI_ERROR (Status)) {
2628 DEBUG ((EFI_D_WARN,
2629 "AhciModeInitialization: failed to enable 64-bit DMA on 64-bit capable controller (%r)\n",
2630 Status));
2631 }
2632 }
2633
2634 //
2635 // Get the number of command slots per port supported by this HBA.
2636 //
2637 MaxPortNumber = (UINT8) ((Capability & 0x1F) + 1);
2638
2639 //
2640 // Get the bit map of those ports exposed by this HBA.
2641 // It indicates which ports that the HBA supports are available for software to use.
2642 //
2643 PortImplementBitMap = AhciReadReg(PciIo, EFI_AHCI_PI_OFFSET);
2644
2645 AhciRegisters = &Instance->AhciRegisters;
2646 Status = AhciCreateTransferDescriptor (PciIo, AhciRegisters);
2647
2648 if (EFI_ERROR (Status)) {
2649 return EFI_OUT_OF_RESOURCES;
2650 }
2651
2652 for (Port = 0; Port < EFI_AHCI_MAX_PORTS; Port ++) {
2653 if ((PortImplementBitMap & (((UINT32)BIT0) << Port)) != 0) {
2654 //
2655 // According to AHCI spec, MaxPortNumber should be equal or greater than the number of implemented ports.
2656 //
2657 if ((MaxPortNumber--) == 0) {
2658 //
2659 // Should never be here.
2660 //
2661 ASSERT (FALSE);
2662 return EFI_SUCCESS;
2663 }
2664
2665 IdeInit->NotifyPhase (IdeInit, EfiIdeBeforeChannelEnumeration, Port);
2666
2667 //
2668 // Initialize FIS Base Address Register and Command List Base Address Register for use.
2669 //
2670 Data64.Uint64 = (UINTN) (AhciRegisters->AhciRFisPciAddr) + sizeof (EFI_AHCI_RECEIVED_FIS) * Port;
2671 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_FB;
2672 AhciWriteReg (PciIo, Offset, Data64.Uint32.Lower32);
2673 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_FBU;
2674 AhciWriteReg (PciIo, Offset, Data64.Uint32.Upper32);
2675
2676 Data64.Uint64 = (UINTN) (AhciRegisters->AhciCmdListPciAddr);
2677 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CLB;
2678 AhciWriteReg (PciIo, Offset, Data64.Uint32.Lower32);
2679 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CLBU;
2680 AhciWriteReg (PciIo, Offset, Data64.Uint32.Upper32);
2681
2682 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
2683 Data = AhciReadReg (PciIo, Offset);
2684 if ((Data & EFI_AHCI_PORT_CMD_CPD) != 0) {
2685 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_POD);
2686 }
2687
2688 if ((Capability & EFI_AHCI_CAP_SSS) != 0) {
2689 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_SUD);
2690 }
2691
2692 //
2693 // Disable aggressive power management.
2694 //
2695 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SCTL;
2696 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_SCTL_IPM_INIT);
2697 //
2698 // Disable the reporting of the corresponding interrupt to system software.
2699 //
2700 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_IE;
2701 AhciAndReg (PciIo, Offset, 0);
2702
2703 //
2704 // Now inform the IDE Controller Init Module.
2705 //
2706 IdeInit->NotifyPhase (IdeInit, EfiIdeBusBeforeDevicePresenceDetection, Port);
2707
2708 //
2709 // Enable FIS Receive DMA engine for the first D2H FIS.
2710 //
2711 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
2712 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_FRE);
2713
2714 //
2715 // Wait for the Phy to detect the presence of a device.
2716 //
2717 PhyDetectDelay = EFI_AHCI_BUS_PHY_DETECT_TIMEOUT;
2718 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SSTS;
2719 do {
2720 Data = AhciReadReg (PciIo, Offset) & EFI_AHCI_PORT_SSTS_DET_MASK;
2721 if ((Data == EFI_AHCI_PORT_SSTS_DET_PCE) || (Data == EFI_AHCI_PORT_SSTS_DET)) {
2722 break;
2723 }
2724
2725 MicroSecondDelay (1000);
2726 PhyDetectDelay--;
2727 } while (PhyDetectDelay > 0);
2728
2729 if (PhyDetectDelay == 0) {
2730 //
2731 // No device detected at this port.
2732 // Clear PxCMD.SUD for those ports at which there are no device present.
2733 //
2734 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
2735 AhciAndReg (PciIo, Offset, (UINT32) ~(EFI_AHCI_PORT_CMD_SUD));
2736 continue;
2737 }
2738
2739 Status = AhciWaitDeviceReady (PciIo, Port);
2740 if (EFI_ERROR (Status)) {
2741 continue;
2742 }
2743
2744 //
2745 // When the first D2H register FIS is received, the content of PxSIG register is updated.
2746 //
2747 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SIG;
2748 Status = AhciWaitMmioSet (
2749 PciIo,
2750 Offset,
2751 0x0000FFFF,
2752 0x00000101,
2753 EFI_TIMER_PERIOD_SECONDS(16)
2754 );
2755 if (EFI_ERROR (Status)) {
2756 continue;
2757 }
2758
2759 Data = AhciReadReg (PciIo, Offset);
2760 if ((Data & EFI_AHCI_ATAPI_SIG_MASK) == EFI_AHCI_ATAPI_DEVICE_SIG) {
2761 Status = AhciIdentifyPacket (PciIo, AhciRegisters, Port, 0, &Buffer);
2762
2763 if (EFI_ERROR (Status)) {
2764 continue;
2765 }
2766
2767 DeviceType = EfiIdeCdrom;
2768 } else if ((Data & EFI_AHCI_ATAPI_SIG_MASK) == EFI_AHCI_ATA_DEVICE_SIG) {
2769 Status = AhciIdentify (PciIo, AhciRegisters, Port, 0, &Buffer);
2770
2771 if (EFI_ERROR (Status)) {
2772 REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_EC_NOT_DETECTED));
2773 continue;
2774 }
2775
2776 DEBUG ((
2777 DEBUG_INFO, "IDENTIFY DEVICE: [0] = %016x, [2] = %016x, [83] = %016x, [86] = %016x\n",
2778 Buffer.AtaData.config, Buffer.AtaData.specific_config,
2779 Buffer.AtaData.command_set_supported_83, Buffer.AtaData.command_set_feature_enb_86
2780 ));
2781 if ((Buffer.AtaData.config & BIT2) != 0) {
2782 //
2783 // SpinUp disk if device reported incomplete IDENTIFY DEVICE.
2784 //
2785 Status = AhciSpinUpDisk (
2786 PciIo,
2787 AhciRegisters,
2788 Port,
2789 0,
2790 &Buffer
2791 );
2792 if (EFI_ERROR (Status)) {
2793 DEBUG ((DEBUG_ERROR, "Spin up standby device failed - %r\n", Status));
2794 continue;
2795 }
2796 }
2797
2798 DeviceType = EfiIdeHarddisk;
2799 } else {
2800 continue;
2801 }
2802 DEBUG ((DEBUG_INFO, "port [%d] port multitplier [%d] has a [%a]\n",
2803 Port, 0, DeviceType == EfiIdeCdrom ? "cdrom" : "harddisk"));
2804
2805 //
2806 // If the device is a hard disk, then try to enable S.M.A.R.T feature
2807 //
2808 if ((DeviceType == EfiIdeHarddisk) && PcdGetBool (PcdAtaSmartEnable)) {
2809 AhciAtaSmartSupport (
2810 PciIo,
2811 AhciRegisters,
2812 Port,
2813 0,
2814 &Buffer,
2815 NULL
2816 );
2817 }
2818
2819 //
2820 // Submit identify data to IDE controller init driver
2821 //
2822 IdeInit->SubmitData (IdeInit, Port, 0, &Buffer);
2823
2824 //
2825 // Now start to config ide device parameter and transfer mode.
2826 //
2827 Status = IdeInit->CalculateMode (
2828 IdeInit,
2829 Port,
2830 0,
2831 &SupportedModes
2832 );
2833 if (EFI_ERROR (Status)) {
2834 DEBUG ((EFI_D_ERROR, "Calculate Mode Fail, Status = %r\n", Status));
2835 continue;
2836 }
2837
2838 //
2839 // Set best supported PIO mode on this IDE device
2840 //
2841 if (SupportedModes->PioMode.Mode <= EfiAtaPioMode2) {
2842 TransferMode.ModeCategory = EFI_ATA_MODE_DEFAULT_PIO;
2843 } else {
2844 TransferMode.ModeCategory = EFI_ATA_MODE_FLOW_PIO;
2845 }
2846
2847 TransferMode.ModeNumber = (UINT8) (SupportedModes->PioMode.Mode);
2848
2849 //
2850 // Set supported DMA mode on this IDE device. Note that UDMA & MDMA can't
2851 // be set together. Only one DMA mode can be set to a device. If setting
2852 // DMA mode operation fails, we can continue moving on because we only use
2853 // PIO mode at boot time. DMA modes are used by certain kind of OS booting
2854 //
2855 if (SupportedModes->UdmaMode.Valid) {
2856 TransferMode.ModeCategory = EFI_ATA_MODE_UDMA;
2857 TransferMode.ModeNumber = (UINT8) (SupportedModes->UdmaMode.Mode);
2858 } else if (SupportedModes->MultiWordDmaMode.Valid) {
2859 TransferMode.ModeCategory = EFI_ATA_MODE_MDMA;
2860 TransferMode.ModeNumber = (UINT8) SupportedModes->MultiWordDmaMode.Mode;
2861 }
2862
2863 Status = AhciDeviceSetFeature (PciIo, AhciRegisters, Port, 0, 0x03, (UINT32)(*(UINT8 *)&TransferMode), ATA_ATAPI_TIMEOUT);
2864 if (EFI_ERROR (Status)) {
2865 DEBUG ((EFI_D_ERROR, "Set transfer Mode Fail, Status = %r\n", Status));
2866 continue;
2867 }
2868
2869 //
2870 // Found a ATA or ATAPI device, add it into the device list.
2871 //
2872 CreateNewDeviceInfo (Instance, Port, 0xFFFF, DeviceType, &Buffer);
2873 if (DeviceType == EfiIdeHarddisk) {
2874 REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_PC_ENABLE));
2875 AhciEnableDevSlp (
2876 PciIo,
2877 AhciRegisters,
2878 Port,
2879 0,
2880 &Buffer
2881 );
2882 }
2883
2884 //
2885 // Enable/disable PUIS according to policy setting if PUIS is capable (Word[83].BIT5 is set).
2886 //
2887 if ((Buffer.AtaData.command_set_supported_83 & BIT5) != 0) {
2888 Status = AhciPuisEnable (
2889 PciIo,
2890 AhciRegisters,
2891 Port,
2892 0
2893 );
2894 if (EFI_ERROR (Status)) {
2895 DEBUG ((DEBUG_ERROR, "PUIS enable/disable failed, Status = %r\n", Status));
2896 continue;
2897 }
2898 }
2899 }
2900 }
2901
2902 return EFI_SUCCESS;
2903 }
2904
EFI Development Kit II mirror for PVE