3 Copyright (c) 2007, Intel Corporation
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 This file contains URB request, each request is warpped in a
19 URB (Usb Request Block)
25 #ifndef _EFI_EHCI_URB_H_
26 #define _EFI_EHCI_URB_H_
29 typedef struct _EHC_QTD EHC_QTD
;
30 typedef struct _EHC_QH EHC_QH
;
31 typedef struct _URB URB
;
35 // Transfer types, used in URB to identify the transfer type
37 EHC_CTRL_TRANSFER
= 0x01,
38 EHC_BULK_TRANSFER
= 0x02,
39 EHC_INT_TRANSFER_SYNC
= 0x04,
40 EHC_INT_TRANSFER_ASYNC
= 0x08,
42 EHC_QTD_SIG
= EFI_SIGNATURE_32 ('U', 'S', 'B', 'T'),
43 EHC_QH_SIG
= EFI_SIGNATURE_32 ('U', 'S', 'B', 'H'),
44 EHC_URB_SIG
= EFI_SIGNATURE_32 ('U', 'S', 'B', 'R'),
47 // Hardware related bit definitions
58 QTD_PID_OUTPUT
= 0x00,
64 QTD_STAT_DO_PING
= 0x01,
65 QTD_STAT_DO_CS
= 0x02,
66 QTD_STAT_TRANS_ERR
= 0x08,
67 QTD_STAT_BABBLE_ERR
= 0x10,
68 QTD_STAT_BUFF_ERR
= 0x20,
69 QTD_STAT_HALTED
= 0x40,
70 QTD_STAT_ACTIVE
= 0x80,
71 QTD_STAT_ERR_MASK
= QTD_STAT_TRANS_ERR
| QTD_STAT_BABBLE_ERR
| QTD_STAT_BUFF_ERR
,
75 QTD_BUF_MASK
= 0x0FFF,
77 QH_MICROFRAME_0
= 0x01,
78 QH_MICROFRAME_1
= 0x02,
79 QH_MICROFRAME_2
= 0x04,
80 QH_MICROFRAME_3
= 0x08,
81 QH_MICROFRAME_4
= 0x10,
82 QH_MICROFRAME_5
= 0x20,
83 QH_MICROFRAME_6
= 0x40,
84 QH_MICROFRAME_7
= 0x80,
86 USB_ERR_SHORT_PACKET
= 0x200
90 // Fill in the hardware link point: pass in a EHC_QH/QH_HW
91 // pointer to QH_LINK; A EHC_QTD/QTD_HW pointer to QTD_LINK
93 #define QH_LINK(Addr, Type, Term) \
94 ((UINT32) ((EHC_LOW_32BIT (Addr) & 0xFFFFFFE0) | (Type) | ((Term) ? 1 : 0)))
96 #define QTD_LINK(Addr, Term) QH_LINK((Addr), 0, (Term))
99 // The defination of EHCI hardware used data structure for
100 // little endian architecture. The QTD and QH structures
101 // are required to be 32 bytes aligned. Don't add members
102 // to the head of the associated software strucuture.
114 UINT32 TotalBytes
: 15;
115 UINT32 DataToggle
: 1;
124 // Endpoint capabilities/Characteristics DWord 1 and DWord 2
126 UINT32 DeviceAddr
: 7;
131 UINT32 ReclaimHead
: 1;
132 UINT32 MaxPacketLen
: 11;
134 UINT32 NakReload
: 4;
140 UINT32 Multiplier
: 2;
143 // Transaction execution overlay area
154 UINT32 TotalBytes
: 15;
155 UINT32 DataToggle
: 1;
164 // Endpoint address and its capabilities
166 typedef struct _USB_ENDPOINT
{
168 UINT8 EpAddr
; // Endpoint address, no direction encoded in
169 EFI_USB_DATA_DIRECTION Direction
;
174 UINT8 Toggle
; // Data toggle, not used for control transfer
176 UINTN PollRate
; // Polling interval used by EHCI
180 // Software QTD strcture, this is used to manage all the
181 // QTD generated from a URB. Don't add fields before QtdHw.
186 LIST_ENTRY QtdList
; // The list of QTDs to one end point
187 UINT8
*Data
; // Buffer of the original data
188 UINTN DataLen
; // Original amount of data in this QTD
192 // Software QH structure. All three different transaction types
193 // supported by UEFI USB, that is the control/bulk/interrupt
194 // transfers use the queue head and queue token strcuture.
196 // Interrupt QHs are linked to periodic frame list in the reversed
197 // 2^N tree. Each interrupt QH is linked to the list starting at
198 // frame 0. There is a dummy interrupt QH linked to each frame as
199 // a sentinental whose polling interval is 1. Synchronous interrupt
200 // transfer is linked after this dummy QH.
202 // For control/bulk transfer, only synchronous (in the sense of UEFI)
203 // transfer is supported. A dummy QH is linked to EHCI AsyncListAddr
204 // as the reclamation header. New transfer is inserted after this QH.
209 EHC_QH
*NextQh
; // The queue head pointed to by horizontal link
210 LIST_ENTRY Qtds
; // The list of QTDs to this queue head
215 // URB (Usb Request Block) contains information for all kinds of
223 // Transaction information
226 EFI_USB_DEVICE_REQUEST
*Request
; // Control transfer only
227 VOID
*RequestPhy
; // Address of the mapped request
231 VOID
*DataPhy
; // Address of the mapped user data
233 EFI_ASYNC_USB_TRANSFER_CALLBACK Callback
;
242 // Transaction result
245 UINTN Completed
; // completed data length
252 Create a single QTD to hold the data
254 @param Ehc The EHCI device
255 @param Data Current data not associated with a QTD
256 @param DataLen The length of the data
257 @param PktId Packet ID to use in the QTD
258 @param Toggle Data toggle to use in the QTD
259 @param MaxPacket Maximu packet length of the endpoint
261 @return Created QTD or NULL if failed to create one
278 Allocate and initialize a EHCI queue head
280 @param Ehci The EHCI device
281 @param Ep The endpoint to create queue head for
283 @return Created queue head or NULL if failed to create one
288 IN USB2_HC_DEV
*Ehci
,
295 Free an allocated URB. It is possible for it to be partially inited.
297 @param Ehc The EHCI device
298 @param Urb The URB to free
312 Create a new URB and its associated QTD
314 @param Ehc The EHCI device
315 @param DevAddr The device address
316 @param EpAddr Endpoint addrress & its direction
317 @param DevSpeed The device speed
318 @param Toggle Initial data toggle to use
319 @param MaxPacket The max packet length of the endpoint
320 @param Hub The transaction translator to use
321 @param Type The transaction type
322 @param Request The standard USB request for control transfer
323 @param Data The user data to transfer
324 @param DataLen The length of data buffer
325 @param Callback The function to call when data is transferred
326 @param Context The context to the callback
327 @param Interval The interval for interrupt transfer
329 @return Created URB or NULL
340 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR
*Hub
,
342 IN EFI_USB_DEVICE_REQUEST
*Request
,
345 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback
,