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1 /** @file
2
3 This file contains URB request, each request is warpped in a
4 URB (Usb Request Block).
5
6 Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>
7 SPDX-License-Identifier: BSD-2-Clause-Patent
8
9 **/
10
11 #ifndef _EFI_EHCI_URB_H_
12 #define _EFI_EHCI_URB_H_
13
14 typedef struct _EHC_QTD EHC_QTD;
15 typedef struct _EHC_QH EHC_QH;
16 typedef struct _URB URB;
17
18 //
19 // Transfer types, used in URB to identify the transfer type
20 //
21 #define EHC_CTRL_TRANSFER 0x01
22 #define EHC_BULK_TRANSFER 0x02
23 #define EHC_INT_TRANSFER_SYNC 0x04
24 #define EHC_INT_TRANSFER_ASYNC 0x08
25
26 #define EHC_QTD_SIG SIGNATURE_32 ('U', 'S', 'B', 'T')
27 #define EHC_QH_SIG SIGNATURE_32 ('U', 'S', 'B', 'H')
28 #define EHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
29
30 //
31 // Hardware related bit definitions
32 //
33 #define EHC_TYPE_ITD 0x00
34 #define EHC_TYPE_QH 0x02
35 #define EHC_TYPE_SITD 0x04
36 #define EHC_TYPE_FSTN 0x06
37
38 #define QH_NAK_RELOAD 3
39 #define QH_HSHBW_MULTI 1
40
41 #define QTD_MAX_ERR 3
42 #define QTD_PID_OUTPUT 0x00
43 #define QTD_PID_INPUT 0x01
44 #define QTD_PID_SETUP 0x02
45
46 #define QTD_STAT_DO_OUT 0
47 #define QTD_STAT_DO_SS 0
48 #define QTD_STAT_DO_PING 0x01
49 #define QTD_STAT_DO_CS 0x02
50 #define QTD_STAT_TRANS_ERR 0x08
51 #define QTD_STAT_BABBLE_ERR 0x10
52 #define QTD_STAT_BUFF_ERR 0x20
53 #define QTD_STAT_HALTED 0x40
54 #define QTD_STAT_ACTIVE 0x80
55 #define QTD_STAT_ERR_MASK (QTD_STAT_TRANS_ERR | QTD_STAT_BABBLE_ERR | QTD_STAT_BUFF_ERR)
56
57 #define QTD_MAX_BUFFER 4
58 #define QTD_BUF_LEN 4096
59 #define QTD_BUF_MASK 0x0FFF
60
61 #define QH_MICROFRAME_0 0x01
62 #define QH_MICROFRAME_1 0x02
63 #define QH_MICROFRAME_2 0x04
64 #define QH_MICROFRAME_3 0x08
65 #define QH_MICROFRAME_4 0x10
66 #define QH_MICROFRAME_5 0x20
67 #define QH_MICROFRAME_6 0x40
68 #define QH_MICROFRAME_7 0x80
69
70 #define USB_ERR_SHORT_PACKET 0x200
71
72 //
73 // Fill in the hardware link point: pass in a EHC_QH/QH_HW
74 // pointer to QH_LINK; A EHC_QTD/QTD_HW pointer to QTD_LINK
75 //
76 #define QH_LINK(Addr, Type, Term) \
77 ((UINT32) ((EHC_LOW_32BIT (Addr) & 0xFFFFFFE0) | (Type) | ((Term) ? 1 : 0)))
78
79 #define QTD_LINK(Addr, Term) QH_LINK((Addr), 0, (Term))
80
81 //
82 // The defination of EHCI hardware used data structure for
83 // little endian architecture. The QTD and QH structures
84 // are required to be 32 bytes aligned. Don't add members
85 // to the head of the associated software strucuture.
86 //
87 #pragma pack(1)
88 typedef struct {
89 UINT32 NextQtd;
90 UINT32 AltNext;
91
92 UINT32 Status : 8;
93 UINT32 Pid : 2;
94 UINT32 ErrCnt : 2;
95 UINT32 CurPage : 3;
96 UINT32 Ioc : 1;
97 UINT32 TotalBytes : 15;
98 UINT32 DataToggle : 1;
99
100 UINT32 Page[5];
101 UINT32 PageHigh[5];
102 } QTD_HW;
103
104 typedef struct {
105 UINT32 HorizonLink;
106 //
107 // Endpoint capabilities/Characteristics DWord 1 and DWord 2
108 //
109 UINT32 DeviceAddr : 7;
110 UINT32 Inactive : 1;
111 UINT32 EpNum : 4;
112 UINT32 EpSpeed : 2;
113 UINT32 DtCtrl : 1;
114 UINT32 ReclaimHead : 1;
115 UINT32 MaxPacketLen : 11;
116 UINT32 CtrlEp : 1;
117 UINT32 NakReload : 4;
118
119 UINT32 SMask : 8;
120 UINT32 CMask : 8;
121 UINT32 HubAddr : 7;
122 UINT32 PortNum : 7;
123 UINT32 Multiplier : 2;
124
125 //
126 // Transaction execution overlay area
127 //
128 UINT32 CurQtd;
129 UINT32 NextQtd;
130 UINT32 AltQtd;
131
132 UINT32 Status : 8;
133 UINT32 Pid : 2;
134 UINT32 ErrCnt : 2;
135 UINT32 CurPage : 3;
136 UINT32 Ioc : 1;
137 UINT32 TotalBytes : 15;
138 UINT32 DataToggle : 1;
139
140 UINT32 Page[5];
141 UINT32 PageHigh[5];
142 } QH_HW;
143 #pragma pack()
144
145 //
146 // Endpoint address and its capabilities
147 //
148 typedef struct _USB_ENDPOINT {
149 UINT8 DevAddr;
150 UINT8 EpAddr; // Endpoint address, no direction encoded in
151 EFI_USB_DATA_DIRECTION Direction;
152 UINT8 DevSpeed;
153 UINTN MaxPacket;
154 UINT8 HubAddr;
155 UINT8 HubPort;
156 UINT8 Toggle; // Data toggle, not used for control transfer
157 UINTN Type;
158 UINTN PollRate; // Polling interval used by EHCI
159 } USB_ENDPOINT;
160
161 //
162 // Software QTD strcture, this is used to manage all the
163 // QTD generated from a URB. Don't add fields before QtdHw.
164 //
165 struct _EHC_QTD {
166 QTD_HW QtdHw;
167 UINT32 Signature;
168 LIST_ENTRY QtdList; // The list of QTDs to one end point
169 UINT8 *Data; // Buffer of the original data
170 UINTN DataLen; // Original amount of data in this QTD
171 };
172
173 //
174 // Software QH structure. All three different transaction types
175 // supported by UEFI USB, that is the control/bulk/interrupt
176 // transfers use the queue head and queue token strcuture.
177 //
178 // Interrupt QHs are linked to periodic frame list in the reversed
179 // 2^N tree. Each interrupt QH is linked to the list starting at
180 // frame 0. There is a dummy interrupt QH linked to each frame as
181 // a sentinental whose polling interval is 1. Synchronous interrupt
182 // transfer is linked after this dummy QH.
183 //
184 // For control/bulk transfer, only synchronous (in the sense of UEFI)
185 // transfer is supported. A dummy QH is linked to EHCI AsyncListAddr
186 // as the reclamation header. New transfer is inserted after this QH.
187 //
188 struct _EHC_QH {
189 QH_HW QhHw;
190 UINT32 Signature;
191 EHC_QH *NextQh; // The queue head pointed to by horizontal link
192 LIST_ENTRY Qtds; // The list of QTDs to this queue head
193 UINTN Interval;
194 };
195
196 //
197 // URB (Usb Request Block) contains information for all kinds of
198 // usb requests.
199 //
200 struct _URB {
201 UINT32 Signature;
202 LIST_ENTRY UrbList;
203
204 //
205 // Transaction information
206 //
207 USB_ENDPOINT Ep;
208 EFI_USB_DEVICE_REQUEST *Request; // Control transfer only
209 VOID *RequestPhy; // Address of the mapped request
210 VOID *RequestMap;
211 VOID *Data;
212 UINTN DataLen;
213 VOID *DataPhy; // Address of the mapped user data
214 VOID *DataMap;
215 EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
216 VOID *Context;
217
218 //
219 // Schedule data
220 //
221 EHC_QH *Qh;
222
223 //
224 // Transaction result
225 //
226 UINT32 Result;
227 UINTN Completed; // completed data length
228 UINT8 DataToggle;
229 };
230
231 /**
232 Create a single QTD to hold the data.
233
234 @param Ehc The EHCI device.
235 @param Data The cpu memory address of current data not associated with a QTD.
236 @param DataPhy The pci bus address of current data not associated with a QTD.
237 @param DataLen The length of the data.
238 @param PktId Packet ID to use in the QTD.
239 @param Toggle Data toggle to use in the QTD.
240 @param MaxPacket Maximu packet length of the endpoint.
241
242 @return Created QTD or NULL if failed to create one.
243
244 **/
245 EHC_QTD *
246 EhcCreateQtd (
247 IN USB2_HC_DEV *Ehc,
248 IN UINT8 *Data,
249 IN UINT8 *DataPhy,
250 IN UINTN DataLen,
251 IN UINT8 PktId,
252 IN UINT8 Toggle,
253 IN UINTN MaxPacket
254 );
255
256 /**
257 Allocate and initialize a EHCI queue head.
258
259 @param Ehci The EHCI device.
260 @param Ep The endpoint to create queue head for.
261
262 @return Created queue head or NULL if failed to create one.
263
264 **/
265 EHC_QH *
266 EhcCreateQh (
267 IN USB2_HC_DEV *Ehci,
268 IN USB_ENDPOINT *Ep
269 );
270
271 /**
272 Free an allocated URB. It is possible for it to be partially inited.
273
274 @param Ehc The EHCI device.
275 @param Urb The URB to free.
276
277 **/
278 VOID
279 EhcFreeUrb (
280 IN USB2_HC_DEV *Ehc,
281 IN URB *Urb
282 );
283
284 /**
285 Create a new URB and its associated QTD.
286
287 @param Ehc The EHCI device.
288 @param DevAddr The device address.
289 @param EpAddr Endpoint addrress & its direction.
290 @param DevSpeed The device speed.
291 @param Toggle Initial data toggle to use.
292 @param MaxPacket The max packet length of the endpoint.
293 @param Hub The transaction translator to use.
294 @param Type The transaction type.
295 @param Request The standard USB request for control transfer.
296 @param Data The user data to transfer.
297 @param DataLen The length of data buffer.
298 @param Callback The function to call when data is transferred.
299 @param Context The context to the callback.
300 @param Interval The interval for interrupt transfer.
301
302 @return Created URB or NULL.
303
304 **/
305 URB *
306 EhcCreateUrb (
307 IN USB2_HC_DEV *Ehc,
308 IN UINT8 DevAddr,
309 IN UINT8 EpAddr,
310 IN UINT8 DevSpeed,
311 IN UINT8 Toggle,
312 IN UINTN MaxPacket,
313 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
314 IN UINTN Type,
315 IN EFI_USB_DEVICE_REQUEST *Request,
316 IN VOID *Data,
317 IN UINTN DataLen,
318 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
319 IN VOID *Context,
320 IN UINTN Interval
321 );
322
323 #endif