2 Header files and data structures needed by PCI Bus module.
4 Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
10 #ifndef _EFI_PCI_BUS_H_
11 #define _EFI_PCI_BUS_H_
15 #include <Protocol/LoadedImage.h>
16 #include <Protocol/PciHostBridgeResourceAllocation.h>
17 #include <Protocol/PciIo.h>
18 #include <Protocol/LoadFile2.h>
19 #include <Protocol/PciRootBridgeIo.h>
20 #include <Protocol/PciHotPlugRequest.h>
21 #include <Protocol/DevicePath.h>
22 #include <Protocol/PciPlatform.h>
23 #include <Protocol/PciHotPlugInit.h>
24 #include <Protocol/Decompress.h>
25 #include <Protocol/BusSpecificDriverOverride.h>
26 #include <Protocol/IncompatiblePciDeviceSupport.h>
27 #include <Protocol/PciOverride.h>
28 #include <Protocol/PciEnumerationComplete.h>
29 #include <Protocol/IoMmu.h>
30 #include <Protocol/DeviceSecurity.h>
32 #include <Library/DebugLib.h>
33 #include <Library/UefiDriverEntryPoint.h>
34 #include <Library/BaseLib.h>
35 #include <Library/UefiLib.h>
36 #include <Library/BaseMemoryLib.h>
37 #include <Library/ReportStatusCodeLib.h>
38 #include <Library/MemoryAllocationLib.h>
39 #include <Library/UefiBootServicesTableLib.h>
40 #include <Library/DevicePathLib.h>
41 #include <Library/PcdLib.h>
43 #include <IndustryStandard/Pci.h>
44 #include <IndustryStandard/PeImage.h>
45 #include <IndustryStandard/Acpi.h>
47 typedef struct _PCI_IO_DEVICE PCI_IO_DEVICE
;
48 typedef struct _PCI_BAR PCI_BAR
;
50 #define EFI_PCI_RID(Bus, Device, Function) (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)
51 #define EFI_PCI_BUS_OF_RID(RID) ((UINT32)RID >> 8)
53 #define EFI_PCI_IOV_POLICY_ARI 0x0001
54 #define EFI_PCI_IOV_POLICY_SRIOV 0x0002
55 #define EFI_PCI_IOV_POLICY_MRIOV 0x0004
58 PciBarTypeUnknown
= 0,
71 #include "ComponentName.h"
73 #include "PciCommand.h"
74 #include "PciDeviceSupport.h"
75 #include "PciEnumerator.h"
76 #include "PciEnumeratorSupport.h"
77 #include "PciDriverOverride.h"
78 #include "PciRomTable.h"
79 #include "PciOptionRomSupport.h"
80 #include "PciPowerManagement.h"
81 #include "PciHotPlugSupport.h"
84 #define VGABASE1 0x3B0
85 #define VGALIMIT1 0x3BB
87 #define VGABASE2 0x3C0
88 #define VGALIMIT2 0x3DF
91 #define ISALIMIT 0x3FF
100 PCI_BAR_TYPE BarType
;
101 BOOLEAN BarTypeFixed
;
106 // defined in PCI Card Specification, 8.0
108 #define PCI_CARD_MEMORY_BASE_0 0x1C
109 #define PCI_CARD_MEMORY_LIMIT_0 0x20
110 #define PCI_CARD_MEMORY_BASE_1 0x24
111 #define PCI_CARD_MEMORY_LIMIT_1 0x28
112 #define PCI_CARD_IO_BASE_0_LOWER 0x2C
113 #define PCI_CARD_IO_BASE_0_UPPER 0x2E
114 #define PCI_CARD_IO_LIMIT_0_LOWER 0x30
115 #define PCI_CARD_IO_LIMIT_0_UPPER 0x32
116 #define PCI_CARD_IO_BASE_1_LOWER 0x34
117 #define PCI_CARD_IO_BASE_1_UPPER 0x36
118 #define PCI_CARD_IO_LIMIT_1_LOWER 0x38
119 #define PCI_CARD_IO_LIMIT_1_UPPER 0x3A
120 #define PCI_CARD_BRIDGE_CONTROL 0x3E
122 #define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8
123 #define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9
125 #define RB_IO_RANGE 1
126 #define RB_MEM32_RANGE 2
127 #define RB_PMEM32_RANGE 3
128 #define RB_MEM64_RANGE 4
129 #define RB_PMEM64_RANGE 5
133 #define PPB_IO_RANGE 2
134 #define PPB_MEM32_RANGE 3
135 #define PPB_PMEM32_RANGE 4
136 #define PPB_PMEM64_RANGE 5
137 #define PPB_MEM64_RANGE 0xFF
145 #define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001
146 #define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002
147 #define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004
148 #define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008
149 #define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
150 #define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020
151 #define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040
153 #define PCI_MAX_HOST_BRIDGE_NUM 0x0010
156 // Define option for attribute
158 #define EFI_SET_SUPPORTS 0
159 #define EFI_SET_ATTRIBUTES 1
161 #define PCI_IO_DEVICE_SIGNATURE SIGNATURE_32 ('p', 'c', 'i', 'o')
163 struct _PCI_IO_DEVICE
{
166 EFI_PCI_IO_PROTOCOL PciIo
;
169 EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride
;
170 EFI_DEVICE_PATH_PROTOCOL
*DevicePath
;
171 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
172 EFI_LOAD_FILE2_PROTOCOL LoadFile2
;
175 // PCI configuration space header type
180 // Bus number, Device number, Function number
184 UINT8 FunctionNumber
;
187 // BAR for this PCI Device
189 PCI_BAR PciBar
[PCI_MAX_BAR
];
192 // The bridge device this pci device is subject to
194 PCI_IO_DEVICE
*Parent
;
197 // A linked list for children Pci Device if it is bridge device
199 LIST_ENTRY ChildList
;
202 // TRUE if the PCI bus driver creates the handle for this PCI device
207 // TRUE if the PCI bus driver successfully allocates the resource required by
213 // The attribute this PCI device currently set
218 // The attributes this PCI device actually supports
223 // The resource decode the bridge supports
228 // TRUE if the ROM image is from the PCI Option ROM BAR
233 // The OptionRom Size
238 // TRUE if all OpROM (in device or in platform specific position) have been processed
240 BOOLEAN AllOpRomProcessed
;
243 // TRUE if there is any EFI driver in the OptionRom
248 // A list tracking reserved resource on a bridge device
250 LIST_ENTRY ReservedResourceList
;
253 // A list tracking image handle of platform specific overriding driver
255 LIST_ENTRY OptionRomDriverList
;
257 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*ResourcePaddingDescriptors
;
258 EFI_HPC_PADDING_ATTRIBUTES PaddingAttributes
;
261 // Bus number ranges for a PCI Root Bridge device
263 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*BusNumberRanges
;
269 UINT8 PciExpressCapabilityOffset
;
270 UINT32 AriCapabilityOffset
;
271 UINT32 SrIovCapabilityOffset
;
272 UINT32 MrIovCapabilityOffset
;
273 PCI_BAR VfPciBar
[PCI_MAX_BAR
];
274 UINT32 SystemPageSize
;
276 UINT16 ReservedBusNum
;
278 // Per PCI to PCI Bridge spec, I/O window is 4K aligned,
279 // but some chipsets support non-standard I/O window alignments less than 4K.
280 // This field is used to support this case.
282 UINT16 BridgeIoAlignment
;
283 UINT32 ResizableBarOffset
;
284 UINT32 ResizableBarNumber
;
287 #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
288 CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)
290 #define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \
291 CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)
293 #define PCI_IO_DEVICE_FROM_LINK(a) \
294 CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)
296 #define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \
297 CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)
304 extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL
*gIncompatiblePciDeviceSupport
;
305 extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding
;
306 extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName
;
307 extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2
;
308 extern BOOLEAN gFullEnumeration
;
309 extern UINTN gPciHostBridgeNumber
;
310 extern EFI_HANDLE gPciHostBrigeHandles
[PCI_MAX_HOST_BRIDGE_NUM
];
311 extern UINT64 gAllOne
;
312 extern UINT64 gAllZero
;
313 extern EFI_PCI_PLATFORM_PROTOCOL
*gPciPlatformProtocol
;
314 extern EFI_PCI_OVERRIDE_PROTOCOL
*gPciOverrideProtocol
;
315 extern BOOLEAN mReserveIsaAliases
;
316 extern BOOLEAN mReserveVgaAliases
;
319 Macro that checks whether device is a GFX device.
321 @param _p Specified device.
323 @retval TRUE Device is a GFX device.
324 @retval FALSE Device is not a GFX device.
327 #define IS_PCI_GFX(_p) IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)
330 Test to see if this driver supports ControllerHandle. Any ControllerHandle
331 than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.
333 @param This Protocol instance pointer.
334 @param Controller Handle of device to test.
335 @param RemainingDevicePath Optional parameter use to pick a specific child
338 @retval EFI_SUCCESS This driver supports this device.
339 @retval EFI_ALREADY_STARTED This driver is already running on this device.
340 @retval other This driver does not support this device.
345 PciBusDriverBindingSupported (
346 IN EFI_DRIVER_BINDING_PROTOCOL
*This
,
347 IN EFI_HANDLE Controller
,
348 IN EFI_DEVICE_PATH_PROTOCOL
*RemainingDevicePath
352 Start this driver on ControllerHandle and enumerate Pci bus and start
353 all device under PCI bus.
355 @param This Protocol instance pointer.
356 @param Controller Handle of device to bind driver to.
357 @param RemainingDevicePath Optional parameter use to pick a specific child
360 @retval EFI_SUCCESS This driver is added to ControllerHandle.
361 @retval EFI_ALREADY_STARTED This driver is already running on ControllerHandle.
362 @retval other This driver does not support this device.
367 PciBusDriverBindingStart (
368 IN EFI_DRIVER_BINDING_PROTOCOL
*This
,
369 IN EFI_HANDLE Controller
,
370 IN EFI_DEVICE_PATH_PROTOCOL
*RemainingDevicePath
374 Stop this driver on ControllerHandle. Support stopping any child handles
375 created by this driver.
377 @param This Protocol instance pointer.
378 @param Controller Handle of device to stop driver on.
379 @param NumberOfChildren Number of Handles in ChildHandleBuffer. If number of
380 children is zero stop the entire bus driver.
381 @param ChildHandleBuffer List of Child Handles to Stop.
383 @retval EFI_SUCCESS This driver is removed ControllerHandle.
384 @retval other This driver was not removed from this device.
389 PciBusDriverBindingStop (
390 IN EFI_DRIVER_BINDING_PROTOCOL
*This
,
391 IN EFI_HANDLE Controller
,
392 IN UINTN NumberOfChildren
,
393 IN EFI_HANDLE
*ChildHandleBuffer