2 PCI eunmeration implementation on entire PCI bus system for PCI Bus module.
4 Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
5 (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 This routine is used to enumerate entire pci bus system
22 @param Controller Parent controller handle.
23 @param HostBridgeHandle Host bridge handle.
25 @retval EFI_SUCCESS PCI enumeration finished successfully.
26 @retval other Some error occurred when enumerating the pci bus system.
31 IN EFI_HANDLE Controller
,
32 IN EFI_HANDLE HostBridgeHandle
36 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
*PciResAlloc
;
39 // Get the pci host bridge resource allocation protocol
41 Status
= gBS
->OpenProtocol (
43 &gEfiPciHostBridgeResourceAllocationProtocolGuid
,
44 (VOID
**) &PciResAlloc
,
45 gPciBusDriverBinding
.DriverBindingHandle
,
47 EFI_OPEN_PROTOCOL_GET_PROTOCOL
50 if (EFI_ERROR (Status
)) {
55 // Notify the pci bus enumeration is about to begin
57 Status
= NotifyPhase (PciResAlloc
, EfiPciHostBridgeBeginEnumeration
);
59 if (EFI_ERROR (Status
)) {
64 // Start the bus allocation phase
66 Status
= PciHostBridgeEnumerator (PciResAlloc
);
68 if (EFI_ERROR (Status
)) {
73 // Submit the resource request
75 Status
= PciHostBridgeResourceAllocator (PciResAlloc
);
77 if (EFI_ERROR (Status
)) {
82 // Notify the pci bus enumeration is about to complete
84 Status
= NotifyPhase (PciResAlloc
, EfiPciHostBridgeEndEnumeration
);
86 if (EFI_ERROR (Status
)) {
93 Status
= PciHostBridgeP2CProcess (PciResAlloc
);
95 if (EFI_ERROR (Status
)) {
100 // Process attributes for devices on this host bridge
102 Status
= PciHostBridgeDeviceAttribute (PciResAlloc
);
103 if (EFI_ERROR (Status
)) {
111 Enumerate PCI root bridge.
113 @param PciResAlloc Pointer to protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.
114 @param RootBridgeDev Instance of root bridge device.
116 @retval EFI_SUCCESS Successfully enumerated root bridge.
117 @retval other Failed to enumerate root bridge.
121 PciRootBridgeEnumerator (
122 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
*PciResAlloc
,
123 IN PCI_IO_DEVICE
*RootBridgeDev
127 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Configuration
;
128 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Configuration1
;
129 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Configuration2
;
130 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Configuration3
;
132 UINT8 StartBusNumber
;
133 UINT8 PaddedBusRange
;
134 EFI_HANDLE RootBridgeHandle
;
144 // Get the root bridge handle
146 RootBridgeHandle
= RootBridgeDev
->Handle
;
148 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
150 EFI_IO_BUS_PCI
| EFI_IOB_PCI_BUS_ENUM
,
151 RootBridgeDev
->DevicePath
155 // Get the Bus information
157 Status
= PciResAlloc
->StartBusEnumeration (
160 (VOID
**) &Configuration
163 if (EFI_ERROR (Status
)) {
167 if (Configuration
== NULL
|| Configuration
->Desc
== ACPI_END_TAG_DESCRIPTOR
) {
168 return EFI_INVALID_PARAMETER
;
170 RootBridgeDev
->BusNumberRanges
= Configuration
;
173 // Sort the descriptors in ascending order
175 for (Configuration1
= Configuration
; Configuration1
->Desc
!= ACPI_END_TAG_DESCRIPTOR
; Configuration1
++) {
176 Configuration2
= Configuration1
;
177 for (Configuration3
= Configuration1
+ 1; Configuration3
->Desc
!= ACPI_END_TAG_DESCRIPTOR
; Configuration3
++) {
178 if (Configuration2
->AddrRangeMin
> Configuration3
->AddrRangeMin
) {
179 Configuration2
= Configuration3
;
183 // All other fields other than AddrRangeMin and AddrLen are ignored in a descriptor,
184 // so only need to swap these two fields.
186 if (Configuration2
!= Configuration1
) {
187 AddrRangeMin
= Configuration1
->AddrRangeMin
;
188 Configuration1
->AddrRangeMin
= Configuration2
->AddrRangeMin
;
189 Configuration2
->AddrRangeMin
= AddrRangeMin
;
191 AddrLen
= Configuration1
->AddrLen
;
192 Configuration1
->AddrLen
= Configuration2
->AddrLen
;
193 Configuration2
->AddrLen
= AddrLen
;
198 // Get the bus number to start with
200 StartBusNumber
= (UINT8
) (Configuration
->AddrRangeMin
);
203 // Initialize the subordinate bus number
205 SubBusNumber
= StartBusNumber
;
208 // Reset all assigned PCI bus number
210 ResetAllPpbBusNumber (
218 Status
= PciScanBus (
225 if (EFI_ERROR (Status
)) {
231 // Assign max bus number scanned
234 Status
= PciAllocateBusNumber (RootBridgeDev
, SubBusNumber
, PaddedBusRange
, &SubBusNumber
);
235 if (EFI_ERROR (Status
)) {
240 // Find the bus range which contains the higest bus number, then returns the number of buses
241 // that should be decoded.
243 while (Configuration
->AddrRangeMin
+ Configuration
->AddrLen
- 1 < SubBusNumber
) {
246 AddrLen
= Configuration
->AddrLen
;
247 Configuration
->AddrLen
= SubBusNumber
- Configuration
->AddrRangeMin
+ 1;
250 // Save the Desc field of the next descriptor. Mark the next descriptor as an END descriptor.
253 Desc
= Configuration
->Desc
;
254 Configuration
->Desc
= ACPI_END_TAG_DESCRIPTOR
;
259 Status
= PciResAlloc
->SetBusNumbers (
262 RootBridgeDev
->BusNumberRanges
266 // Restore changed fields
268 Configuration
->Desc
= Desc
;
269 (Configuration
- 1)->AddrLen
= AddrLen
;
275 This routine is used to process all PCI devices' Option Rom
276 on a certain root bridge.
278 @param Bridge Given parent's root bridge.
279 @param RomBase Base address of ROM driver loaded from.
280 @param MaxLength Maximum rom size.
285 IN PCI_IO_DEVICE
*Bridge
,
290 LIST_ENTRY
*CurrentLink
;
294 // Go through bridges to reach all devices
296 CurrentLink
= Bridge
->ChildList
.ForwardLink
;
297 while (CurrentLink
!= NULL
&& CurrentLink
!= &Bridge
->ChildList
) {
298 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
299 if (!IsListEmpty (&Temp
->ChildList
)) {
302 // Go further to process the option rom under this bridge
304 ProcessOptionRom (Temp
, RomBase
, MaxLength
);
307 if (Temp
->RomSize
!= 0 && Temp
->RomSize
<= MaxLength
) {
310 // Load and process the option rom
312 LoadOpRomImage (Temp
, RomBase
);
315 CurrentLink
= CurrentLink
->ForwardLink
;
320 This routine is used to assign bus number to the given PCI bus system
322 @param Bridge Parent root bridge instance.
323 @param StartBusNumber Number of beginning.
324 @param SubBusNumber The number of sub bus.
326 @retval EFI_SUCCESS Successfully assigned bus number.
327 @retval EFI_DEVICE_ERROR Failed to assign bus number.
332 IN PCI_IO_DEVICE
*Bridge
,
333 IN UINT8 StartBusNumber
,
334 OUT UINT8
*SubBusNumber
345 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
347 PciRootBridgeIo
= Bridge
->PciRootBridgeIo
;
352 *SubBusNumber
= StartBusNumber
;
355 // First check to see whether the parent is ppb
357 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
358 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
361 // Check to see whether a pci device is present
363 Status
= PciDevicePresent (
371 if (EFI_ERROR (Status
) && Func
== 0) {
373 // go to next device if there is no Function 0
378 if (!EFI_ERROR (Status
) &&
379 (IS_PCI_BRIDGE (&Pci
) || IS_CARDBUS_BRIDGE (&Pci
))) {
382 // Reserved one bus for cardbus bridge
384 Status
= PciAllocateBusNumber (Bridge
, *SubBusNumber
, 1, SubBusNumber
);
385 if (EFI_ERROR (Status
)) {
388 SecondBus
= *SubBusNumber
;
390 Register
= (UINT16
) ((SecondBus
<< 8) | (UINT16
) StartBusNumber
);
392 Address
= EFI_PCI_ADDRESS (StartBusNumber
, Device
, Func
, 0x18);
394 Status
= PciRootBridgeIo
->Pci
.Write (
403 // Initialize SubBusNumber to SecondBus
405 Address
= EFI_PCI_ADDRESS (StartBusNumber
, Device
, Func
, 0x1A);
406 Status
= PciRootBridgeIo
->Pci
.Write (
414 // If it is PPB, resursively search down this bridge
416 if (IS_PCI_BRIDGE (&Pci
)) {
419 Status
= PciRootBridgeIo
->Pci
.Write (
427 Status
= PciAssignBusNumber (
433 if (EFI_ERROR (Status
)) {
434 return EFI_DEVICE_ERROR
;
439 // Set the current maximum bus number under the PPB
441 Address
= EFI_PCI_ADDRESS (StartBusNumber
, Device
, Func
, 0x1A);
443 Status
= PciRootBridgeIo
->Pci
.Write (
453 if (Func
== 0 && !IS_PCI_MULTI_FUNC (&Pci
)) {
456 // Skip sub functions, this is not a multi function device
467 This routine is used to determine the root bridge attribute by interfacing
468 the host bridge resource allocation protocol.
470 @param PciResAlloc Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
471 @param RootBridgeDev Root bridge instance
473 @retval EFI_SUCCESS Successfully got root bridge's attribute.
474 @retval other Failed to get attribute.
478 DetermineRootBridgeAttributes (
479 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
*PciResAlloc
,
480 IN PCI_IO_DEVICE
*RootBridgeDev
485 EFI_HANDLE RootBridgeHandle
;
488 RootBridgeHandle
= RootBridgeDev
->Handle
;
491 // Get root bridge attribute by calling into pci host bridge resource allocation protocol
493 Status
= PciResAlloc
->GetAllocAttributes (
499 if (EFI_ERROR (Status
)) {
504 // Here is the point where PCI bus driver calls HOST bridge allocation protocol
505 // Currently we hardcoded for ea815
507 if ((Attributes
& EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM
) != 0) {
508 RootBridgeDev
->Decodes
|= EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED
;
511 if ((Attributes
& EFI_PCI_HOST_BRIDGE_MEM64_DECODE
) != 0) {
512 RootBridgeDev
->Decodes
|= EFI_BRIDGE_MEM64_DECODE_SUPPORTED
;
513 RootBridgeDev
->Decodes
|= EFI_BRIDGE_PMEM64_DECODE_SUPPORTED
;
516 RootBridgeDev
->Decodes
|= EFI_BRIDGE_MEM32_DECODE_SUPPORTED
;
517 RootBridgeDev
->Decodes
|= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED
;
518 RootBridgeDev
->Decodes
|= EFI_BRIDGE_IO16_DECODE_SUPPORTED
;
524 Get Max Option Rom size on specified bridge.
526 @param Bridge Given bridge device instance.
528 @return Max size of option rom needed.
532 GetMaxOptionRomSize (
533 IN PCI_IO_DEVICE
*Bridge
536 LIST_ENTRY
*CurrentLink
;
538 UINT32 MaxOptionRomSize
;
539 UINT32 TempOptionRomSize
;
541 MaxOptionRomSize
= 0;
544 // Go through bridges to reach all devices
546 CurrentLink
= Bridge
->ChildList
.ForwardLink
;
547 while (CurrentLink
!= NULL
&& CurrentLink
!= &Bridge
->ChildList
) {
548 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
549 if (!IsListEmpty (&Temp
->ChildList
)) {
552 // Get max option rom size under this bridge
554 TempOptionRomSize
= GetMaxOptionRomSize (Temp
);
557 // Compare with the option rom size of the bridge
558 // Get the larger one
560 if (Temp
->RomSize
> TempOptionRomSize
) {
561 TempOptionRomSize
= Temp
->RomSize
;
567 // For devices get the rom size directly
569 TempOptionRomSize
= Temp
->RomSize
;
573 // Get the largest rom size on this bridge
575 if (TempOptionRomSize
> MaxOptionRomSize
) {
576 MaxOptionRomSize
= TempOptionRomSize
;
579 CurrentLink
= CurrentLink
->ForwardLink
;
582 return MaxOptionRomSize
;
586 Process attributes of devices on this host bridge
588 @param PciResAlloc Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.
590 @retval EFI_SUCCESS Successfully process attribute.
591 @retval EFI_NOT_FOUND Can not find the specific root bridge device.
592 @retval other Failed to determine the root bridge device's attribute.
596 PciHostBridgeDeviceAttribute (
597 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
*PciResAlloc
600 EFI_HANDLE RootBridgeHandle
;
601 PCI_IO_DEVICE
*RootBridgeDev
;
604 RootBridgeHandle
= NULL
;
606 while (PciResAlloc
->GetNextRootBridge (PciResAlloc
, &RootBridgeHandle
) == EFI_SUCCESS
) {
609 // Get RootBridg Device by handle
611 RootBridgeDev
= GetRootBridgeByHandle (RootBridgeHandle
);
613 if (RootBridgeDev
== NULL
) {
614 return EFI_NOT_FOUND
;
618 // Set the attributes for devcies behind the Root Bridge
620 Status
= DetermineDeviceAttribute (RootBridgeDev
);
621 if (EFI_ERROR (Status
)) {
631 Get resource allocation status from the ACPI resource descriptor.
633 @param AcpiConfig Point to Acpi configuration table.
634 @param IoResStatus Return the status of I/O resource.
635 @param Mem32ResStatus Return the status of 32-bit Memory resource.
636 @param PMem32ResStatus Return the status of 32-bit Prefetchable Memory resource.
637 @param Mem64ResStatus Return the status of 64-bit Memory resource.
638 @param PMem64ResStatus Return the status of 64-bit Prefetchable Memory resource.
642 GetResourceAllocationStatus (
644 OUT UINT64
*IoResStatus
,
645 OUT UINT64
*Mem32ResStatus
,
646 OUT UINT64
*PMem32ResStatus
,
647 OUT UINT64
*Mem64ResStatus
,
648 OUT UINT64
*PMem64ResStatus
653 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*ACPIAddressDesc
;
655 Temp
= (UINT8
*) AcpiConfig
;
657 while (*Temp
== ACPI_ADDRESS_SPACE_DESCRIPTOR
) {
659 ACPIAddressDesc
= (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*) Temp
;
660 ResStatus
= ACPIAddressDesc
->AddrTranslationOffset
;
662 switch (ACPIAddressDesc
->ResType
) {
664 if (ACPIAddressDesc
->AddrSpaceGranularity
== 32) {
665 if (ACPIAddressDesc
->SpecificFlag
== 0x06) {
669 *PMem32ResStatus
= ResStatus
;
674 *Mem32ResStatus
= ResStatus
;
678 if (ACPIAddressDesc
->AddrSpaceGranularity
== 64) {
679 if (ACPIAddressDesc
->SpecificFlag
== 0x06) {
683 *PMem64ResStatus
= ResStatus
;
688 *Mem64ResStatus
= ResStatus
;
698 *IoResStatus
= ResStatus
;
705 Temp
+= sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
);
710 Remove a PCI device from device pool and mark its bar.
712 @param PciDevice Instance of Pci device.
714 @retval EFI_SUCCESS Successfully remove the PCI device.
715 @retval EFI_ABORTED Pci device is a root bridge or a PCI-PCI bridge.
720 IN PCI_IO_DEVICE
*PciDevice
723 PCI_IO_DEVICE
*Bridge
;
725 LIST_ENTRY
*CurrentLink
;
728 // Remove the padding resource from a bridge
730 if ( IS_PCI_BRIDGE(&PciDevice
->Pci
) &&
731 PciDevice
->ResourcePaddingDescriptors
!= NULL
) {
732 FreePool (PciDevice
->ResourcePaddingDescriptors
);
733 PciDevice
->ResourcePaddingDescriptors
= NULL
;
740 if (IS_PCI_BRIDGE (&PciDevice
->Pci
) || (PciDevice
->Parent
== NULL
)) {
744 if (IS_CARDBUS_BRIDGE (&PciDevice
->Pci
)) {
746 // Get the root bridge device
749 while (Bridge
->Parent
!= NULL
) {
750 Bridge
= Bridge
->Parent
;
753 RemoveAllPciDeviceOnBridge (Bridge
->Handle
, PciDevice
);
758 InitializeP2C (PciDevice
);
764 Bridge
= PciDevice
->Parent
;
765 CurrentLink
= Bridge
->ChildList
.ForwardLink
;
766 while (CurrentLink
!= NULL
&& CurrentLink
!= &Bridge
->ChildList
) {
767 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
768 if (Temp
== PciDevice
) {
769 InitializePciDevice (Temp
);
770 RemoveEntryList (CurrentLink
);
774 CurrentLink
= CurrentLink
->ForwardLink
;
781 Determine whethter a PCI device can be rejected.
783 @param PciResNode Pointer to Pci resource node instance.
785 @retval TRUE The PCI device can be rejected.
786 @retval TRUE The PCI device cannot be rejected.
791 IN PCI_RESOURCE_NODE
*PciResNode
796 Temp
= PciResNode
->PciDev
;
799 // Ensure the device is present
806 // PPB and RB should go ahead
808 if (IS_PCI_BRIDGE (&Temp
->Pci
) || (Temp
->Parent
== NULL
)) {
813 // Skip device on Bus0
815 if ((Temp
->Parent
!= NULL
) && (Temp
->BusNumber
== 0)) {
822 if (IS_PCI_VGA (&Temp
->Pci
)) {
830 Compare two resource nodes and get the larger resource consumer.
832 @param PciResNode1 resource node 1 want to be compared
833 @param PciResNode2 resource node 2 want to be compared
835 @return Larger resource node.
839 GetLargerConsumerDevice (
840 IN PCI_RESOURCE_NODE
*PciResNode1
,
841 IN PCI_RESOURCE_NODE
*PciResNode2
844 if (PciResNode2
== NULL
) {
848 if ((IS_PCI_BRIDGE(&(PciResNode2
->PciDev
->Pci
)) || (PciResNode2
->PciDev
->Parent
== NULL
)) \
849 && (PciResNode2
->ResourceUsage
!= PciResUsagePadding
) )
854 if (PciResNode1
== NULL
) {
858 if ((PciResNode1
->Length
) > (PciResNode2
->Length
)) {
867 Get the max resource consumer in the host resource pool.
869 @param ResPool Pointer to resource pool node.
871 @return The max resource consumer in the host resource pool.
875 GetMaxResourceConsumerDevice (
876 IN PCI_RESOURCE_NODE
*ResPool
879 PCI_RESOURCE_NODE
*Temp
;
880 LIST_ENTRY
*CurrentLink
;
881 PCI_RESOURCE_NODE
*PciResNode
;
882 PCI_RESOURCE_NODE
*PPBResNode
;
886 CurrentLink
= ResPool
->ChildList
.ForwardLink
;
887 while (CurrentLink
!= NULL
&& CurrentLink
!= &ResPool
->ChildList
) {
889 Temp
= RESOURCE_NODE_FROM_LINK (CurrentLink
);
891 if (!IsRejectiveDevice (Temp
)) {
892 CurrentLink
= CurrentLink
->ForwardLink
;
896 if ((IS_PCI_BRIDGE (&(Temp
->PciDev
->Pci
)) || (Temp
->PciDev
->Parent
== NULL
)) \
897 && (Temp
->ResourceUsage
!= PciResUsagePadding
))
899 PPBResNode
= GetMaxResourceConsumerDevice (Temp
);
900 PciResNode
= GetLargerConsumerDevice (PciResNode
, PPBResNode
);
902 PciResNode
= GetLargerConsumerDevice (PciResNode
, Temp
);
905 CurrentLink
= CurrentLink
->ForwardLink
;
912 Adjust host bridge allocation so as to reduce resource requirement
914 @param IoPool Pointer to instance of I/O resource Node.
915 @param Mem32Pool Pointer to instance of 32-bit memory resource Node.
916 @param PMem32Pool Pointer to instance of 32-bit Prefetchable memory resource node.
917 @param Mem64Pool Pointer to instance of 64-bit memory resource node.
918 @param PMem64Pool Pointer to instance of 64-bit Prefetchable memory resource node.
919 @param IoResStatus Status of I/O resource Node.
920 @param Mem32ResStatus Status of 32-bit memory resource Node.
921 @param PMem32ResStatus Status of 32-bit Prefetchable memory resource node.
922 @param Mem64ResStatus Status of 64-bit memory resource node.
923 @param PMem64ResStatus Status of 64-bit Prefetchable memory resource node.
925 @retval EFI_SUCCESS Successfully adjusted resource on host bridge.
926 @retval EFI_ABORTED Host bridge hasn't this resource type or no resource be adjusted.
930 PciHostBridgeAdjustAllocation (
931 IN PCI_RESOURCE_NODE
*IoPool
,
932 IN PCI_RESOURCE_NODE
*Mem32Pool
,
933 IN PCI_RESOURCE_NODE
*PMem32Pool
,
934 IN PCI_RESOURCE_NODE
*Mem64Pool
,
935 IN PCI_RESOURCE_NODE
*PMem64Pool
,
936 IN UINT64 IoResStatus
,
937 IN UINT64 Mem32ResStatus
,
938 IN UINT64 PMem32ResStatus
,
939 IN UINT64 Mem64ResStatus
,
940 IN UINT64 PMem64ResStatus
943 BOOLEAN AllocationAjusted
;
944 PCI_RESOURCE_NODE
*PciResNode
;
945 PCI_RESOURCE_NODE
*ResPool
[5];
946 PCI_IO_DEVICE
*RemovedPciDev
[5];
948 UINTN RemovedPciDevNum
;
952 EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD AllocFailExtendedData
;
955 ZeroMem (RemovedPciDev
, 5 * sizeof (PCI_IO_DEVICE
*));
956 RemovedPciDevNum
= 0;
959 ResPool
[1] = Mem32Pool
;
960 ResPool
[2] = PMem32Pool
;
961 ResPool
[3] = Mem64Pool
;
962 ResPool
[4] = PMem64Pool
;
964 ResStatus
[0] = IoResStatus
;
965 ResStatus
[1] = Mem32ResStatus
;
966 ResStatus
[2] = PMem32ResStatus
;
967 ResStatus
[3] = Mem64ResStatus
;
968 ResStatus
[4] = PMem64ResStatus
;
970 AllocationAjusted
= FALSE
;
972 for (ResType
= 0; ResType
< 5; ResType
++) {
974 if (ResStatus
[ResType
] == EFI_RESOURCE_SATISFIED
) {
978 if (ResStatus
[ResType
] == EFI_RESOURCE_NOT_SATISFIED
) {
980 // Host bridge hasn't this resource type
986 // Hostbridge hasn't enough resource
988 PciResNode
= GetMaxResourceConsumerDevice (ResPool
[ResType
]);
989 if (PciResNode
== NULL
) {
994 // Check if the device has been removed before
996 for (DevIndex
= 0; DevIndex
< RemovedPciDevNum
; DevIndex
++) {
997 if (PciResNode
->PciDev
== RemovedPciDev
[DevIndex
]) {
1002 if (DevIndex
!= RemovedPciDevNum
) {
1007 // Remove the device if it isn't in the array
1009 Status
= RejectPciDevice (PciResNode
->PciDev
);
1010 if (Status
== EFI_SUCCESS
) {
1013 "PciBus: [%02x|%02x|%02x] was rejected due to resource confliction.\n",
1014 PciResNode
->PciDev
->BusNumber
, PciResNode
->PciDev
->DeviceNumber
, PciResNode
->PciDev
->FunctionNumber
1018 // Raise the EFI_IOB_EC_RESOURCE_CONFLICT status code
1021 // Have no way to get ReqRes, AllocRes & Bar here
1023 ZeroMem (&AllocFailExtendedData
, sizeof (AllocFailExtendedData
));
1024 AllocFailExtendedData
.DevicePathSize
= (UINT16
) sizeof (EFI_DEVICE_PATH_PROTOCOL
);
1025 AllocFailExtendedData
.DevicePath
= (UINT8
*) PciResNode
->PciDev
->DevicePath
;
1026 AllocFailExtendedData
.Bar
= PciResNode
->Bar
;
1028 REPORT_STATUS_CODE_WITH_EXTENDED_DATA (
1030 EFI_IO_BUS_PCI
| EFI_IOB_EC_RESOURCE_CONFLICT
,
1031 (VOID
*) &AllocFailExtendedData
,
1032 sizeof (AllocFailExtendedData
)
1036 // Add it to the array and indicate at least a device has been rejected
1038 RemovedPciDev
[RemovedPciDevNum
++] = PciResNode
->PciDev
;
1039 AllocationAjusted
= TRUE
;
1046 if (AllocationAjusted
) {
1054 Summary requests for all resource type, and construct ACPI resource
1057 @param Bridge detecting bridge
1058 @param IoNode Pointer to instance of I/O resource Node
1059 @param Mem32Node Pointer to instance of 32-bit memory resource Node
1060 @param PMem32Node Pointer to instance of 32-bit Pmemory resource node
1061 @param Mem64Node Pointer to instance of 64-bit memory resource node
1062 @param PMem64Node Pointer to instance of 64-bit Pmemory resource node
1063 @param Config Output buffer holding new constructed APCI resource requestor
1065 @retval EFI_SUCCESS Successfully constructed ACPI resource.
1066 @retval EFI_OUT_OF_RESOURCES No memory available.
1070 ConstructAcpiResourceRequestor (
1071 IN PCI_IO_DEVICE
*Bridge
,
1072 IN PCI_RESOURCE_NODE
*IoNode
,
1073 IN PCI_RESOURCE_NODE
*Mem32Node
,
1074 IN PCI_RESOURCE_NODE
*PMem32Node
,
1075 IN PCI_RESOURCE_NODE
*Mem64Node
,
1076 IN PCI_RESOURCE_NODE
*PMem64Node
,
1082 UINT8
*Configuration
;
1083 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Ptr
;
1084 EFI_ACPI_END_TAG_DESCRIPTOR
*PtrEnd
;
1092 // if there is io request, add to the io aperture
1094 if (ResourceRequestExisted (IoNode
)) {
1100 // if there is mem32 request, add to the mem32 aperture
1102 if (ResourceRequestExisted (Mem32Node
)) {
1108 // if there is pmem32 request, add to the pmem32 aperture
1110 if (ResourceRequestExisted (PMem32Node
)) {
1116 // if there is mem64 request, add to the mem64 aperture
1118 if (ResourceRequestExisted (Mem64Node
)) {
1124 // if there is pmem64 request, add to the pmem64 aperture
1126 if (ResourceRequestExisted (PMem64Node
)) {
1131 if (NumConfig
!= 0) {
1134 // If there is at least one type of resource request,
1135 // allocate a acpi resource node
1137 Configuration
= AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) * NumConfig
+ sizeof (EFI_ACPI_END_TAG_DESCRIPTOR
));
1138 if (Configuration
== NULL
) {
1139 return EFI_OUT_OF_RESOURCES
;
1142 Ptr
= (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*) Configuration
;
1145 // Deal with io aperture
1147 if ((Aperture
& 0x01) != 0) {
1148 Ptr
->Desc
= ACPI_ADDRESS_SPACE_DESCRIPTOR
;
1149 Ptr
->Len
= (UINT16
) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) - 3);
1153 Ptr
->ResType
= ACPI_ADDRESS_SPACE_TYPE_IO
;
1157 Ptr
->SpecificFlag
= 1;
1158 Ptr
->AddrLen
= IoNode
->Length
;
1159 Ptr
->AddrRangeMax
= IoNode
->Alignment
;
1164 // Deal with mem32 aperture
1166 if ((Aperture
& 0x02) != 0) {
1167 Ptr
->Desc
= ACPI_ADDRESS_SPACE_DESCRIPTOR
;
1168 Ptr
->Len
= (UINT16
) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) - 3);
1172 Ptr
->ResType
= ACPI_ADDRESS_SPACE_TYPE_MEM
;
1176 Ptr
->SpecificFlag
= 0;
1180 Ptr
->AddrSpaceGranularity
= 32;
1181 Ptr
->AddrLen
= Mem32Node
->Length
;
1182 Ptr
->AddrRangeMax
= Mem32Node
->Alignment
;
1188 // Deal with Pmem32 aperture
1190 if ((Aperture
& 0x04) != 0) {
1191 Ptr
->Desc
= ACPI_ADDRESS_SPACE_DESCRIPTOR
;
1192 Ptr
->Len
= (UINT16
) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) - 3);
1196 Ptr
->ResType
= ACPI_ADDRESS_SPACE_TYPE_MEM
;
1200 Ptr
->SpecificFlag
= 0x6;
1204 Ptr
->AddrSpaceGranularity
= 32;
1205 Ptr
->AddrLen
= PMem32Node
->Length
;
1206 Ptr
->AddrRangeMax
= PMem32Node
->Alignment
;
1211 // Deal with mem64 aperture
1213 if ((Aperture
& 0x08) != 0) {
1214 Ptr
->Desc
= ACPI_ADDRESS_SPACE_DESCRIPTOR
;
1215 Ptr
->Len
= (UINT16
) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) - 3);
1219 Ptr
->ResType
= ACPI_ADDRESS_SPACE_TYPE_MEM
;
1223 Ptr
->SpecificFlag
= 0;
1227 Ptr
->AddrSpaceGranularity
= 64;
1228 Ptr
->AddrLen
= Mem64Node
->Length
;
1229 Ptr
->AddrRangeMax
= Mem64Node
->Alignment
;
1234 // Deal with Pmem64 aperture
1236 if ((Aperture
& 0x10) != 0) {
1237 Ptr
->Desc
= ACPI_ADDRESS_SPACE_DESCRIPTOR
;
1238 Ptr
->Len
= (UINT16
) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) - 3);
1242 Ptr
->ResType
= ACPI_ADDRESS_SPACE_TYPE_MEM
;
1246 Ptr
->SpecificFlag
= 0x06;
1250 Ptr
->AddrSpaceGranularity
= 64;
1251 Ptr
->AddrLen
= PMem64Node
->Length
;
1252 Ptr
->AddrRangeMax
= PMem64Node
->Alignment
;
1260 PtrEnd
= (EFI_ACPI_END_TAG_DESCRIPTOR
*) Ptr
;
1262 PtrEnd
->Desc
= ACPI_END_TAG_DESCRIPTOR
;
1263 PtrEnd
->Checksum
= 0;
1268 // If there is no resource request
1270 Configuration
= AllocateZeroPool (sizeof (EFI_ACPI_END_TAG_DESCRIPTOR
));
1271 if (Configuration
== NULL
) {
1272 return EFI_OUT_OF_RESOURCES
;
1275 PtrEnd
= (EFI_ACPI_END_TAG_DESCRIPTOR
*) (Configuration
);
1276 PtrEnd
->Desc
= ACPI_END_TAG_DESCRIPTOR
;
1277 PtrEnd
->Checksum
= 0;
1280 *Config
= Configuration
;
1286 Get resource base from an acpi configuration descriptor.
1288 @param Config An acpi configuration descriptor.
1289 @param IoBase Output of I/O resource base address.
1290 @param Mem32Base Output of 32-bit memory base address.
1291 @param PMem32Base Output of 32-bit prefetchable memory base address.
1292 @param Mem64Base Output of 64-bit memory base address.
1293 @param PMem64Base Output of 64-bit prefetchable memory base address.
1300 OUT UINT64
*Mem32Base
,
1301 OUT UINT64
*PMem32Base
,
1302 OUT UINT64
*Mem64Base
,
1303 OUT UINT64
*PMem64Base
1307 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Ptr
;
1310 ASSERT (Config
!= NULL
);
1312 *IoBase
= 0xFFFFFFFFFFFFFFFFULL
;
1313 *Mem32Base
= 0xFFFFFFFFFFFFFFFFULL
;
1314 *PMem32Base
= 0xFFFFFFFFFFFFFFFFULL
;
1315 *Mem64Base
= 0xFFFFFFFFFFFFFFFFULL
;
1316 *PMem64Base
= 0xFFFFFFFFFFFFFFFFULL
;
1318 Temp
= (UINT8
*) Config
;
1320 while (*Temp
== ACPI_ADDRESS_SPACE_DESCRIPTOR
) {
1322 Ptr
= (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*) Temp
;
1323 ResStatus
= Ptr
->AddrTranslationOffset
;
1325 if (ResStatus
== EFI_RESOURCE_SATISFIED
) {
1327 switch (Ptr
->ResType
) {
1330 // Memory type aperture
1335 // Check to see the granularity
1337 if (Ptr
->AddrSpaceGranularity
== 32) {
1338 if ((Ptr
->SpecificFlag
& 0x06) != 0) {
1339 *PMem32Base
= Ptr
->AddrRangeMin
;
1341 *Mem32Base
= Ptr
->AddrRangeMin
;
1345 if (Ptr
->AddrSpaceGranularity
== 64) {
1346 if ((Ptr
->SpecificFlag
& 0x06) != 0) {
1347 *PMem64Base
= Ptr
->AddrRangeMin
;
1349 *Mem64Base
= Ptr
->AddrRangeMin
;
1359 *IoBase
= Ptr
->AddrRangeMin
;
1373 Temp
+= sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
);
1378 Enumerate pci bridge, allocate resource and determine attribute
1379 for devices on this bridge.
1381 @param BridgeDev Pointer to instance of bridge device.
1383 @retval EFI_SUCCESS Successfully enumerated PCI bridge.
1384 @retval other Failed to enumerate.
1388 PciBridgeEnumerator (
1389 IN PCI_IO_DEVICE
*BridgeDev
1393 UINT8 StartBusNumber
;
1394 EFI_PCI_IO_PROTOCOL
*PciIo
;
1399 PciIo
= &(BridgeDev
->PciIo
);
1400 Status
= PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, 0x19, 1, &StartBusNumber
);
1402 if (EFI_ERROR (Status
)) {
1406 Status
= PciAssignBusNumber (
1412 if (EFI_ERROR (Status
)) {
1416 Status
= PciPciDeviceInfoCollector (BridgeDev
, StartBusNumber
);
1418 if (EFI_ERROR (Status
)) {
1422 Status
= PciBridgeResourceAllocator (BridgeDev
);
1424 if (EFI_ERROR (Status
)) {
1428 Status
= DetermineDeviceAttribute (BridgeDev
);
1430 if (EFI_ERROR (Status
)) {
1439 Allocate all kinds of resource for PCI bridge.
1441 @param Bridge Pointer to bridge instance.
1443 @retval EFI_SUCCESS Successfully allocated resource for PCI bridge.
1444 @retval other Failed to allocate resource for bridge.
1448 PciBridgeResourceAllocator (
1449 IN PCI_IO_DEVICE
*Bridge
1452 PCI_RESOURCE_NODE
*IoBridge
;
1453 PCI_RESOURCE_NODE
*Mem32Bridge
;
1454 PCI_RESOURCE_NODE
*PMem32Bridge
;
1455 PCI_RESOURCE_NODE
*Mem64Bridge
;
1456 PCI_RESOURCE_NODE
*PMem64Bridge
;
1464 IoBridge
= CreateResourceNode (
1467 Bridge
->BridgeIoAlignment
,
1473 Mem32Bridge
= CreateResourceNode (
1482 PMem32Bridge
= CreateResourceNode (
1491 Mem64Bridge
= CreateResourceNode (
1500 PMem64Bridge
= CreateResourceNode (
1510 // Create resourcemap by going through all the devices subject to this root bridge
1521 Status
= GetResourceBaseFromBridge (
1530 if (EFI_ERROR (Status
)) {
1535 // Program IO resources
1543 // Program Mem32 resources
1551 // Program PMem32 resources
1559 // Program Mem64 resources
1567 // Program PMem64 resources
1574 DestroyResourceTree (IoBridge
);
1575 DestroyResourceTree (Mem32Bridge
);
1576 DestroyResourceTree (PMem32Bridge
);
1577 DestroyResourceTree (PMem64Bridge
);
1578 DestroyResourceTree (Mem64Bridge
);
1580 gBS
->FreePool (IoBridge
);
1581 gBS
->FreePool (Mem32Bridge
);
1582 gBS
->FreePool (PMem32Bridge
);
1583 gBS
->FreePool (PMem64Bridge
);
1584 gBS
->FreePool (Mem64Bridge
);
1590 Get resource base address for a pci bridge device.
1592 @param Bridge Given Pci driver instance.
1593 @param IoBase Output for base address of I/O type resource.
1594 @param Mem32Base Output for base address of 32-bit memory type resource.
1595 @param PMem32Base Ooutput for base address of 32-bit Pmemory type resource.
1596 @param Mem64Base Output for base address of 64-bit memory type resource.
1597 @param PMem64Base Output for base address of 64-bit Pmemory type resource.
1599 @retval EFI_SUCCESS Successfully got resource base address.
1600 @retval EFI_OUT_OF_RESOURCES PCI bridge is not available.
1604 GetResourceBaseFromBridge (
1605 IN PCI_IO_DEVICE
*Bridge
,
1607 OUT UINT64
*Mem32Base
,
1608 OUT UINT64
*PMem32Base
,
1609 OUT UINT64
*Mem64Base
,
1610 OUT UINT64
*PMem64Base
1613 if (!Bridge
->Allocated
) {
1614 return EFI_OUT_OF_RESOURCES
;
1618 *Mem32Base
= gAllOne
;
1619 *PMem32Base
= gAllOne
;
1620 *Mem64Base
= gAllOne
;
1621 *PMem64Base
= gAllOne
;
1623 if (IS_PCI_BRIDGE (&Bridge
->Pci
)) {
1625 if (Bridge
->PciBar
[PPB_IO_RANGE
].Length
> 0) {
1626 *IoBase
= Bridge
->PciBar
[PPB_IO_RANGE
].BaseAddress
;
1629 if (Bridge
->PciBar
[PPB_MEM32_RANGE
].Length
> 0) {
1630 *Mem32Base
= Bridge
->PciBar
[PPB_MEM32_RANGE
].BaseAddress
;
1633 if (Bridge
->PciBar
[PPB_PMEM32_RANGE
].Length
> 0) {
1634 *PMem32Base
= Bridge
->PciBar
[PPB_PMEM32_RANGE
].BaseAddress
;
1637 if (Bridge
->PciBar
[PPB_PMEM64_RANGE
].Length
> 0) {
1638 *PMem64Base
= Bridge
->PciBar
[PPB_PMEM64_RANGE
].BaseAddress
;
1640 *PMem64Base
= gAllOne
;
1645 if (IS_CARDBUS_BRIDGE (&Bridge
->Pci
)) {
1646 if (Bridge
->PciBar
[P2C_IO_1
].Length
> 0) {
1647 *IoBase
= Bridge
->PciBar
[P2C_IO_1
].BaseAddress
;
1649 if (Bridge
->PciBar
[P2C_IO_2
].Length
> 0) {
1650 *IoBase
= Bridge
->PciBar
[P2C_IO_2
].BaseAddress
;
1654 if (Bridge
->PciBar
[P2C_MEM_1
].Length
> 0) {
1655 if (Bridge
->PciBar
[P2C_MEM_1
].BarType
== PciBarTypePMem32
) {
1656 *PMem32Base
= Bridge
->PciBar
[P2C_MEM_1
].BaseAddress
;
1659 if (Bridge
->PciBar
[P2C_MEM_1
].BarType
== PciBarTypeMem32
) {
1660 *Mem32Base
= Bridge
->PciBar
[P2C_MEM_1
].BaseAddress
;
1664 if (Bridge
->PciBar
[P2C_MEM_2
].Length
> 0) {
1665 if (Bridge
->PciBar
[P2C_MEM_2
].BarType
== PciBarTypePMem32
) {
1666 *PMem32Base
= Bridge
->PciBar
[P2C_MEM_2
].BaseAddress
;
1669 if (Bridge
->PciBar
[P2C_MEM_2
].BarType
== PciBarTypeMem32
) {
1670 *Mem32Base
= Bridge
->PciBar
[P2C_MEM_2
].BaseAddress
;
1679 These are the notifications from the PCI bus driver that it is about to enter a certain
1680 phase of the PCI enumeration process.
1682 This member function can be used to notify the host bridge driver to perform specific actions,
1683 including any chipset-specific initialization, so that the chipset is ready to enter the next phase.
1684 Eight notification points are defined at this time. See belows:
1685 EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures and internal data
1686 structures. The PCI enumerator should issue this notification
1687 before starting a fresh enumeration process. Enumeration cannot
1688 be restarted after sending any other notification such as
1689 EfiPciHostBridgeBeginBusAllocation.
1690 EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin. No specific action is
1691 required here. This notification can be used to perform any
1692 chipset-specific programming.
1693 EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming phase is complete. No
1694 specific action is required here. This notification can be used to
1695 perform any chipset-specific programming.
1696 EfiPciHostBridgeBeginResourceAllocation
1697 The resource allocation phase is about to begin. No specific
1698 action is required here. This notification can be used to perform
1699 any chipset-specific programming.
1700 EfiPciHostBridgeAllocateResources Allocates resources per previously submitted requests for all the PCI
1701 root bridges. These resource settings are returned on the next call to
1702 GetProposedResources(). Before calling NotifyPhase() with a Phase of
1703 EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible
1704 for gathering I/O and memory requests for
1705 all the PCI root bridges and submitting these requests using
1706 SubmitResources(). This function pads the resource amount
1707 to suit the root bridge hardware, takes care of dependencies between
1708 the PCI root bridges, and calls the Global Coherency Domain (GCD)
1709 with the allocation request. In the case of padding, the allocated range
1710 could be bigger than what was requested.
1711 EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated
1712 resources (proposed resources) for all the PCI root bridges. After the
1713 hardware is programmed, reassigning resources will not be supported.
1714 The bus settings are not affected.
1715 EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI
1716 root bridges and resets the I/O and memory apertures to their initial
1717 state. The bus settings are not affected. If the request to allocate
1718 resources fails, the PCI enumerator can use this notification to
1719 deallocate previous resources, adjust the requests, and retry
1721 EfiPciHostBridgeEndResourceAllocation The resource allocation phase is completed. No specific action is
1722 required here. This notification can be used to perform any chipsetspecific
1725 @param[in] PciResAlloc The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
1726 @param[in] Phase The phase during enumeration
1728 @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error
1729 is valid for a Phase of EfiPciHostBridgeAllocateResources if
1730 SubmitResources() has not been called for one or more
1731 PCI root bridges before this call
1732 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid
1733 for a Phase of EfiPciHostBridgeSetResources.
1734 @retval EFI_INVALID_PARAMETER Invalid phase parameter
1735 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1736 This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the
1737 previously submitted resource requests cannot be fulfilled or
1738 were only partially fulfilled.
1739 @retval EFI_SUCCESS The notification was accepted without any errors.
1744 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
*PciResAlloc
,
1745 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
1748 EFI_HANDLE HostBridgeHandle
;
1749 EFI_HANDLE RootBridgeHandle
;
1750 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
1753 HostBridgeHandle
= NULL
;
1754 RootBridgeHandle
= NULL
;
1755 if (gPciPlatformProtocol
!= NULL
) {
1757 // Get Host Bridge Handle.
1759 PciResAlloc
->GetNextRootBridge (PciResAlloc
, &RootBridgeHandle
);
1762 // Get the rootbridge Io protocol to find the host bridge handle
1764 Status
= gBS
->HandleProtocol (
1766 &gEfiPciRootBridgeIoProtocolGuid
,
1767 (VOID
**) &PciRootBridgeIo
1770 if (EFI_ERROR (Status
)) {
1771 return EFI_NOT_FOUND
;
1774 HostBridgeHandle
= PciRootBridgeIo
->ParentHandle
;
1777 // Call PlatformPci::PlatformNotify() if the protocol is present.
1779 gPciPlatformProtocol
->PlatformNotify (
1780 gPciPlatformProtocol
,
1785 } else if (gPciOverrideProtocol
!= NULL
){
1787 // Get Host Bridge Handle.
1789 PciResAlloc
->GetNextRootBridge (PciResAlloc
, &RootBridgeHandle
);
1792 // Get the rootbridge Io protocol to find the host bridge handle
1794 Status
= gBS
->HandleProtocol (
1796 &gEfiPciRootBridgeIoProtocolGuid
,
1797 (VOID
**) &PciRootBridgeIo
1800 if (EFI_ERROR (Status
)) {
1801 return EFI_NOT_FOUND
;
1804 HostBridgeHandle
= PciRootBridgeIo
->ParentHandle
;
1807 // Call PlatformPci::PhaseNotify() if the protocol is present.
1809 gPciOverrideProtocol
->PlatformNotify (
1810 gPciOverrideProtocol
,
1817 Status
= PciResAlloc
->NotifyPhase (
1822 if (gPciPlatformProtocol
!= NULL
) {
1824 // Call PlatformPci::PlatformNotify() if the protocol is present.
1826 gPciPlatformProtocol
->PlatformNotify (
1827 gPciPlatformProtocol
,
1833 } else if (gPciOverrideProtocol
!= NULL
) {
1835 // Call PlatformPci::PhaseNotify() if the protocol is present.
1837 gPciOverrideProtocol
->PlatformNotify (
1838 gPciOverrideProtocol
,
1849 Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various
1850 stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual
1851 PCI controllers before enumeration.
1853 This function is called during the PCI enumeration process. No specific action is expected from this
1854 member function. It allows the host bridge driver to preinitialize individual PCI controllers before
1857 @param Bridge Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
1858 @param Bus The bus number of the pci device.
1859 @param Device The device number of the pci device.
1860 @param Func The function number of the pci device.
1861 @param Phase The phase of the PCI device enumeration.
1863 @retval EFI_SUCCESS The requested parameters were returned.
1864 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
1865 @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in
1866 EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.
1867 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should
1868 not enumerate this device, including its child devices if it is a PCI-to-PCI
1873 PreprocessController (
1874 IN PCI_IO_DEVICE
*Bridge
,
1878 IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
1881 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS RootBridgePciAddress
;
1882 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
*PciResAlloc
;
1883 EFI_HANDLE RootBridgeHandle
;
1884 EFI_HANDLE HostBridgeHandle
;
1888 // Get the host bridge handle
1890 HostBridgeHandle
= Bridge
->PciRootBridgeIo
->ParentHandle
;
1893 // Get the pci host bridge resource allocation protocol
1895 Status
= gBS
->OpenProtocol (
1897 &gEfiPciHostBridgeResourceAllocationProtocolGuid
,
1898 (VOID
**) &PciResAlloc
,
1901 EFI_OPEN_PROTOCOL_GET_PROTOCOL
1904 if (EFI_ERROR (Status
)) {
1905 return EFI_UNSUPPORTED
;
1909 // Get Root Brige Handle
1911 while (Bridge
->Parent
!= NULL
) {
1912 Bridge
= Bridge
->Parent
;
1915 RootBridgeHandle
= Bridge
->Handle
;
1917 RootBridgePciAddress
.Register
= 0;
1918 RootBridgePciAddress
.Function
= Func
;
1919 RootBridgePciAddress
.Device
= Device
;
1920 RootBridgePciAddress
.Bus
= Bus
;
1921 RootBridgePciAddress
.ExtendedRegister
= 0;
1923 if (gPciPlatformProtocol
!= NULL
) {
1925 // Call PlatformPci::PrepController() if the protocol is present.
1927 gPciPlatformProtocol
->PlatformPrepController (
1928 gPciPlatformProtocol
,
1931 RootBridgePciAddress
,
1935 } else if (gPciOverrideProtocol
!= NULL
) {
1937 // Call PlatformPci::PrepController() if the protocol is present.
1939 gPciOverrideProtocol
->PlatformPrepController (
1940 gPciOverrideProtocol
,
1943 RootBridgePciAddress
,
1949 Status
= PciResAlloc
->PreprocessController (
1952 RootBridgePciAddress
,
1956 if (gPciPlatformProtocol
!= NULL
) {
1958 // Call PlatformPci::PrepController() if the protocol is present.
1960 gPciPlatformProtocol
->PlatformPrepController (
1961 gPciPlatformProtocol
,
1964 RootBridgePciAddress
,
1968 } else if (gPciOverrideProtocol
!= NULL
) {
1970 // Call PlatformPci::PrepController() if the protocol is present.
1972 gPciOverrideProtocol
->PlatformPrepController (
1973 gPciOverrideProtocol
,
1976 RootBridgePciAddress
,
1986 This function allows the PCI bus driver to be notified to act as requested when a hot-plug event has
1987 happened on the hot-plug controller. Currently, the operations include add operation and remove operation..
1989 @param This A pointer to the hot plug request protocol.
1990 @param Operation The operation the PCI bus driver is requested to make.
1991 @param Controller The handle of the hot-plug controller.
1992 @param RemainingDevicePath The remaining device path for the PCI-like hot-plug device.
1993 @param NumberOfChildren The number of child handles.
1994 For a add operation, it is an output parameter.
1995 For a remove operation, it's an input parameter.
1996 @param ChildHandleBuffer The buffer which contains the child handles.
1998 @retval EFI_INVALID_PARAMETER Operation is not a legal value.
1999 Controller is NULL or not a valid handle.
2000 NumberOfChildren is NULL.
2001 ChildHandleBuffer is NULL while Operation is add.
2002 @retval EFI_OUT_OF_RESOURCES There are no enough resources to start the devices.
2003 @retval EFI_NOT_FOUND Can not find bridge according to controller handle.
2004 @retval EFI_SUCCESS The handles for the specified device have been created or destroyed
2005 as requested, and for an add operation, the new handles are
2006 returned in ChildHandleBuffer.
2010 PciHotPlugRequestNotify (
2011 IN EFI_PCI_HOTPLUG_REQUEST_PROTOCOL
* This
,
2012 IN EFI_PCI_HOTPLUG_OPERATION Operation
,
2013 IN EFI_HANDLE Controller
,
2014 IN EFI_DEVICE_PATH_PROTOCOL
* RemainingDevicePath OPTIONAL
,
2015 IN OUT UINT8
*NumberOfChildren
,
2016 IN OUT EFI_HANDLE
* ChildHandleBuffer
2019 PCI_IO_DEVICE
*Bridge
;
2020 PCI_IO_DEVICE
*Temp
;
2021 EFI_PCI_IO_PROTOCOL
*PciIo
;
2023 EFI_HANDLE RootBridgeHandle
;
2027 // Check input parameter validity
2029 if ((Controller
== NULL
) || (NumberOfChildren
== NULL
)){
2030 return EFI_INVALID_PARAMETER
;
2033 if ((Operation
!= EfiPciHotPlugRequestAdd
) && (Operation
!= EfiPciHotplugRequestRemove
)) {
2034 return EFI_INVALID_PARAMETER
;
2037 if (Operation
== EfiPciHotPlugRequestAdd
){
2038 if (ChildHandleBuffer
== NULL
) {
2039 return EFI_INVALID_PARAMETER
;
2041 } else if ((Operation
== EfiPciHotplugRequestRemove
) && (*NumberOfChildren
!= 0)) {
2042 if (ChildHandleBuffer
== NULL
) {
2043 return EFI_INVALID_PARAMETER
;
2047 Status
= gBS
->OpenProtocol (
2049 &gEfiPciIoProtocolGuid
,
2051 gPciBusDriverBinding
.DriverBindingHandle
,
2053 EFI_OPEN_PROTOCOL_GET_PROTOCOL
2056 if (EFI_ERROR (Status
)) {
2057 return EFI_NOT_FOUND
;
2060 Bridge
= PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo
);
2063 // Get root bridge handle
2066 while (Temp
->Parent
!= NULL
) {
2067 Temp
= Temp
->Parent
;
2070 RootBridgeHandle
= Temp
->Handle
;
2072 if (Operation
== EfiPciHotPlugRequestAdd
) {
2074 // Report Status Code to indicate hot plug happens
2076 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
2078 (EFI_IO_BUS_PCI
| EFI_IOB_PC_HOTPLUG
),
2082 if (NumberOfChildren
!= NULL
) {
2083 *NumberOfChildren
= 0;
2086 if (IsListEmpty (&Bridge
->ChildList
)) {
2088 Status
= PciBridgeEnumerator (Bridge
);
2090 if (EFI_ERROR (Status
)) {
2095 Status
= StartPciDevicesOnBridge (
2098 RemainingDevicePath
,
2106 if (Operation
== EfiPciHotplugRequestRemove
) {
2108 if (*NumberOfChildren
== 0) {
2110 // Remove all devices on the bridge
2112 RemoveAllPciDeviceOnBridge (RootBridgeHandle
, Bridge
);
2117 for (Index
= 0; Index
< *NumberOfChildren
; Index
++) {
2119 // De register all the pci device
2121 Status
= DeRegisterPciDevice (RootBridgeHandle
, ChildHandleBuffer
[Index
]);
2123 if (EFI_ERROR (Status
)) {
2138 Search hostbridge according to given handle
2140 @param RootBridgeHandle Host bridge handle.
2142 @retval TRUE Found host bridge handle.
2143 @retval FALSE Not found hot bridge handle.
2147 SearchHostBridgeHandle (
2148 IN EFI_HANDLE RootBridgeHandle
2151 EFI_HANDLE HostBridgeHandle
;
2152 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
2157 // Get the rootbridge Io protocol to find the host bridge handle
2159 Status
= gBS
->OpenProtocol (
2161 &gEfiPciRootBridgeIoProtocolGuid
,
2162 (VOID
**) &PciRootBridgeIo
,
2163 gPciBusDriverBinding
.DriverBindingHandle
,
2165 EFI_OPEN_PROTOCOL_GET_PROTOCOL
2168 if (EFI_ERROR (Status
)) {
2172 HostBridgeHandle
= PciRootBridgeIo
->ParentHandle
;
2173 for (Index
= 0; Index
< gPciHostBridgeNumber
; Index
++) {
2174 if (HostBridgeHandle
== gPciHostBrigeHandles
[Index
]) {
2183 Add host bridge handle to global variable for enumerating.
2185 @param HostBridgeHandle Host bridge handle.
2187 @retval EFI_SUCCESS Successfully added host bridge.
2188 @retval EFI_ABORTED Host bridge is NULL, or given host bridge
2189 has been in host bridge list.
2193 AddHostBridgeEnumerator (
2194 IN EFI_HANDLE HostBridgeHandle
2199 if (HostBridgeHandle
== NULL
) {
2203 for (Index
= 0; Index
< gPciHostBridgeNumber
; Index
++) {
2204 if (HostBridgeHandle
== gPciHostBrigeHandles
[Index
]) {
2209 if (Index
< PCI_MAX_HOST_BRIDGE_NUM
) {
2210 gPciHostBrigeHandles
[Index
] = HostBridgeHandle
;
2211 gPciHostBridgeNumber
++;