2 PCI emumeration support functions implementation for PCI Bus module.
4 Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 extern CHAR16
*mBarTypeStr
[];
20 This routine is used to check whether the pci device is present.
22 @param PciRootBridgeIo Pointer to instance of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
23 @param Pci Output buffer for PCI device configuration space.
24 @param Bus PCI bus NO.
25 @param Device PCI device NO.
26 @param Func PCI Func NO.
28 @retval EFI_NOT_FOUND PCI device not present.
29 @retval EFI_SUCCESS PCI device is found.
34 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
,
45 // Create PCI address map in terms of Bus, Device and Func
47 Address
= EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
50 // Read the Vendor ID register
52 Status
= PciRootBridgeIo
->Pci
.Read (
60 if (!EFI_ERROR (Status
) && (Pci
->Hdr
).VendorId
!= 0xffff) {
62 // Read the entire config header for the device
64 Status
= PciRootBridgeIo
->Pci
.Read (
68 sizeof (PCI_TYPE00
) / sizeof (UINT32
),
79 Collect all the resource information under this root bridge.
81 A database that records all the information about pci device subject to this
82 root bridge will then be created.
84 @param Bridge Parent bridge instance.
85 @param StartBusNumber Bus number of begining.
87 @retval EFI_SUCCESS PCI device is found.
88 @retval other Some error occurred when reading PCI bridge information.
92 PciPciDeviceInfoCollector (
93 IN PCI_IO_DEVICE
*Bridge
,
94 IN UINT8 StartBusNumber
102 PCI_IO_DEVICE
*PciIoDevice
;
103 EFI_PCI_IO_PROTOCOL
*PciIo
;
105 Status
= EFI_SUCCESS
;
108 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
110 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
113 // Check to see whether PCI device is present
115 Status
= PciDevicePresent (
116 Bridge
->PciRootBridgeIo
,
118 (UINT8
) StartBusNumber
,
122 if (!EFI_ERROR (Status
)) {
125 // Call back to host bridge function
127 PreprocessController (Bridge
, (UINT8
) StartBusNumber
, Device
, Func
, EfiPciBeforeResourceCollection
);
130 // Collect all the information about the PCI device discovered
132 Status
= PciSearchDevice (
135 (UINT8
) StartBusNumber
,
142 // Recursively scan PCI busses on the other side of PCI-PCI bridges
145 if (!EFI_ERROR (Status
) && (IS_PCI_BRIDGE (&Pci
) || IS_CARDBUS_BRIDGE (&Pci
))) {
148 // If it is PPB, we need to get the secondary bus to continue the enumeration
150 PciIo
= &(PciIoDevice
->PciIo
);
152 Status
= PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET
, 1, &SecBus
);
154 if (EFI_ERROR (Status
)) {
159 // Get resource padding for PPB
161 GetResourcePaddingPpb (PciIoDevice
);
164 // Deep enumerate the next level bus
166 Status
= PciPciDeviceInfoCollector (
173 if (Func
== 0 && !IS_PCI_MULTI_FUNC (&Pci
)) {
176 // Skip sub functions, this is not a multi function device
189 Seach required device and create PCI device instance.
191 @param Bridge Parent bridge instance.
192 @param Pci Input PCI device information block.
193 @param Bus PCI bus NO.
194 @param Device PCI device NO.
195 @param Func PCI func NO.
196 @param PciDevice Output of searched PCI device instance.
198 @retval EFI_SUCCESS Successfully created PCI device instance.
199 @retval EFI_OUT_OF_RESOURCES Cannot get PCI device information.
204 IN PCI_IO_DEVICE
*Bridge
,
209 OUT PCI_IO_DEVICE
**PciDevice
212 PCI_IO_DEVICE
*PciIoDevice
;
218 "PciBus: Discovered %s @ [%02x|%02x|%02x]\n",
219 IS_PCI_BRIDGE (Pci
) ? L
"PPB" :
220 IS_CARDBUS_BRIDGE (Pci
) ? L
"P2C" :
225 if (!IS_PCI_BRIDGE (Pci
)) {
227 if (IS_CARDBUS_BRIDGE (Pci
)) {
228 PciIoDevice
= GatherP2CInfo (
235 if ((PciIoDevice
!= NULL
) && gFullEnumeration
) {
236 InitializeP2C (PciIoDevice
);
241 // Create private data for Pci Device
243 PciIoDevice
= GatherDeviceInfo (
256 // Create private data for PPB
258 PciIoDevice
= GatherPpbInfo (
267 // Special initialization for PPB including making the PPB quiet
269 if ((PciIoDevice
!= NULL
) && gFullEnumeration
) {
270 InitializePpb (PciIoDevice
);
274 if (PciIoDevice
== NULL
) {
275 return EFI_OUT_OF_RESOURCES
;
279 // Update the bar information for this PCI device so as to support some specific device
281 UpdatePciInfo (PciIoDevice
);
283 if (PciIoDevice
->DevicePath
== NULL
) {
284 return EFI_OUT_OF_RESOURCES
;
288 // Detect this function has option rom
290 if (gFullEnumeration
) {
292 if (!IS_CARDBUS_BRIDGE (Pci
)) {
294 GetOpRomInfo (PciIoDevice
);
298 ResetPowerManagementFeature (PciIoDevice
);
303 // Insert it into a global tree for future reference
305 InsertPciDevice (Bridge
, PciIoDevice
);
308 // Determine PCI device attributes
311 if (PciDevice
!= NULL
) {
312 *PciDevice
= PciIoDevice
;
319 Dump the PCI BAR information.
321 @param PciIoDevice PCI IO instance.
325 IN PCI_IO_DEVICE
*PciIoDevice
330 for (Index
= 0; Index
< PCI_MAX_BAR
; Index
++) {
331 if (PciIoDevice
->PciBar
[Index
].BarType
== PciBarTypeUnknown
) {
337 " BAR[%d]: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx;\tOffset = 0x%02x\n",
338 Index
, mBarTypeStr
[MIN (PciIoDevice
->PciBar
[Index
].BarType
, PciBarTypeMaxType
)],
339 PciIoDevice
->PciBar
[Index
].Alignment
, PciIoDevice
->PciBar
[Index
].Length
, PciIoDevice
->PciBar
[Index
].Offset
343 for (Index
= 0; Index
< PCI_MAX_BAR
; Index
++) {
344 if ((PciIoDevice
->VfPciBar
[Index
].BarType
== PciBarTypeUnknown
) && (PciIoDevice
->VfPciBar
[Index
].Length
== 0)) {
350 " VFBAR[%d]: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx;\tOffset = 0x%02x\n",
351 Index
, mBarTypeStr
[MIN (PciIoDevice
->VfPciBar
[Index
].BarType
, PciBarTypeMaxType
)],
352 PciIoDevice
->VfPciBar
[Index
].Alignment
, PciIoDevice
->VfPciBar
[Index
].Length
, PciIoDevice
->VfPciBar
[Index
].Offset
355 DEBUG ((EFI_D_INFO
, "\n"));
359 Create PCI device instance for PCI device.
361 @param Bridge Parent bridge instance.
362 @param Pci Input PCI device information block.
363 @param Bus PCI device Bus NO.
364 @param Device PCI device Device NO.
365 @param Func PCI device's func NO.
367 @return Created PCI device instance.
372 IN PCI_IO_DEVICE
*Bridge
,
381 PCI_IO_DEVICE
*PciIoDevice
;
383 PciIoDevice
= CreatePciIoDevice (
391 if (PciIoDevice
== NULL
) {
396 // Create a device path for this PCI device and store it into its private data
398 CreatePciDevicePath (
404 // If it is a full enumeration, disconnect the device in advance
406 if (gFullEnumeration
) {
408 PCI_DISABLE_COMMAND_REGISTER (PciIoDevice
, EFI_PCI_COMMAND_BITS_OWNED
);
413 // Start to parse the bars
415 for (Offset
= 0x10, BarIndex
= 0; Offset
<= 0x24 && BarIndex
< PCI_MAX_BAR
; BarIndex
++) {
416 Offset
= PciParseBar (PciIoDevice
, Offset
, BarIndex
);
420 // Parse the SR-IOV VF bars
422 if (PcdGetBool (PcdSrIovSupport
) && PciIoDevice
->SrIovCapabilityOffset
!= 0) {
423 for (Offset
= PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0
, BarIndex
= 0;
424 Offset
<= PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5
;
427 ASSERT (BarIndex
< PCI_MAX_BAR
);
428 Offset
= PciIovParseVfBar (PciIoDevice
, Offset
, BarIndex
);
432 DEBUG_CODE (DumpPciBars (PciIoDevice
););
437 Create PCI device instance for PCI-PCI bridge.
439 @param Bridge Parent bridge instance.
440 @param Pci Input PCI device information block.
441 @param Bus PCI device Bus NO.
442 @param Device PCI device Device NO.
443 @param Func PCI device's func NO.
445 @return Created PCI device instance.
450 IN PCI_IO_DEVICE
*Bridge
,
457 PCI_IO_DEVICE
*PciIoDevice
;
460 EFI_PCI_IO_PROTOCOL
*PciIo
;
462 UINT32 PMemBaseLimit
;
463 UINT16 PrefetchableMemoryBase
;
464 UINT16 PrefetchableMemoryLimit
;
466 PciIoDevice
= CreatePciIoDevice (
474 if (PciIoDevice
== NULL
) {
479 // Create a device path for this PCI device and store it into its private data
481 CreatePciDevicePath (
486 if (gFullEnumeration
) {
487 PCI_DISABLE_COMMAND_REGISTER (PciIoDevice
, EFI_PCI_COMMAND_BITS_OWNED
);
490 // Initalize the bridge control register
492 PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice
, EFI_PCI_BRIDGE_CONTROL_BITS_OWNED
);
497 // PPB can have two BARs
499 if (PciParseBar (PciIoDevice
, 0x10, PPB_BAR_0
) == 0x14) {
503 PciParseBar (PciIoDevice
, 0x14, PPB_BAR_1
);
506 PciIo
= &PciIoDevice
->PciIo
;
509 // Test whether it support 32 decode or not
511 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Temp
);
512 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &gAllOne
);
513 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Value
);
514 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Temp
);
517 if ((Value
& 0x01) != 0) {
518 PciIoDevice
->Decodes
|= EFI_BRIDGE_IO32_DECODE_SUPPORTED
;
520 PciIoDevice
->Decodes
|= EFI_BRIDGE_IO16_DECODE_SUPPORTED
;
525 // if PcdPciBridgeIoAlignmentProbe is TRUE, PCI bus driver probes
526 // PCI bridge supporting non-stardard I/O window alignment less than 4K.
529 PciIoDevice
->BridgeIoAlignment
= 0xFFF;
530 if (FeaturePcdGet (PcdPciBridgeIoAlignmentProbe
)) {
532 // Check any bits of bit 3-1 of I/O Base Register are writable.
533 // if so, it is assumed non-stardard I/O window alignment is supported by this bridge.
534 // Per spec, bit 3-1 of I/O Base Register are reserved bits, so its content can't be assumed.
536 Value
= (UINT8
)(Temp
^ (BIT3
| BIT2
| BIT1
));
537 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Value
);
538 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Value
);
539 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Temp
);
540 Value
= (UINT8
)((Value
^ Temp
) & (BIT3
| BIT2
| BIT1
));
543 PciIoDevice
->BridgeIoAlignment
= 0x7FF;
546 PciIoDevice
->BridgeIoAlignment
= 0x3FF;
548 case BIT3
| BIT2
| BIT1
:
549 PciIoDevice
->BridgeIoAlignment
= 0x1FF;
554 Status
= BarExisted (
562 // Test if it supports 64 memory or not
564 // The bottom 4 bits of both the Prefetchable Memory Base and Prefetchable Memory Limit
566 // 0 - the bridge supports only 32 bit addresses.
567 // 1 - the bridge supports 64-bit addresses.
569 PrefetchableMemoryBase
= (UINT16
)(PMemBaseLimit
& 0xffff);
570 PrefetchableMemoryLimit
= (UINT16
)(PMemBaseLimit
>> 16);
571 if (!EFI_ERROR (Status
) &&
572 (PrefetchableMemoryBase
& 0x000f) == 0x0001 &&
573 (PrefetchableMemoryLimit
& 0x000f) == 0x0001) {
574 Status
= BarExisted (
581 if (!EFI_ERROR (Status
)) {
582 PciIoDevice
->Decodes
|= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED
;
583 PciIoDevice
->Decodes
|= EFI_BRIDGE_PMEM64_DECODE_SUPPORTED
;
585 PciIoDevice
->Decodes
|= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED
;
590 // Memory 32 code is required for ppb
592 PciIoDevice
->Decodes
|= EFI_BRIDGE_MEM32_DECODE_SUPPORTED
;
594 GetResourcePaddingPpb (PciIoDevice
);
596 DEBUG_CODE (DumpPciBars (PciIoDevice
););
603 Create PCI device instance for PCI Card bridge device.
605 @param Bridge Parent bridge instance.
606 @param Pci Input PCI device information block.
607 @param Bus PCI device Bus NO.
608 @param Device PCI device Device NO.
609 @param Func PCI device's func NO.
611 @return Created PCI device instance.
616 IN PCI_IO_DEVICE
*Bridge
,
623 PCI_IO_DEVICE
*PciIoDevice
;
625 PciIoDevice
= CreatePciIoDevice (
633 if (PciIoDevice
== NULL
) {
638 // Create a device path for this PCI device and store it into its private data
640 CreatePciDevicePath (
645 if (gFullEnumeration
) {
646 PCI_DISABLE_COMMAND_REGISTER (PciIoDevice
, EFI_PCI_COMMAND_BITS_OWNED
);
649 // Initalize the bridge control register
651 PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice
, EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED
);
655 // P2C only has one bar that is in 0x10
657 PciParseBar (PciIoDevice
, 0x10, P2C_BAR_0
);
660 // Read PciBar information from the bar register
662 GetBackPcCardBar (PciIoDevice
);
663 PciIoDevice
->Decodes
= EFI_BRIDGE_MEM32_DECODE_SUPPORTED
|
664 EFI_BRIDGE_PMEM32_DECODE_SUPPORTED
|
665 EFI_BRIDGE_IO32_DECODE_SUPPORTED
;
667 DEBUG_CODE (DumpPciBars (PciIoDevice
););
673 Create device path for pci deivce.
675 @param ParentDevicePath Parent bridge's path.
676 @param PciIoDevice Pci device instance.
678 @return Device path protocol instance for specific pci device.
681 EFI_DEVICE_PATH_PROTOCOL
*
682 CreatePciDevicePath (
683 IN EFI_DEVICE_PATH_PROTOCOL
*ParentDevicePath
,
684 IN PCI_IO_DEVICE
*PciIoDevice
688 PCI_DEVICE_PATH PciNode
;
691 // Create PCI device path
693 PciNode
.Header
.Type
= HARDWARE_DEVICE_PATH
;
694 PciNode
.Header
.SubType
= HW_PCI_DP
;
695 SetDevicePathNodeLength (&PciNode
.Header
, sizeof (PciNode
));
697 PciNode
.Device
= PciIoDevice
->DeviceNumber
;
698 PciNode
.Function
= PciIoDevice
->FunctionNumber
;
699 PciIoDevice
->DevicePath
= AppendDevicePathNode (ParentDevicePath
, &PciNode
.Header
);
701 return PciIoDevice
->DevicePath
;
705 Check whether the PCI IOV VF bar is existed or not.
707 @param PciIoDevice A pointer to the PCI_IO_DEVICE.
708 @param Offset The offset.
709 @param BarLengthValue The bar length value returned.
710 @param OriginalBarValue The original bar value returned.
712 @retval EFI_NOT_FOUND The bar doesn't exist.
713 @retval EFI_SUCCESS The bar exist.
718 IN PCI_IO_DEVICE
*PciIoDevice
,
720 OUT UINT32
*BarLengthValue
,
721 OUT UINT32
*OriginalBarValue
724 EFI_PCI_IO_PROTOCOL
*PciIo
;
725 UINT32 OriginalValue
;
730 // Ensure it is called properly
732 ASSERT (PciIoDevice
->SrIovCapabilityOffset
!= 0);
733 if (PciIoDevice
->SrIovCapabilityOffset
== 0) {
734 return EFI_NOT_FOUND
;
737 PciIo
= &PciIoDevice
->PciIo
;
740 // Preserve the original value
743 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint32
, (UINT32
)Offset
, 1, &OriginalValue
);
746 // Raise TPL to high level to disable timer interrupt while the BAR is probed
748 OldTpl
= gBS
->RaiseTPL (TPL_HIGH_LEVEL
);
750 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, (UINT32
)Offset
, 1, &gAllOne
);
751 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint32
, (UINT32
)Offset
, 1, &Value
);
754 // Write back the original value
756 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, (UINT32
)Offset
, 1, &OriginalValue
);
759 // Restore TPL to its original level
761 gBS
->RestoreTPL (OldTpl
);
763 if (BarLengthValue
!= NULL
) {
764 *BarLengthValue
= Value
;
767 if (OriginalBarValue
!= NULL
) {
768 *OriginalBarValue
= OriginalValue
;
772 return EFI_NOT_FOUND
;
779 Check whether the bar is existed or not.
781 @param PciIoDevice A pointer to the PCI_IO_DEVICE.
782 @param Offset The offset.
783 @param BarLengthValue The bar length value returned.
784 @param OriginalBarValue The original bar value returned.
786 @retval EFI_NOT_FOUND The bar doesn't exist.
787 @retval EFI_SUCCESS The bar exist.
792 IN PCI_IO_DEVICE
*PciIoDevice
,
794 OUT UINT32
*BarLengthValue
,
795 OUT UINT32
*OriginalBarValue
798 EFI_PCI_IO_PROTOCOL
*PciIo
;
799 UINT32 OriginalValue
;
803 PciIo
= &PciIoDevice
->PciIo
;
806 // Preserve the original value
808 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint32
, (UINT8
) Offset
, 1, &OriginalValue
);
811 // Raise TPL to high level to disable timer interrupt while the BAR is probed
813 OldTpl
= gBS
->RaiseTPL (TPL_HIGH_LEVEL
);
815 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, (UINT8
) Offset
, 1, &gAllOne
);
816 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint32
, (UINT8
) Offset
, 1, &Value
);
819 // Write back the original value
821 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, (UINT8
) Offset
, 1, &OriginalValue
);
824 // Restore TPL to its original level
826 gBS
->RestoreTPL (OldTpl
);
828 if (BarLengthValue
!= NULL
) {
829 *BarLengthValue
= Value
;
832 if (OriginalBarValue
!= NULL
) {
833 *OriginalBarValue
= OriginalValue
;
837 return EFI_NOT_FOUND
;
844 Test whether the device can support given attributes.
846 @param PciIoDevice Pci device instance.
847 @param Command Input command register value, and
848 returned supported register value.
849 @param BridgeControl Inout bridge control value for PPB or P2C, and
850 returned supported bridge control value.
851 @param OldCommand Returned and stored old command register offset.
852 @param OldBridgeControl Returned and stored old Bridge control value for PPB or P2C.
856 PciTestSupportedAttribute (
857 IN PCI_IO_DEVICE
*PciIoDevice
,
858 IN OUT UINT16
*Command
,
859 IN OUT UINT16
*BridgeControl
,
860 OUT UINT16
*OldCommand
,
861 OUT UINT16
*OldBridgeControl
867 // Preserve the original value
869 PCI_READ_COMMAND_REGISTER (PciIoDevice
, OldCommand
);
872 // Raise TPL to high level to disable timer interrupt while the BAR is probed
874 OldTpl
= gBS
->RaiseTPL (TPL_HIGH_LEVEL
);
876 PCI_SET_COMMAND_REGISTER (PciIoDevice
, *Command
);
877 PCI_READ_COMMAND_REGISTER (PciIoDevice
, Command
);
880 // Write back the original value
882 PCI_SET_COMMAND_REGISTER (PciIoDevice
, *OldCommand
);
885 // Restore TPL to its original level
887 gBS
->RestoreTPL (OldTpl
);
889 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
) || IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
892 // Preserve the original value
894 PCI_READ_BRIDGE_CONTROL_REGISTER (PciIoDevice
, OldBridgeControl
);
897 // Raise TPL to high level to disable timer interrupt while the BAR is probed
899 OldTpl
= gBS
->RaiseTPL (TPL_HIGH_LEVEL
);
901 PCI_SET_BRIDGE_CONTROL_REGISTER (PciIoDevice
, *BridgeControl
);
902 PCI_READ_BRIDGE_CONTROL_REGISTER (PciIoDevice
, BridgeControl
);
905 // Write back the original value
907 PCI_SET_BRIDGE_CONTROL_REGISTER (PciIoDevice
, *OldBridgeControl
);
910 // Restore TPL to its original level
912 gBS
->RestoreTPL (OldTpl
);
915 *OldBridgeControl
= 0;
921 Set the supported or current attributes of a PCI device.
923 @param PciIoDevice Structure pointer for PCI device.
924 @param Command Command register value.
925 @param BridgeControl Bridge control value for PPB or P2C.
926 @param Option Make a choice of EFI_SET_SUPPORTS or EFI_SET_ATTRIBUTES.
930 PciSetDeviceAttribute (
931 IN PCI_IO_DEVICE
*PciIoDevice
,
933 IN UINT16 BridgeControl
,
941 if ((Command
& EFI_PCI_COMMAND_IO_SPACE
) != 0) {
942 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IO
;
945 if ((Command
& EFI_PCI_COMMAND_MEMORY_SPACE
) != 0) {
946 Attributes
|= EFI_PCI_IO_ATTRIBUTE_MEMORY
;
949 if ((Command
& EFI_PCI_COMMAND_BUS_MASTER
) != 0) {
950 Attributes
|= EFI_PCI_IO_ATTRIBUTE_BUS_MASTER
;
953 if ((Command
& EFI_PCI_COMMAND_VGA_PALETTE_SNOOP
) != 0) {
954 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO
;
957 if ((BridgeControl
& EFI_PCI_BRIDGE_CONTROL_ISA
) != 0) {
958 Attributes
|= EFI_PCI_IO_ATTRIBUTE_ISA_IO
;
961 if ((BridgeControl
& EFI_PCI_BRIDGE_CONTROL_VGA
) != 0) {
962 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_IO
;
963 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY
;
964 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO
;
967 if ((BridgeControl
& EFI_PCI_BRIDGE_CONTROL_VGA_16
) != 0) {
968 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_IO_16
;
969 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16
;
972 if (Option
== EFI_SET_SUPPORTS
) {
974 Attributes
|= EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE
|
975 EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED
|
976 EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE
|
977 EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE
|
978 EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM
|
979 EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE
;
981 if (IS_PCI_LPC (&PciIoDevice
->Pci
)) {
982 Attributes
|= EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO
;
983 Attributes
|= (mReserveIsaAliases
? (UINT64
) EFI_PCI_IO_ATTRIBUTE_ISA_IO
: \
984 (UINT64
) EFI_PCI_IO_ATTRIBUTE_ISA_IO_16
);
987 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
) || IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
989 // For bridge, it should support IDE attributes
991 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO
;
992 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO
;
994 if (mReserveVgaAliases
) {
995 Attributes
&= ~(UINT64
)(EFI_PCI_IO_ATTRIBUTE_VGA_IO_16
| \
996 EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16
);
998 Attributes
&= ~(UINT64
)(EFI_PCI_IO_ATTRIBUTE_VGA_IO
| \
999 EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO
);
1003 if (IS_PCI_IDE (&PciIoDevice
->Pci
)) {
1004 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO
;
1005 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO
;
1008 if (IS_PCI_VGA (&PciIoDevice
->Pci
)) {
1009 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY
;
1010 Attributes
|= (mReserveVgaAliases
? (UINT64
) EFI_PCI_IO_ATTRIBUTE_VGA_IO
: \
1011 (UINT64
) EFI_PCI_IO_ATTRIBUTE_VGA_IO_16
);
1015 PciIoDevice
->Supports
= Attributes
;
1016 PciIoDevice
->Supports
&= ( (PciIoDevice
->Parent
->Supports
) | \
1017 EFI_PCI_IO_ATTRIBUTE_IO
| EFI_PCI_IO_ATTRIBUTE_MEMORY
| \
1018 EFI_PCI_IO_ATTRIBUTE_BUS_MASTER
);
1022 // When this attribute is clear, the RomImage and RomSize fields in the PCI IO were
1023 // initialized based on the PCI option ROM found through the ROM BAR of the PCI controller.
1024 // When this attribute is set, the PCI option ROM described by the RomImage and RomSize
1025 // fields is not from the the ROM BAR of the PCI controller.
1027 if (!PciIoDevice
->EmbeddedRom
) {
1028 Attributes
|= EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM
;
1030 PciIoDevice
->Attributes
= Attributes
;
1035 Determine if the device can support Fast Back to Back attribute.
1037 @param PciIoDevice Pci device instance.
1038 @param StatusIndex Status register value.
1040 @retval EFI_SUCCESS This device support Fast Back to Back attribute.
1041 @retval EFI_UNSUPPORTED This device doesn't support Fast Back to Back attribute.
1045 GetFastBackToBackSupport (
1046 IN PCI_IO_DEVICE
*PciIoDevice
,
1047 IN UINT8 StatusIndex
1050 EFI_PCI_IO_PROTOCOL
*PciIo
;
1052 UINT32 StatusRegister
;
1055 // Read the status register
1057 PciIo
= &PciIoDevice
->PciIo
;
1058 Status
= PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint16
, StatusIndex
, 1, &StatusRegister
);
1059 if (EFI_ERROR (Status
)) {
1060 return EFI_UNSUPPORTED
;
1064 // Check the Fast B2B bit
1066 if ((StatusRegister
& EFI_PCI_FAST_BACK_TO_BACK_CAPABLE
) != 0) {
1069 return EFI_UNSUPPORTED
;
1074 Process the option ROM for all the children of the specified parent PCI device.
1075 It can only be used after the first full Option ROM process.
1077 @param PciIoDevice Pci device instance.
1081 ProcessOptionRomLight (
1082 IN PCI_IO_DEVICE
*PciIoDevice
1085 PCI_IO_DEVICE
*Temp
;
1086 LIST_ENTRY
*CurrentLink
;
1089 // For RootBridge, PPB , P2C, go recursively to traverse all its children
1091 CurrentLink
= PciIoDevice
->ChildList
.ForwardLink
;
1092 while (CurrentLink
!= NULL
&& CurrentLink
!= &PciIoDevice
->ChildList
) {
1094 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
1096 if (!IsListEmpty (&Temp
->ChildList
)) {
1097 ProcessOptionRomLight (Temp
);
1100 PciRomGetImageMapping (Temp
);
1103 // The OpRom has already been processed in the first round
1105 Temp
->AllOpRomProcessed
= TRUE
;
1107 CurrentLink
= CurrentLink
->ForwardLink
;
1112 Determine the related attributes of all devices under a Root Bridge.
1114 @param PciIoDevice PCI device instance.
1118 DetermineDeviceAttribute (
1119 IN PCI_IO_DEVICE
*PciIoDevice
1123 UINT16 BridgeControl
;
1125 UINT16 OldBridgeControl
;
1126 BOOLEAN FastB2BSupport
;
1127 PCI_IO_DEVICE
*Temp
;
1128 LIST_ENTRY
*CurrentLink
;
1132 // For Root Bridge, just copy it by RootBridgeIo proctocol
1133 // so as to keep consistent with the actual attribute
1135 if (PciIoDevice
->Parent
== NULL
) {
1136 Status
= PciIoDevice
->PciRootBridgeIo
->GetAttributes (
1137 PciIoDevice
->PciRootBridgeIo
,
1138 &PciIoDevice
->Supports
,
1139 &PciIoDevice
->Attributes
1141 if (EFI_ERROR (Status
)) {
1145 // Assume the PCI Root Bridge supports DAC
1147 PciIoDevice
->Supports
|= (EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE
|
1148 EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM
|
1149 EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE
);
1154 // Set the attributes to be checked for common PCI devices and PPB or P2C
1155 // Since some devices only support part of them, it is better to set the
1156 // attribute according to its command or bridge control register
1158 Command
= EFI_PCI_COMMAND_IO_SPACE
|
1159 EFI_PCI_COMMAND_MEMORY_SPACE
|
1160 EFI_PCI_COMMAND_BUS_MASTER
|
1161 EFI_PCI_COMMAND_VGA_PALETTE_SNOOP
;
1163 BridgeControl
= EFI_PCI_BRIDGE_CONTROL_ISA
| EFI_PCI_BRIDGE_CONTROL_VGA
| EFI_PCI_BRIDGE_CONTROL_VGA_16
;
1166 // Test whether the device can support attributes above
1168 PciTestSupportedAttribute (PciIoDevice
, &Command
, &BridgeControl
, &OldCommand
, &OldBridgeControl
);
1171 // Set the supported attributes for specified PCI device
1173 PciSetDeviceAttribute (PciIoDevice
, Command
, BridgeControl
, EFI_SET_SUPPORTS
);
1176 // Set the current attributes for specified PCI device
1178 PciSetDeviceAttribute (PciIoDevice
, OldCommand
, OldBridgeControl
, EFI_SET_ATTRIBUTES
);
1181 // Enable other supported attributes but not defined in PCI_IO_PROTOCOL
1183 PCI_ENABLE_COMMAND_REGISTER (PciIoDevice
, EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE
);
1186 FastB2BSupport
= TRUE
;
1189 // P2C can not support FB2B on the secondary side
1191 if (IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
1192 FastB2BSupport
= FALSE
;
1196 // For RootBridge, PPB , P2C, go recursively to traverse all its children
1198 CurrentLink
= PciIoDevice
->ChildList
.ForwardLink
;
1199 while (CurrentLink
!= NULL
&& CurrentLink
!= &PciIoDevice
->ChildList
) {
1201 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
1202 Status
= DetermineDeviceAttribute (Temp
);
1203 if (EFI_ERROR (Status
)) {
1207 // Detect Fast Bact to Bact support for the device under the bridge
1209 Status
= GetFastBackToBackSupport (Temp
, PCI_PRIMARY_STATUS_OFFSET
);
1210 if (FastB2BSupport
&& EFI_ERROR (Status
)) {
1211 FastB2BSupport
= FALSE
;
1214 CurrentLink
= CurrentLink
->ForwardLink
;
1217 // Set or clear Fast Back to Back bit for the whole bridge
1219 if (!IsListEmpty (&PciIoDevice
->ChildList
)) {
1221 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
)) {
1223 Status
= GetFastBackToBackSupport (PciIoDevice
, PCI_BRIDGE_STATUS_REGISTER_OFFSET
);
1225 if (EFI_ERROR (Status
) || (!FastB2BSupport
)) {
1226 FastB2BSupport
= FALSE
;
1227 PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice
, EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK
);
1229 PCI_ENABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice
, EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK
);
1233 CurrentLink
= PciIoDevice
->ChildList
.ForwardLink
;
1234 while (CurrentLink
!= NULL
&& CurrentLink
!= &PciIoDevice
->ChildList
) {
1235 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
1236 if (FastB2BSupport
) {
1237 PCI_ENABLE_COMMAND_REGISTER (Temp
, EFI_PCI_COMMAND_FAST_BACK_TO_BACK
);
1239 PCI_DISABLE_COMMAND_REGISTER (Temp
, EFI_PCI_COMMAND_FAST_BACK_TO_BACK
);
1242 CurrentLink
= CurrentLink
->ForwardLink
;
1246 // End for IsListEmpty
1252 This routine is used to update the bar information for those incompatible PCI device.
1254 @param PciIoDevice Input Pci device instance. Output Pci device instance with updated
1257 @retval EFI_SUCCESS Successfully updated bar information.
1258 @retval EFI_UNSUPPORTED Given PCI device doesn't belong to incompatible PCI device list.
1263 IN OUT PCI_IO_DEVICE
*PciIoDevice
1270 VOID
*Configuration
;
1271 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Ptr
;
1273 Configuration
= NULL
;
1274 Status
= EFI_SUCCESS
;
1276 if (gEfiIncompatiblePciDeviceSupport
== NULL
) {
1278 // It can only be supported after the Incompatible PCI Device
1279 // Support Protocol has been installed
1281 Status
= gBS
->LocateProtocol (
1282 &gEfiIncompatiblePciDeviceSupportProtocolGuid
,
1284 (VOID
**) &gEfiIncompatiblePciDeviceSupport
1287 if (Status
== EFI_SUCCESS
) {
1289 // Check whether the device belongs to incompatible devices from protocol or not
1290 // If it is , then get its special requirement in the ACPI table
1292 Status
= gEfiIncompatiblePciDeviceSupport
->CheckDevice (
1293 gEfiIncompatiblePciDeviceSupport
,
1294 PciIoDevice
->Pci
.Hdr
.VendorId
,
1295 PciIoDevice
->Pci
.Hdr
.DeviceId
,
1296 PciIoDevice
->Pci
.Hdr
.RevisionID
,
1297 PciIoDevice
->Pci
.Device
.SubsystemVendorID
,
1298 PciIoDevice
->Pci
.Device
.SubsystemID
,
1304 if (EFI_ERROR (Status
) || Configuration
== NULL
) {
1305 return EFI_UNSUPPORTED
;
1309 // Update PCI device information from the ACPI table
1311 Ptr
= (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*) Configuration
;
1313 while (Ptr
->Desc
!= ACPI_END_TAG_DESCRIPTOR
) {
1315 if (Ptr
->Desc
!= ACPI_ADDRESS_SPACE_DESCRIPTOR
) {
1317 // The format is not support
1322 BarIndex
= (UINTN
) Ptr
->AddrTranslationOffset
;
1323 BarEndIndex
= BarIndex
;
1326 // Update all the bars in the device
1328 if (BarIndex
== PCI_BAR_ALL
) {
1330 BarEndIndex
= PCI_MAX_BAR
- 1;
1333 if (BarIndex
> PCI_MAX_BAR
) {
1338 for (; BarIndex
<= BarEndIndex
; BarIndex
++) {
1340 switch (Ptr
->ResType
) {
1341 case ACPI_ADDRESS_SPACE_TYPE_MEM
:
1344 // Make sure the bar is memory type
1346 if (CheckBarType (PciIoDevice
, (UINT8
) BarIndex
, PciBarTypeMem
)) {
1351 case ACPI_ADDRESS_SPACE_TYPE_IO
:
1354 // Make sure the bar is IO type
1356 if (CheckBarType (PciIoDevice
, (UINT8
) BarIndex
, PciBarTypeIo
)) {
1365 // Update the new alignment for the device
1367 SetNewAlign (&(PciIoDevice
->PciBar
[BarIndex
].Alignment
), Ptr
->AddrRangeMax
);
1370 // Update the new length for the device
1372 if (Ptr
->AddrLen
!= PCI_BAR_NOCHANGE
) {
1373 PciIoDevice
->PciBar
[BarIndex
].Length
= Ptr
->AddrLen
;
1381 FreePool (Configuration
);
1387 This routine will update the alignment with the new alignment.
1389 @param Alignment Input Old alignment. Output updated alignment.
1390 @param NewAlignment New alignment.
1395 IN OUT UINT64
*Alignment
,
1396 IN UINT64 NewAlignment
1399 UINT64 OldAlignment
;
1403 // The new alignment is the same as the original,
1406 if (NewAlignment
== PCI_BAR_OLD_ALIGN
) {
1410 // Check the validity of the parameter
1412 if (NewAlignment
!= PCI_BAR_EVEN_ALIGN
&&
1413 NewAlignment
!= PCI_BAR_SQUAD_ALIGN
&&
1414 NewAlignment
!= PCI_BAR_DQUAD_ALIGN
) {
1415 *Alignment
= NewAlignment
;
1419 OldAlignment
= (*Alignment
) + 1;
1423 // Get the first non-zero hex value of the length
1425 while ((OldAlignment
& 0x0F) == 0x00) {
1426 OldAlignment
= RShiftU64 (OldAlignment
, 4);
1431 // Adjust the alignment to even, quad or double quad boundary
1433 if (NewAlignment
== PCI_BAR_EVEN_ALIGN
) {
1434 if ((OldAlignment
& 0x01) != 0) {
1435 OldAlignment
= OldAlignment
+ 2 - (OldAlignment
& 0x01);
1437 } else if (NewAlignment
== PCI_BAR_SQUAD_ALIGN
) {
1438 if ((OldAlignment
& 0x03) != 0) {
1439 OldAlignment
= OldAlignment
+ 4 - (OldAlignment
& 0x03);
1441 } else if (NewAlignment
== PCI_BAR_DQUAD_ALIGN
) {
1442 if ((OldAlignment
& 0x07) != 0) {
1443 OldAlignment
= OldAlignment
+ 8 - (OldAlignment
& 0x07);
1448 // Update the old value
1450 NewAlignment
= LShiftU64 (OldAlignment
, ShiftBit
) - 1;
1451 *Alignment
= NewAlignment
;
1457 Parse PCI IOV VF bar information and fill them into PCI device instance.
1459 @param PciIoDevice Pci device instance.
1460 @param Offset Bar offset.
1461 @param BarIndex Bar index.
1463 @return Next bar offset.
1468 IN PCI_IO_DEVICE
*PciIoDevice
,
1474 UINT32 OriginalValue
;
1479 // Ensure it is called properly
1481 ASSERT (PciIoDevice
->SrIovCapabilityOffset
!= 0);
1482 if (PciIoDevice
->SrIovCapabilityOffset
== 0) {
1489 Status
= VfBarExisted (
1496 if (EFI_ERROR (Status
)) {
1497 PciIoDevice
->VfPciBar
[BarIndex
].BaseAddress
= 0;
1498 PciIoDevice
->VfPciBar
[BarIndex
].Length
= 0;
1499 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= 0;
1502 // Scan all the BARs anyway
1504 PciIoDevice
->VfPciBar
[BarIndex
].Offset
= (UINT16
) Offset
;
1508 PciIoDevice
->VfPciBar
[BarIndex
].Offset
= (UINT16
) Offset
;
1509 if ((Value
& 0x01) != 0) {
1511 // Device I/Os. Impossible
1520 PciIoDevice
->VfPciBar
[BarIndex
].BaseAddress
= OriginalValue
& Mask
;
1522 switch (Value
& 0x07) {
1525 //memory space; anywhere in 32 bit address space
1528 if ((Value
& 0x08) != 0) {
1529 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypePMem32
;
1531 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypeMem32
;
1534 PciIoDevice
->VfPciBar
[BarIndex
].Length
= (~(Value
& Mask
)) + 1;
1535 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->VfPciBar
[BarIndex
].Length
- 1;
1540 PciIoDevice
->VfPciBar
[BarIndex
].Length
= MultU64x32 (PciIoDevice
->VfPciBar
[BarIndex
].Length
, PciIoDevice
->InitialVFs
);
1544 if (PciIoDevice
->VfPciBar
[BarIndex
].Alignment
< PciIoDevice
->SystemPageSize
- 1) {
1545 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->SystemPageSize
- 1;
1551 // memory space; anywhere in 64 bit address space
1554 if ((Value
& 0x08) != 0) {
1555 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypePMem64
;
1557 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypeMem64
;
1561 // According to PCI 2.2,if the bar indicates a memory 64 decoding, next bar
1562 // is regarded as an extension for the first bar. As a result
1563 // the sizing will be conducted on combined 64 bit value
1564 // Here just store the masked first 32bit value for future size
1567 PciIoDevice
->VfPciBar
[BarIndex
].Length
= Value
& Mask
;
1568 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->VfPciBar
[BarIndex
].Length
- 1;
1570 if (PciIoDevice
->VfPciBar
[BarIndex
].Alignment
< PciIoDevice
->SystemPageSize
- 1) {
1571 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->SystemPageSize
- 1;
1575 // Increment the offset to point to next DWORD
1579 Status
= VfBarExisted (
1586 if (EFI_ERROR (Status
)) {
1591 // Fix the length to support some spefic 64 bit BAR
1593 Value
|= ((UINT32
) -1 << HighBitSet32 (Value
));
1596 // Calculate the size of 64bit bar
1598 PciIoDevice
->VfPciBar
[BarIndex
].BaseAddress
|= LShiftU64 ((UINT64
) OriginalValue
, 32);
1600 PciIoDevice
->VfPciBar
[BarIndex
].Length
= PciIoDevice
->VfPciBar
[BarIndex
].Length
| LShiftU64 ((UINT64
) Value
, 32);
1601 PciIoDevice
->VfPciBar
[BarIndex
].Length
= (~(PciIoDevice
->VfPciBar
[BarIndex
].Length
)) + 1;
1602 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->VfPciBar
[BarIndex
].Length
- 1;
1607 PciIoDevice
->VfPciBar
[BarIndex
].Length
= MultU64x32 (PciIoDevice
->VfPciBar
[BarIndex
].Length
, PciIoDevice
->InitialVFs
);
1611 if (PciIoDevice
->VfPciBar
[BarIndex
].Alignment
< PciIoDevice
->SystemPageSize
- 1) {
1612 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->SystemPageSize
- 1;
1621 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1622 PciIoDevice
->VfPciBar
[BarIndex
].Length
= (~(Value
& Mask
)) + 1;
1623 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->VfPciBar
[BarIndex
].Length
- 1;
1625 if (PciIoDevice
->VfPciBar
[BarIndex
].Alignment
< PciIoDevice
->SystemPageSize
- 1) {
1626 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->SystemPageSize
- 1;
1634 // Check the length again so as to keep compatible with some special bars
1636 if (PciIoDevice
->VfPciBar
[BarIndex
].Length
== 0) {
1637 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1638 PciIoDevice
->VfPciBar
[BarIndex
].BaseAddress
= 0;
1639 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= 0;
1643 // Increment number of bar
1649 Parse PCI bar information and fill them into PCI device instance.
1651 @param PciIoDevice Pci device instance.
1652 @param Offset Bar offset.
1653 @param BarIndex Bar index.
1655 @return Next bar offset.
1660 IN PCI_IO_DEVICE
*PciIoDevice
,
1666 UINT32 OriginalValue
;
1673 Status
= BarExisted (
1680 if (EFI_ERROR (Status
)) {
1681 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= 0;
1682 PciIoDevice
->PciBar
[BarIndex
].Length
= 0;
1683 PciIoDevice
->PciBar
[BarIndex
].Alignment
= 0;
1686 // Some devices don't fully comply to PCI spec 2.2. So be to scan all the BARs anyway
1688 PciIoDevice
->PciBar
[BarIndex
].Offset
= (UINT8
) Offset
;
1692 PciIoDevice
->PciBar
[BarIndex
].Offset
= (UINT8
) Offset
;
1693 if ((Value
& 0x01) != 0) {
1699 if ((Value
& 0xFFFF0000) != 0) {
1703 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeIo32
;
1704 PciIoDevice
->PciBar
[BarIndex
].Length
= ((~(Value
& Mask
)) + 1);
1705 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1711 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeIo16
;
1712 PciIoDevice
->PciBar
[BarIndex
].Length
= 0x0000FFFF & ((~(Value
& Mask
)) + 1);
1713 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1717 // Workaround. Some platforms inplement IO bar with 0 length
1718 // Need to treat it as no-bar
1720 if (PciIoDevice
->PciBar
[BarIndex
].Length
== 0) {
1721 PciIoDevice
->PciBar
[BarIndex
].BarType
= (PCI_BAR_TYPE
) 0;
1724 PciIoDevice
->PciBar
[BarIndex
].Prefetchable
= FALSE
;
1725 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= OriginalValue
& Mask
;
1731 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= OriginalValue
& Mask
;
1733 switch (Value
& 0x07) {
1736 //memory space; anywhere in 32 bit address space
1739 if ((Value
& 0x08) != 0) {
1740 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypePMem32
;
1742 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeMem32
;
1745 PciIoDevice
->PciBar
[BarIndex
].Length
= (~(Value
& Mask
)) + 1;
1746 if (PciIoDevice
->PciBar
[BarIndex
].Length
< (SIZE_4KB
)) {
1748 // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
1750 PciIoDevice
->PciBar
[BarIndex
].Alignment
= (SIZE_4KB
- 1);
1752 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1757 // memory space; anywhere in 64 bit address space
1760 if ((Value
& 0x08) != 0) {
1761 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypePMem64
;
1763 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeMem64
;
1767 // According to PCI 2.2,if the bar indicates a memory 64 decoding, next bar
1768 // is regarded as an extension for the first bar. As a result
1769 // the sizing will be conducted on combined 64 bit value
1770 // Here just store the masked first 32bit value for future size
1773 PciIoDevice
->PciBar
[BarIndex
].Length
= Value
& Mask
;
1774 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1777 // Increment the offset to point to next DWORD
1781 Status
= BarExisted (
1788 if (EFI_ERROR (Status
)) {
1790 // the high 32 bit does not claim any BAR, we need to re-check the low 32 bit BAR again
1792 if (PciIoDevice
->PciBar
[BarIndex
].Length
== 0) {
1794 // some device implement MMIO bar with 0 length, need to treat it as no-bar
1796 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1802 // Fix the length to support some spefic 64 bit BAR
1804 Value
|= ((UINT32
)(-1) << HighBitSet32 (Value
));
1807 // Calculate the size of 64bit bar
1809 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
|= LShiftU64 ((UINT64
) OriginalValue
, 32);
1811 PciIoDevice
->PciBar
[BarIndex
].Length
= PciIoDevice
->PciBar
[BarIndex
].Length
| LShiftU64 ((UINT64
) Value
, 32);
1812 PciIoDevice
->PciBar
[BarIndex
].Length
= (~(PciIoDevice
->PciBar
[BarIndex
].Length
)) + 1;
1813 if (PciIoDevice
->PciBar
[BarIndex
].Length
< (SIZE_4KB
)) {
1815 // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
1817 PciIoDevice
->PciBar
[BarIndex
].Alignment
= (SIZE_4KB
- 1);
1819 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1828 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1829 PciIoDevice
->PciBar
[BarIndex
].Length
= (~(Value
& Mask
)) + 1;
1830 if (PciIoDevice
->PciBar
[BarIndex
].Length
< (SIZE_4KB
)) {
1832 // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
1834 PciIoDevice
->PciBar
[BarIndex
].Alignment
= (SIZE_4KB
- 1);
1836 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1843 // Check the length again so as to keep compatible with some special bars
1845 if (PciIoDevice
->PciBar
[BarIndex
].Length
== 0) {
1846 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1847 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= 0;
1848 PciIoDevice
->PciBar
[BarIndex
].Alignment
= 0;
1852 // Increment number of bar
1858 This routine is used to initialize the bar of a PCI device.
1860 @param PciIoDevice Pci device instance.
1862 @note It can be called typically when a device is going to be rejected.
1866 InitializePciDevice (
1867 IN PCI_IO_DEVICE
*PciIoDevice
1870 EFI_PCI_IO_PROTOCOL
*PciIo
;
1873 PciIo
= &(PciIoDevice
->PciIo
);
1876 // Put all the resource apertures
1877 // Resource base is set to all ones so as to indicate its resource
1878 // has not been alloacted
1880 for (Offset
= 0x10; Offset
<= 0x24; Offset
+= sizeof (UINT32
)) {
1881 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, Offset
, 1, &gAllOne
);
1886 This routine is used to initialize the bar of a PCI-PCI Bridge device.
1888 @param PciIoDevice PCI-PCI bridge device instance.
1893 IN PCI_IO_DEVICE
*PciIoDevice
1896 EFI_PCI_IO_PROTOCOL
*PciIo
;
1898 PciIo
= &(PciIoDevice
->PciIo
);
1901 // Put all the resource apertures including IO16
1902 // Io32, pMem32, pMem64 to quiescent state
1903 // Resource base all ones, Resource limit all zeros
1905 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &gAllOne
);
1906 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1D, 1, &gAllZero
);
1908 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x20, 1, &gAllOne
);
1909 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x22, 1, &gAllZero
);
1911 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x24, 1, &gAllOne
);
1912 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x26, 1, &gAllZero
);
1914 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x28, 1, &gAllOne
);
1915 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x2C, 1, &gAllZero
);
1918 // Don't support use io32 as for now
1920 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x30, 1, &gAllOne
);
1921 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x32, 1, &gAllZero
);
1924 // Force Interrupt line to zero for cards that come up randomly
1926 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x3C, 1, &gAllZero
);
1930 This routine is used to initialize the bar of a PCI Card Bridge device.
1932 @param PciIoDevice PCI Card bridge device.
1937 IN PCI_IO_DEVICE
*PciIoDevice
1940 EFI_PCI_IO_PROTOCOL
*PciIo
;
1942 PciIo
= &(PciIoDevice
->PciIo
);
1945 // Put all the resource apertures including IO16
1946 // Io32, pMem32, pMem64 to quiescent state(
1947 // Resource base all ones, Resource limit all zeros
1949 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x1c, 1, &gAllOne
);
1950 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x20, 1, &gAllZero
);
1952 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x24, 1, &gAllOne
);
1953 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x28, 1, &gAllZero
);
1955 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x2c, 1, &gAllOne
);
1956 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x30, 1, &gAllZero
);
1958 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x34, 1, &gAllOne
);
1959 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x38, 1, &gAllZero
);
1962 // Force Interrupt line to zero for cards that come up randomly
1964 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x3C, 1, &gAllZero
);
1968 Create and initiliaze general PCI I/O device instance for
1969 PCI device/bridge device/hotplug bridge device.
1971 @param PciRootBridgeIo Pointer to instance of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1972 @param Pci Input Pci information block.
1973 @param Bus Device Bus NO.
1974 @param Device Device device NO.
1975 @param Func Device func NO.
1977 @return Instance of PCI device. NULL means no instance created.
1982 IN PCI_IO_DEVICE
*Bridge
,
1989 PCI_IO_DEVICE
*PciIoDevice
;
1990 EFI_PCI_IO_PROTOCOL
*PciIo
;
1993 PciIoDevice
= AllocateZeroPool (sizeof (PCI_IO_DEVICE
));
1994 if (PciIoDevice
== NULL
) {
1998 PciIoDevice
->Signature
= PCI_IO_DEVICE_SIGNATURE
;
1999 PciIoDevice
->Handle
= NULL
;
2000 PciIoDevice
->PciRootBridgeIo
= Bridge
->PciRootBridgeIo
;
2001 PciIoDevice
->DevicePath
= NULL
;
2002 PciIoDevice
->BusNumber
= Bus
;
2003 PciIoDevice
->DeviceNumber
= Device
;
2004 PciIoDevice
->FunctionNumber
= Func
;
2005 PciIoDevice
->Decodes
= 0;
2007 if (gFullEnumeration
) {
2008 PciIoDevice
->Allocated
= FALSE
;
2010 PciIoDevice
->Allocated
= TRUE
;
2013 PciIoDevice
->Registered
= FALSE
;
2014 PciIoDevice
->Attributes
= 0;
2015 PciIoDevice
->Supports
= 0;
2016 PciIoDevice
->BusOverride
= FALSE
;
2017 PciIoDevice
->AllOpRomProcessed
= FALSE
;
2019 PciIoDevice
->IsPciExp
= FALSE
;
2021 CopyMem (&(PciIoDevice
->Pci
), Pci
, sizeof (PCI_TYPE01
));
2024 // Initialize the PCI I/O instance structure
2026 InitializePciIoInstance (PciIoDevice
);
2027 InitializePciDriverOverrideInstance (PciIoDevice
);
2028 InitializePciLoadFile2 (PciIoDevice
);
2029 PciIo
= &PciIoDevice
->PciIo
;
2032 // Detect if PCI Express Device
2034 PciIoDevice
->PciExpressCapabilityOffset
= 0;
2035 Status
= LocateCapabilityRegBlock (
2037 EFI_PCI_CAPABILITY_ID_PCIEXP
,
2038 &PciIoDevice
->PciExpressCapabilityOffset
,
2041 if (!EFI_ERROR (Status
)) {
2042 PciIoDevice
->IsPciExp
= TRUE
;
2045 if (PcdGetBool (PcdAriSupport
)) {
2047 // Check if the device is an ARI device.
2049 Status
= LocatePciExpressCapabilityRegBlock (
2051 EFI_PCIE_CAPABILITY_ID_ARI
,
2052 &PciIoDevice
->AriCapabilityOffset
,
2055 if (!EFI_ERROR (Status
)) {
2057 // We need to enable ARI feature before calculate BusReservation,
2058 // because FirstVFOffset and VFStride may change after that.
2060 EFI_PCI_IO_PROTOCOL
*ParentPciIo
;
2064 // Check if its parent supports ARI forwarding.
2066 ParentPciIo
= &Bridge
->PciIo
;
2067 ParentPciIo
->Pci
.Read (
2069 EfiPciIoWidthUint32
,
2070 Bridge
->PciExpressCapabilityOffset
+ EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET
,
2074 if ((Data32
& EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING
) != 0) {
2076 // ARI forward support in bridge, so enable it.
2078 ParentPciIo
->Pci
.Read (
2080 EfiPciIoWidthUint32
,
2081 Bridge
->PciExpressCapabilityOffset
+ EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET
,
2085 if ((Data32
& EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING
) == 0) {
2086 Data32
|= EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING
;
2087 ParentPciIo
->Pci
.Write (
2089 EfiPciIoWidthUint32
,
2090 Bridge
->PciExpressCapabilityOffset
+ EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET
,
2096 " ARI: forwarding enabled for PPB[%02x:%02x:%02x]\n",
2098 Bridge
->DeviceNumber
,
2099 Bridge
->FunctionNumber
2104 DEBUG ((EFI_D_INFO
, " ARI: CapOffset = 0x%x\n", PciIoDevice
->AriCapabilityOffset
));
2109 // Initialization for SR-IOV
2112 if (PcdGetBool (PcdSrIovSupport
)) {
2113 Status
= LocatePciExpressCapabilityRegBlock (
2115 EFI_PCIE_CAPABILITY_ID_SRIOV
,
2116 &PciIoDevice
->SrIovCapabilityOffset
,
2119 if (!EFI_ERROR (Status
)) {
2120 UINT32 SupportedPageSize
;
2122 UINT16 FirstVFOffset
;
2128 // If the SR-IOV device is an ARI device, then Set ARI Capable Hierarchy for the device.
2130 if (PcdGetBool (PcdAriSupport
) && PciIoDevice
->AriCapabilityOffset
!= 0) {
2133 EfiPciIoWidthUint16
,
2134 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL
,
2138 Data16
|= EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY
;
2141 EfiPciIoWidthUint16
,
2142 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL
,
2149 // Calculate SystemPageSize
2154 EfiPciIoWidthUint32
,
2155 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE
,
2159 PciIoDevice
->SystemPageSize
= (PcdGet32 (PcdSrIovSystemPageSize
) & SupportedPageSize
);
2160 ASSERT (PciIoDevice
->SystemPageSize
!= 0);
2164 EfiPciIoWidthUint32
,
2165 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE
,
2167 &PciIoDevice
->SystemPageSize
2170 // Adjust SystemPageSize for Alignment usage later
2172 PciIoDevice
->SystemPageSize
<<= 12;
2175 // Calculate BusReservation for PCI IOV
2179 // Read First FirstVFOffset, InitialVFs, and VFStride
2183 EfiPciIoWidthUint16
,
2184 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF
,
2190 EfiPciIoWidthUint16
,
2191 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS
,
2193 &PciIoDevice
->InitialVFs
2197 EfiPciIoWidthUint16
,
2198 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE
,
2205 PFRid
= EFI_PCI_RID(Bus
, Device
, Func
);
2206 LastVF
= PFRid
+ FirstVFOffset
+ (PciIoDevice
->InitialVFs
- 1) * VFStride
;
2209 // Calculate ReservedBusNum for this PF
2211 PciIoDevice
->ReservedBusNum
= (UINT16
)(EFI_PCI_BUS_OF_RID (LastVF
) - Bus
+ 1);
2215 " SR-IOV: SupportedPageSize = 0x%x; SystemPageSize = 0x%x; FirstVFOffset = 0x%x;\n",
2216 SupportedPageSize
, PciIoDevice
->SystemPageSize
>> 12, FirstVFOffset
2220 " InitialVFs = 0x%x; ReservedBusNum = 0x%x; CapOffset = 0x%x\n",
2221 PciIoDevice
->InitialVFs
, PciIoDevice
->ReservedBusNum
, PciIoDevice
->SrIovCapabilityOffset
2226 if (PcdGetBool (PcdMrIovSupport
)) {
2227 Status
= LocatePciExpressCapabilityRegBlock (
2229 EFI_PCIE_CAPABILITY_ID_MRIOV
,
2230 &PciIoDevice
->MrIovCapabilityOffset
,
2233 if (!EFI_ERROR (Status
)) {
2234 DEBUG ((EFI_D_INFO
, " MR-IOV: CapOffset = 0x%x\n", PciIoDevice
->MrIovCapabilityOffset
));
2239 // Initialize the reserved resource list
2241 InitializeListHead (&PciIoDevice
->ReservedResourceList
);
2244 // Initialize the driver list
2246 InitializeListHead (&PciIoDevice
->OptionRomDriverList
);
2249 // Initialize the child list
2251 InitializeListHead (&PciIoDevice
->ChildList
);
2257 This routine is used to enumerate entire pci bus system
2258 in a given platform.
2260 It is only called on the second start on the same Root Bridge.
2262 @param Controller Parent bridge handler.
2264 @retval EFI_SUCCESS PCI enumeration finished successfully.
2265 @retval other Some error occurred when enumerating the pci bus system.
2269 PciEnumeratorLight (
2270 IN EFI_HANDLE Controller
2275 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
2276 PCI_IO_DEVICE
*RootBridgeDev
;
2279 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
2282 MaxBus
= PCI_MAX_BUS
;
2286 // If this root bridge has been already enumerated, then return successfully
2288 if (GetRootBridgeByHandle (Controller
) != NULL
) {
2293 // Open pci root bridge io protocol
2295 Status
= gBS
->OpenProtocol (
2297 &gEfiPciRootBridgeIoProtocolGuid
,
2298 (VOID
**) &PciRootBridgeIo
,
2299 gPciBusDriverBinding
.DriverBindingHandle
,
2301 EFI_OPEN_PROTOCOL_BY_DRIVER
2303 if (EFI_ERROR (Status
) && Status
!= EFI_ALREADY_STARTED
) {
2307 Status
= PciRootBridgeIo
->Configuration (PciRootBridgeIo
, (VOID
**) &Descriptors
);
2309 if (EFI_ERROR (Status
)) {
2313 while (PciGetBusRange (&Descriptors
, &MinBus
, &MaxBus
, NULL
) == EFI_SUCCESS
) {
2316 // Create a device node for root bridge device with a NULL host bridge controller handle
2318 RootBridgeDev
= CreateRootBridge (Controller
);
2320 if (RootBridgeDev
== NULL
) {
2326 // Record the root bridgeio protocol
2328 RootBridgeDev
->PciRootBridgeIo
= PciRootBridgeIo
;
2330 Status
= PciPciDeviceInfoCollector (
2335 if (!EFI_ERROR (Status
)) {
2338 // Remove those PCI devices which are rejected when full enumeration
2340 RemoveRejectedPciDevices (RootBridgeDev
->Handle
, RootBridgeDev
);
2343 // Process option rom light
2345 ProcessOptionRomLight (RootBridgeDev
);
2348 // Determine attributes for all devices under this root bridge
2350 DetermineDeviceAttribute (RootBridgeDev
);
2353 // If successfully, insert the node into device pool
2355 InsertRootBridge (RootBridgeDev
);
2359 // If unsuccessly, destroy the entire node
2361 DestroyRootBridge (RootBridgeDev
);
2371 Get bus range from PCI resource descriptor list.
2373 @param Descriptors A pointer to the address space descriptor.
2374 @param MinBus The min bus returned.
2375 @param MaxBus The max bus returned.
2376 @param BusRange The bus range returned.
2378 @retval EFI_SUCCESS Successfully got bus range.
2379 @retval EFI_NOT_FOUND Can not find the specific bus.
2384 IN EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
,
2387 OUT UINT16
*BusRange
2390 while ((*Descriptors
)->Desc
!= ACPI_END_TAG_DESCRIPTOR
) {
2391 if ((*Descriptors
)->ResType
== ACPI_ADDRESS_SPACE_TYPE_BUS
) {
2392 if (MinBus
!= NULL
) {
2393 *MinBus
= (UINT16
) (*Descriptors
)->AddrRangeMin
;
2396 if (MaxBus
!= NULL
) {
2397 *MaxBus
= (UINT16
) (*Descriptors
)->AddrRangeMax
;
2400 if (BusRange
!= NULL
) {
2401 *BusRange
= (UINT16
) (*Descriptors
)->AddrLen
;
2410 return EFI_NOT_FOUND
;
2414 This routine can be used to start the root bridge.
2416 @param RootBridgeDev Pci device instance.
2418 @retval EFI_SUCCESS This device started.
2419 @retval other Failed to get PCI Root Bridge I/O protocol.
2423 StartManagingRootBridge (
2424 IN PCI_IO_DEVICE
*RootBridgeDev
2427 EFI_HANDLE RootBridgeHandle
;
2429 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
2432 // Get the root bridge handle
2434 RootBridgeHandle
= RootBridgeDev
->Handle
;
2435 PciRootBridgeIo
= NULL
;
2438 // Get the pci root bridge io protocol
2440 Status
= gBS
->OpenProtocol (
2442 &gEfiPciRootBridgeIoProtocolGuid
,
2443 (VOID
**) &PciRootBridgeIo
,
2444 gPciBusDriverBinding
.DriverBindingHandle
,
2446 EFI_OPEN_PROTOCOL_BY_DRIVER
2449 if (EFI_ERROR (Status
) && Status
!= EFI_ALREADY_STARTED
) {
2454 // Store the PciRootBridgeIo protocol into root bridge private data
2456 RootBridgeDev
->PciRootBridgeIo
= PciRootBridgeIo
;
2463 This routine can be used to check whether a PCI device should be rejected when light enumeration.
2465 @param PciIoDevice Pci device instance.
2467 @retval TRUE This device should be rejected.
2468 @retval FALSE This device shouldn't be rejected.
2472 IsPciDeviceRejected (
2473 IN PCI_IO_DEVICE
*PciIoDevice
2483 // PPB should be skip!
2485 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
)) {
2489 if (IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
2491 // Only test base registers for P2C
2493 for (BarOffset
= 0x1C; BarOffset
<= 0x38; BarOffset
+= 2 * sizeof (UINT32
)) {
2495 Mask
= (BarOffset
< 0x2C) ? 0xFFFFF000 : 0xFFFFFFFC;
2496 Status
= BarExisted (PciIoDevice
, BarOffset
, &TestValue
, &OldValue
);
2497 if (EFI_ERROR (Status
)) {
2501 TestValue
= TestValue
& Mask
;
2502 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2504 // The bar isn't programed, so it should be rejected
2513 for (BarOffset
= 0x14; BarOffset
<= 0x24; BarOffset
+= sizeof (UINT32
)) {
2517 Status
= BarExisted (PciIoDevice
, BarOffset
, &TestValue
, &OldValue
);
2518 if (EFI_ERROR (Status
)) {
2522 if ((TestValue
& 0x01) != 0) {
2528 TestValue
= TestValue
& Mask
;
2529 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2539 TestValue
= TestValue
& Mask
;
2541 if ((TestValue
& 0x07) == 0x04) {
2546 BarOffset
+= sizeof (UINT32
);
2547 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2550 // Test its high 32-Bit BAR
2552 Status
= BarExisted (PciIoDevice
, BarOffset
, &TestValue
, &OldValue
);
2553 if (TestValue
== OldValue
) {
2563 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2574 Reset all bus number from specific bridge.
2576 @param Bridge Parent specific bridge.
2577 @param StartBusNumber Start bus number.
2581 ResetAllPpbBusNumber (
2582 IN PCI_IO_DEVICE
*Bridge
,
2583 IN UINT8 StartBusNumber
2593 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
2595 PciRootBridgeIo
= Bridge
->PciRootBridgeIo
;
2597 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
2598 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
2601 // Check to see whether a pci device is present
2603 Status
= PciDevicePresent (
2611 if (!EFI_ERROR (Status
) && (IS_PCI_BRIDGE (&Pci
))) {
2614 Address
= EFI_PCI_ADDRESS (StartBusNumber
, Device
, Func
, 0x18);
2615 Status
= PciRootBridgeIo
->Pci
.Read (
2622 SecondaryBus
= (UINT8
)(Register
>> 8);
2624 if (SecondaryBus
!= 0) {
2625 ResetAllPpbBusNumber (Bridge
, SecondaryBus
);
2629 // Reset register 18h, 19h, 1Ah on PCI Bridge
2631 Register
&= 0xFF000000;
2632 Status
= PciRootBridgeIo
->Pci
.Write (
2641 if (Func
== 0 && !IS_PCI_MULTI_FUNC (&Pci
)) {
2643 // Skip sub functions, this is not a multi function device
2645 Func
= PCI_MAX_FUNC
;