3 PCI Root Bridge Io Protocol code.
5 Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #include "PciHostBridge.h"
17 #include "PciRootBridge.h"
18 #include "PciHostResource.h"
20 #define NO_MAPPING (VOID *) (UINTN) -1
22 #define RESOURCE_VALID(Resource) ((Resource)->Base <= (Resource)->Limit)
25 // Lookup table for increment values based on transfer widths
28 1, // EfiPciWidthUint8
29 2, // EfiPciWidthUint16
30 4, // EfiPciWidthUint32
31 8, // EfiPciWidthUint64
32 0, // EfiPciWidthFifoUint8
33 0, // EfiPciWidthFifoUint16
34 0, // EfiPciWidthFifoUint32
35 0, // EfiPciWidthFifoUint64
36 1, // EfiPciWidthFillUint8
37 2, // EfiPciWidthFillUint16
38 4, // EfiPciWidthFillUint32
39 8 // EfiPciWidthFillUint64
43 // Lookup table for increment values based on transfer widths
45 UINT8 mOutStride
[] = {
46 1, // EfiPciWidthUint8
47 2, // EfiPciWidthUint16
48 4, // EfiPciWidthUint32
49 8, // EfiPciWidthUint64
50 1, // EfiPciWidthFifoUint8
51 2, // EfiPciWidthFifoUint16
52 4, // EfiPciWidthFifoUint32
53 8, // EfiPciWidthFifoUint64
54 0, // EfiPciWidthFillUint8
55 0, // EfiPciWidthFillUint16
56 0, // EfiPciWidthFillUint32
57 0 // EfiPciWidthFillUint64
61 Construct the Pci Root Bridge instance.
63 @param Bridge The root bridge instance.
65 @return The pointer to PCI_ROOT_BRIDGE_INSTANCE just created
66 or NULL if creation fails.
68 PCI_ROOT_BRIDGE_INSTANCE
*
70 IN PCI_ROOT_BRIDGE
*Bridge
73 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
74 PCI_RESOURCE_TYPE Index
;
75 CHAR16
*DevicePathStr
;
76 PCI_ROOT_BRIDGE_APERTURE
*Aperture
;
80 DEBUG ((EFI_D_INFO
, "RootBridge: "));
81 DEBUG ((EFI_D_INFO
, "%s\n", DevicePathStr
= ConvertDevicePathToText (Bridge
->DevicePath
, FALSE
, FALSE
)));
82 DEBUG ((EFI_D_INFO
, " Support/Attr: %lx / %lx\n", Bridge
->Supports
, Bridge
->Attributes
));
83 DEBUG ((EFI_D_INFO
, " DmaAbove4G: %s\n", Bridge
->DmaAbove4G
? L
"Yes" : L
"No"));
84 DEBUG ((EFI_D_INFO
, "NoExtConfSpace: %s\n", Bridge
->NoExtendedConfigSpace
? L
"Yes" : L
"No"));
85 DEBUG ((EFI_D_INFO
, " AllocAttr: %lx (%s%s)\n", Bridge
->AllocationAttributes
,
86 (Bridge
->AllocationAttributes
& EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM
) != 0 ? L
"CombineMemPMem " : L
"",
87 (Bridge
->AllocationAttributes
& EFI_PCI_HOST_BRIDGE_MEM64_DECODE
) != 0 ? L
"Mem64Decode" : L
""
90 EFI_D_INFO
, " Bus: %lx - %lx Translation=%lx\n",
91 Bridge
->Bus
.Base
, Bridge
->Bus
.Limit
, Bridge
->Bus
.Translation
94 // Translation for bus is not supported.
96 ASSERT (Bridge
->Bus
.Translation
== 0);
97 if (Bridge
->Bus
.Translation
!= 0) {
102 DEBUG_INFO
, " Io: %lx - %lx Translation=%lx\n",
103 Bridge
->Io
.Base
, Bridge
->Io
.Limit
, Bridge
->Io
.Translation
106 DEBUG_INFO
, " Mem: %lx - %lx Translation=%lx\n",
107 Bridge
->Mem
.Base
, Bridge
->Mem
.Limit
, Bridge
->Mem
.Translation
110 DEBUG_INFO
, " MemAbove4G: %lx - %lx Translation=%lx\n",
111 Bridge
->MemAbove4G
.Base
, Bridge
->MemAbove4G
.Limit
, Bridge
->MemAbove4G
.Translation
114 DEBUG_INFO
, " PMem: %lx - %lx Translation=%lx\n",
115 Bridge
->PMem
.Base
, Bridge
->PMem
.Limit
, Bridge
->PMem
.Translation
118 DEBUG_INFO
, " PMemAbove4G: %lx - %lx Translation=%lx\n",
119 Bridge
->PMemAbove4G
.Base
, Bridge
->PMemAbove4G
.Limit
, Bridge
->PMemAbove4G
.Translation
123 // Make sure Mem and MemAbove4G apertures are valid
125 if (RESOURCE_VALID (&Bridge
->Mem
)) {
126 ASSERT (Bridge
->Mem
.Limit
< SIZE_4GB
);
127 if (Bridge
->Mem
.Limit
>= SIZE_4GB
) {
131 if (RESOURCE_VALID (&Bridge
->MemAbove4G
)) {
132 ASSERT (Bridge
->MemAbove4G
.Base
>= SIZE_4GB
);
133 if (Bridge
->MemAbove4G
.Base
< SIZE_4GB
) {
137 if (RESOURCE_VALID (&Bridge
->PMem
)) {
138 ASSERT (Bridge
->PMem
.Limit
< SIZE_4GB
);
139 if (Bridge
->PMem
.Limit
>= SIZE_4GB
) {
143 if (RESOURCE_VALID (&Bridge
->PMemAbove4G
)) {
144 ASSERT (Bridge
->PMemAbove4G
.Base
>= SIZE_4GB
);
145 if (Bridge
->PMemAbove4G
.Base
< SIZE_4GB
) {
151 // Ignore AllocationAttributes when resources were already assigned.
153 if (!Bridge
->ResourceAssigned
) {
154 if ((Bridge
->AllocationAttributes
& EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM
) != 0) {
156 // If this bit is set, then the PCI Root Bridge does not
157 // support separate windows for Non-prefetchable and Prefetchable
160 ASSERT (!RESOURCE_VALID (&Bridge
->PMem
));
161 ASSERT (!RESOURCE_VALID (&Bridge
->PMemAbove4G
));
162 if (RESOURCE_VALID (&Bridge
->PMem
) || RESOURCE_VALID (&Bridge
->PMemAbove4G
)) {
167 if ((Bridge
->AllocationAttributes
& EFI_PCI_HOST_BRIDGE_MEM64_DECODE
) == 0) {
169 // If this bit is not set, then the PCI Root Bridge does not support
170 // 64 bit memory windows.
172 ASSERT (!RESOURCE_VALID (&Bridge
->MemAbove4G
));
173 ASSERT (!RESOURCE_VALID (&Bridge
->PMemAbove4G
));
174 if (RESOURCE_VALID (&Bridge
->MemAbove4G
) || RESOURCE_VALID (&Bridge
->PMemAbove4G
)) {
180 RootBridge
= AllocateZeroPool (sizeof (PCI_ROOT_BRIDGE_INSTANCE
));
181 ASSERT (RootBridge
!= NULL
);
183 RootBridge
->Signature
= PCI_ROOT_BRIDGE_SIGNATURE
;
184 RootBridge
->Supports
= Bridge
->Supports
;
185 RootBridge
->Attributes
= Bridge
->Attributes
;
186 RootBridge
->DmaAbove4G
= Bridge
->DmaAbove4G
;
187 RootBridge
->NoExtendedConfigSpace
= Bridge
->NoExtendedConfigSpace
;
188 RootBridge
->AllocationAttributes
= Bridge
->AllocationAttributes
;
189 RootBridge
->DevicePath
= DuplicateDevicePath (Bridge
->DevicePath
);
190 RootBridge
->DevicePathStr
= DevicePathStr
;
191 RootBridge
->ConfigBuffer
= AllocatePool (
192 TypeMax
* sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR
)
194 ASSERT (RootBridge
->ConfigBuffer
!= NULL
);
195 InitializeListHead (&RootBridge
->Maps
);
197 CopyMem (&RootBridge
->Bus
, &Bridge
->Bus
, sizeof (PCI_ROOT_BRIDGE_APERTURE
));
198 CopyMem (&RootBridge
->Io
, &Bridge
->Io
, sizeof (PCI_ROOT_BRIDGE_APERTURE
));
199 CopyMem (&RootBridge
->Mem
, &Bridge
->Mem
, sizeof (PCI_ROOT_BRIDGE_APERTURE
));
200 CopyMem (&RootBridge
->MemAbove4G
, &Bridge
->MemAbove4G
, sizeof (PCI_ROOT_BRIDGE_APERTURE
));
201 CopyMem (&RootBridge
->PMem
, &Bridge
->PMem
, sizeof (PCI_ROOT_BRIDGE_APERTURE
));
202 CopyMem (&RootBridge
->PMemAbove4G
, &Bridge
->PMemAbove4G
, sizeof (PCI_ROOT_BRIDGE_APERTURE
));
204 for (Index
= TypeIo
; Index
< TypeMax
; Index
++) {
207 Aperture
= &RootBridge
->Bus
;
210 Aperture
= &RootBridge
->Io
;
213 Aperture
= &RootBridge
->Mem
;
216 Aperture
= &RootBridge
->MemAbove4G
;
219 Aperture
= &RootBridge
->PMem
;
222 Aperture
= &RootBridge
->PMemAbove4G
;
229 RootBridge
->ResAllocNode
[Index
].Type
= Index
;
230 if (Bridge
->ResourceAssigned
&& (Aperture
->Limit
>= Aperture
->Base
)) {
232 // Base in ResAllocNode is a host address, while Base in Aperture is a
235 RootBridge
->ResAllocNode
[Index
].Base
= TO_HOST_ADDRESS (Aperture
->Base
,
236 Aperture
->Translation
);
237 RootBridge
->ResAllocNode
[Index
].Length
= Aperture
->Limit
- Aperture
->Base
+ 1;
238 RootBridge
->ResAllocNode
[Index
].Status
= ResAllocated
;
240 RootBridge
->ResAllocNode
[Index
].Base
= 0;
241 RootBridge
->ResAllocNode
[Index
].Length
= 0;
242 RootBridge
->ResAllocNode
[Index
].Status
= ResNone
;
246 RootBridge
->RootBridgeIo
.SegmentNumber
= Bridge
->Segment
;
247 RootBridge
->RootBridgeIo
.PollMem
= RootBridgeIoPollMem
;
248 RootBridge
->RootBridgeIo
.PollIo
= RootBridgeIoPollIo
;
249 RootBridge
->RootBridgeIo
.Mem
.Read
= RootBridgeIoMemRead
;
250 RootBridge
->RootBridgeIo
.Mem
.Write
= RootBridgeIoMemWrite
;
251 RootBridge
->RootBridgeIo
.Io
.Read
= RootBridgeIoIoRead
;
252 RootBridge
->RootBridgeIo
.Io
.Write
= RootBridgeIoIoWrite
;
253 RootBridge
->RootBridgeIo
.CopyMem
= RootBridgeIoCopyMem
;
254 RootBridge
->RootBridgeIo
.Pci
.Read
= RootBridgeIoPciRead
;
255 RootBridge
->RootBridgeIo
.Pci
.Write
= RootBridgeIoPciWrite
;
256 RootBridge
->RootBridgeIo
.Map
= RootBridgeIoMap
;
257 RootBridge
->RootBridgeIo
.Unmap
= RootBridgeIoUnmap
;
258 RootBridge
->RootBridgeIo
.AllocateBuffer
= RootBridgeIoAllocateBuffer
;
259 RootBridge
->RootBridgeIo
.FreeBuffer
= RootBridgeIoFreeBuffer
;
260 RootBridge
->RootBridgeIo
.Flush
= RootBridgeIoFlush
;
261 RootBridge
->RootBridgeIo
.GetAttributes
= RootBridgeIoGetAttributes
;
262 RootBridge
->RootBridgeIo
.SetAttributes
= RootBridgeIoSetAttributes
;
263 RootBridge
->RootBridgeIo
.Configuration
= RootBridgeIoConfiguration
;
269 Check parameters for IO,MMIO,PCI read/write services of PCI Root Bridge IO.
271 The I/O operations are carried out exactly as requested. The caller is
272 responsible for satisfying any alignment and I/O width restrictions that a PI
273 System on a platform might require. For example on some platforms, width
274 requests of EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other
275 hand, will be handled by the driver.
277 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
279 @param[in] OperationType I/O operation type: IO/MMIO/PCI.
281 @param[in] Width Signifies the width of the I/O or Memory operation.
283 @param[in] Address The base address of the I/O operation.
285 @param[in] Count The number of I/O operations to perform. The number
286 of bytes moved is Width size * Count, starting at
289 @param[in] Buffer For read operations, the destination buffer to
290 store the results. For write operations, the source
291 buffer from which to write data.
293 @retval EFI_SUCCESS The parameters for this request pass the
296 @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
298 @retval EFI_INVALID_PARAMETER Buffer is NULL.
300 @retval EFI_INVALID_PARAMETER Address or Count is invalid.
302 @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
304 @retval EFI_UNSUPPORTED The address range specified by Address, Width,
305 and Count is not valid for this PI system.
308 RootBridgeIoCheckParameter (
309 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
310 IN OPERATION_TYPE OperationType
,
311 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
317 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
318 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS
*PciRbAddr
;
325 // Check to see if Buffer is NULL
327 if (Buffer
== NULL
) {
328 return EFI_INVALID_PARAMETER
;
332 // Check to see if Width is in the valid range
334 if ((UINT32
) Width
>= EfiPciWidthMaximum
) {
335 return EFI_INVALID_PARAMETER
;
339 // For FIFO type, the device address won't increase during the access,
340 // so treat Count as 1
342 if (Width
>= EfiPciWidthFifoUint8
&& Width
<= EfiPciWidthFifoUint64
) {
346 Width
= (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
) (Width
& 0x03);
350 // Make sure (Count * Size) doesn't exceed MAX_UINT64
352 if (Count
> DivU64x32 (MAX_UINT64
, Size
)) {
353 return EFI_INVALID_PARAMETER
;
357 // Check to see if Address is aligned
359 if ((Address
& (Size
- 1)) != 0) {
360 return EFI_UNSUPPORTED
;
364 // Make sure (Address + Count * Size) doesn't exceed MAX_UINT64
366 Length
= MultU64x32 (Count
, Size
);
367 if (Address
> MAX_UINT64
- Length
) {
368 return EFI_INVALID_PARAMETER
;
371 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
374 // Check to see if any address associated with this transfer exceeds the
375 // maximum allowed address. The maximum address implied by the parameters
376 // passed in is Address + Size * Count. If the following condition is met,
377 // then the transfer is not supported.
379 // Address + Size * Count > Limit + 1
381 // Since Limit can be the maximum integer value supported by the CPU and
382 // Count can also be the maximum integer value supported by the CPU, this
383 // range check must be adjusted to avoid all oveflow conditions.
385 if (OperationType
== IoOperation
) {
387 // Allow Legacy IO access
389 if (Address
+ Length
<= 0x1000) {
390 if ((RootBridge
->Attributes
& (
391 EFI_PCI_ATTRIBUTE_ISA_IO
| EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO
| EFI_PCI_ATTRIBUTE_VGA_IO
|
392 EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO
| EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO
|
393 EFI_PCI_ATTRIBUTE_ISA_IO_16
| EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16
| EFI_PCI_ATTRIBUTE_VGA_IO_16
)) != 0) {
397 Base
= RootBridge
->Io
.Base
;
398 Limit
= RootBridge
->Io
.Limit
;
399 } else if (OperationType
== MemOperation
) {
401 // Allow Legacy MMIO access
403 if ((Address
>= 0xA0000) && (Address
+ Length
) <= 0xC0000) {
404 if ((RootBridge
->Attributes
& EFI_PCI_ATTRIBUTE_VGA_MEMORY
) != 0) {
409 // By comparing the Address against Limit we know which range to be used
412 if ((Address
>= RootBridge
->Mem
.Base
) && (Address
+ Length
<= RootBridge
->Mem
.Limit
+ 1)) {
413 Base
= RootBridge
->Mem
.Base
;
414 Limit
= RootBridge
->Mem
.Limit
;
415 } else if ((Address
>= RootBridge
->PMem
.Base
) && (Address
+ Length
<= RootBridge
->PMem
.Limit
+ 1)) {
416 Base
= RootBridge
->PMem
.Base
;
417 Limit
= RootBridge
->PMem
.Limit
;
418 } else if ((Address
>= RootBridge
->MemAbove4G
.Base
) && (Address
+ Length
<= RootBridge
->MemAbove4G
.Limit
+ 1)) {
419 Base
= RootBridge
->MemAbove4G
.Base
;
420 Limit
= RootBridge
->MemAbove4G
.Limit
;
422 Base
= RootBridge
->PMemAbove4G
.Base
;
423 Limit
= RootBridge
->PMemAbove4G
.Limit
;
426 PciRbAddr
= (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS
*) &Address
;
427 if (PciRbAddr
->Bus
< RootBridge
->Bus
.Base
||
428 PciRbAddr
->Bus
> RootBridge
->Bus
.Limit
) {
429 return EFI_INVALID_PARAMETER
;
432 if (PciRbAddr
->Device
> PCI_MAX_DEVICE
||
433 PciRbAddr
->Function
> PCI_MAX_FUNC
) {
434 return EFI_INVALID_PARAMETER
;
437 if (PciRbAddr
->ExtendedRegister
!= 0) {
438 Address
= PciRbAddr
->ExtendedRegister
;
440 Address
= PciRbAddr
->Register
;
443 Limit
= RootBridge
->NoExtendedConfigSpace
? 0xFF : 0xFFF;
446 if (Address
< Base
) {
447 return EFI_INVALID_PARAMETER
;
450 if (Address
+ Length
> Limit
+ 1) {
451 return EFI_INVALID_PARAMETER
;
458 Use address to match apertures of memory type and then get the corresponding
461 @param RootBridge The root bridge instance.
462 @param Address The address used to match aperture.
463 @param Translation Pointer containing the output translation.
465 @return EFI_SUCCESS Get translation successfully.
466 @return EFI_INVALID_PARAMETER No matched memory aperture; the input Address
470 RootBridgeIoGetMemTranslationByAddress (
471 IN PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
,
473 IN OUT UINT64
*Translation
476 if (Address
>= RootBridge
->Mem
.Base
&& Address
<= RootBridge
->Mem
.Limit
) {
477 *Translation
= RootBridge
->Mem
.Translation
;
478 } else if (Address
>= RootBridge
->PMem
.Base
&& Address
<= RootBridge
->PMem
.Limit
) {
479 *Translation
= RootBridge
->PMem
.Translation
;
480 } else if (Address
>= RootBridge
->MemAbove4G
.Base
&& Address
<= RootBridge
->MemAbove4G
.Limit
) {
481 *Translation
= RootBridge
->MemAbove4G
.Translation
;
482 } else if (Address
>= RootBridge
->PMemAbove4G
.Base
&& Address
<= RootBridge
->PMemAbove4G
.Limit
) {
483 *Translation
= RootBridge
->PMemAbove4G
.Translation
;
485 return EFI_INVALID_PARAMETER
;
492 Return the result of (Multiplicand * Multiplier / Divisor).
494 @param Multiplicand A 64-bit unsigned value.
495 @param Multiplier A 64-bit unsigned value.
496 @param Divisor A 32-bit unsigned value.
497 @param Remainder A pointer to a 32-bit unsigned value. This parameter is
498 optional and may be NULL.
500 @return Multiplicand * Multiplier / Divisor.
503 MultThenDivU64x64x32 (
504 IN UINT64 Multiplicand
,
505 IN UINT64 Multiplier
,
507 OUT UINT32
*Remainder OPTIONAL
511 UINT32 LocalRemainder
;
513 if (Multiplicand
> DivU64x64Remainder (MAX_UINT64
, Multiplier
, NULL
)) {
515 // Make sure Multiplicand is the bigger one.
517 if (Multiplicand
< Multiplier
) {
518 Uint64
= Multiplicand
;
519 Multiplicand
= Multiplier
;
523 // Because Multiplicand * Multiplier overflows,
524 // Multiplicand * Multiplier / Divisor
525 // = (2 * Multiplicand' + 1) * Multiplier / Divisor
526 // = 2 * (Multiplicand' * Multiplier / Divisor) + Multiplier / Divisor
528 Uint64
= MultThenDivU64x64x32 (RShiftU64 (Multiplicand
, 1), Multiplier
, Divisor
, &LocalRemainder
);
529 Uint64
= LShiftU64 (Uint64
, 1);
531 if ((Multiplicand
& 0x1) == 1) {
532 Uint64
+= DivU64x32Remainder (Multiplier
, Divisor
, &Uint32
);
534 return Uint64
+ DivU64x32Remainder (Uint32
+ LShiftU64 (LocalRemainder
, 1), Divisor
, Remainder
);
536 return DivU64x32Remainder (MultU64x64 (Multiplicand
, Multiplier
), Divisor
, Remainder
);
541 Return the elapsed tick count from CurrentTick.
543 @param CurrentTick On input, the previous tick count.
544 On output, the current tick count.
545 @param StartTick The value the performance counter starts with when it
547 @param EndTick The value that the performance counter ends with before
550 @return The elapsed tick count from CurrentTick.
561 PreviousTick
= *CurrentTick
;
562 *CurrentTick
= GetPerformanceCounter();
563 if (StartTick
< EndTick
) {
564 return *CurrentTick
- PreviousTick
;
566 return PreviousTick
- *CurrentTick
;
571 Polls an address in memory mapped I/O space until an exit condition is met,
574 This function provides a standard way to poll a PCI memory location. A PCI
575 memory read operation is performed at the PCI memory address specified by
576 Address for the width specified by Width. The result of this PCI memory read
577 operation is stored in Result. This PCI memory read operation is repeated
578 until either a timeout of Delay 100 ns units has expired, or (Result & Mask)
581 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
582 @param[in] Width Signifies the width of the memory operations.
583 @param[in] Address The base address of the memory operations. The caller
584 is responsible for aligning Address if required.
585 @param[in] Mask Mask used for the polling criteria. Bytes above Width
586 in Mask are ignored. The bits in the bytes below Width
587 which are zero in Mask are ignored when polling the
589 @param[in] Value The comparison value used for the polling exit
591 @param[in] Delay The number of 100 ns units to poll. Note that timer
592 available may be of poorer granularity.
593 @param[out] Result Pointer to the last value read from the memory
596 @retval EFI_SUCCESS The last data returned from the access matched
597 the poll exit criteria.
598 @retval EFI_INVALID_PARAMETER Width is invalid.
599 @retval EFI_INVALID_PARAMETER Result is NULL.
600 @retval EFI_TIMEOUT Delay expired before a match occurred.
601 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
606 RootBridgeIoPollMem (
607 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
608 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
617 UINT64 NumberOfTicks
;
625 if (Result
== NULL
) {
626 return EFI_INVALID_PARAMETER
;
629 if ((UINT32
)Width
> EfiPciWidthUint64
) {
630 return EFI_INVALID_PARAMETER
;
634 // No matter what, always do a single poll.
636 Status
= This
->Mem
.Read (This
, Width
, Address
, 1, Result
);
637 if (EFI_ERROR (Status
)) {
641 if ((*Result
& Mask
) == Value
) {
650 // NumberOfTicks = Frenquency * Delay / EFI_TIMER_PERIOD_SECONDS(1)
652 Frequency
= GetPerformanceCounterProperties (&StartTick
, &EndTick
);
653 NumberOfTicks
= MultThenDivU64x64x32 (Frequency
, Delay
, (UINT32
)EFI_TIMER_PERIOD_SECONDS(1), &Remainder
);
654 if (Remainder
>= (UINTN
)EFI_TIMER_PERIOD_SECONDS(1) / 2) {
657 for ( ElapsedTick
= 0, CurrentTick
= GetPerformanceCounter()
658 ; ElapsedTick
<= NumberOfTicks
659 ; ElapsedTick
+= GetElapsedTick (&CurrentTick
, StartTick
, EndTick
)
661 Status
= This
->Mem
.Read (This
, Width
, Address
, 1, Result
);
662 if (EFI_ERROR (Status
)) {
666 if ((*Result
& Mask
) == Value
) {
675 Reads from the I/O space of a PCI Root Bridge. Returns when either the
676 polling exit criteria is satisfied or after a defined duration.
678 This function provides a standard way to poll a PCI I/O location. A PCI I/O
679 read operation is performed at the PCI I/O address specified by Address for
680 the width specified by Width.
681 The result of this PCI I/O read operation is stored in Result. This PCI I/O
682 read operation is repeated until either a timeout of Delay 100 ns units has
683 expired, or (Result & Mask) is equal to Value.
685 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
686 @param[in] Width Signifies the width of the I/O operations.
687 @param[in] Address The base address of the I/O operations. The caller is
688 responsible for aligning Address if required.
689 @param[in] Mask Mask used for the polling criteria. Bytes above Width in
690 Mask are ignored. The bits in the bytes below Width
691 which are zero in Mask are ignored when polling the I/O
693 @param[in] Value The comparison value used for the polling exit criteria.
694 @param[in] Delay The number of 100 ns units to poll. Note that timer
695 available may be of poorer granularity.
696 @param[out] Result Pointer to the last value read from the memory location.
698 @retval EFI_SUCCESS The last data returned from the access matched
699 the poll exit criteria.
700 @retval EFI_INVALID_PARAMETER Width is invalid.
701 @retval EFI_INVALID_PARAMETER Result is NULL.
702 @retval EFI_TIMEOUT Delay expired before a match occurred.
703 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
709 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
710 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
719 UINT64 NumberOfTicks
;
728 // No matter what, always do a single poll.
731 if (Result
== NULL
) {
732 return EFI_INVALID_PARAMETER
;
735 if ((UINT32
)Width
> EfiPciWidthUint64
) {
736 return EFI_INVALID_PARAMETER
;
739 Status
= This
->Io
.Read (This
, Width
, Address
, 1, Result
);
740 if (EFI_ERROR (Status
)) {
743 if ((*Result
& Mask
) == Value
) {
752 // NumberOfTicks = Frenquency * Delay / EFI_TIMER_PERIOD_SECONDS(1)
754 Frequency
= GetPerformanceCounterProperties (&StartTick
, &EndTick
);
755 NumberOfTicks
= MultThenDivU64x64x32 (Frequency
, Delay
, (UINT32
)EFI_TIMER_PERIOD_SECONDS(1), &Remainder
);
756 if (Remainder
>= (UINTN
)EFI_TIMER_PERIOD_SECONDS(1) / 2) {
759 for ( ElapsedTick
= 0, CurrentTick
= GetPerformanceCounter()
760 ; ElapsedTick
<= NumberOfTicks
761 ; ElapsedTick
+= GetElapsedTick (&CurrentTick
, StartTick
, EndTick
)
763 Status
= This
->Io
.Read (This
, Width
, Address
, 1, Result
);
764 if (EFI_ERROR (Status
)) {
768 if ((*Result
& Mask
) == Value
) {
777 Enables a PCI driver to access PCI controller registers in the PCI root
780 The Mem.Read(), and Mem.Write() functions enable a driver to access PCI
781 controller registers in the PCI root bridge memory space.
782 The memory operations are carried out exactly as requested. The caller is
783 responsible for satisfying any alignment and memory width restrictions that a
784 PCI Root Bridge on a platform might require.
786 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
787 @param[in] Width Signifies the width of the memory operation.
788 @param[in] Address The base address of the memory operation. The caller
789 is responsible for aligning the Address if required.
790 @param[in] Count The number of memory operations to perform. Bytes
791 moved is Width size * Count, starting at Address.
792 @param[out] Buffer For read operations, the destination buffer to store
793 the results. For write operations, the source buffer
796 @retval EFI_SUCCESS The data was read from or written to the PCI
798 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
799 @retval EFI_INVALID_PARAMETER Buffer is NULL.
800 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
805 RootBridgeIoMemRead (
806 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
807 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
814 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
817 Status
= RootBridgeIoCheckParameter (This
, MemOperation
, Width
, Address
,
819 if (EFI_ERROR (Status
)) {
823 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
824 Status
= RootBridgeIoGetMemTranslationByAddress (RootBridge
, Address
, &Translation
);
825 if (EFI_ERROR (Status
)) {
829 // Address passed to CpuIo->Mem.Read needs to be a host address instead of
831 return mCpuIo
->Mem
.Read (mCpuIo
, (EFI_CPU_IO_PROTOCOL_WIDTH
) Width
,
832 TO_HOST_ADDRESS (Address
, Translation
), Count
, Buffer
);
836 Enables a PCI driver to access PCI controller registers in the PCI root
839 The Mem.Read(), and Mem.Write() functions enable a driver to access PCI
840 controller registers in the PCI root bridge memory space.
841 The memory operations are carried out exactly as requested. The caller is
842 responsible for satisfying any alignment and memory width restrictions that a
843 PCI Root Bridge on a platform might require.
845 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
846 @param[in] Width Signifies the width of the memory operation.
847 @param[in] Address The base address of the memory operation. The caller
848 is responsible for aligning the Address if required.
849 @param[in] Count The number of memory operations to perform. Bytes
850 moved is Width size * Count, starting at Address.
851 @param[in] Buffer For read operations, the destination buffer to store
852 the results. For write operations, the source buffer
855 @retval EFI_SUCCESS The data was read from or written to the PCI
857 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
858 @retval EFI_INVALID_PARAMETER Buffer is NULL.
859 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
864 RootBridgeIoMemWrite (
865 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
866 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
873 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
876 Status
= RootBridgeIoCheckParameter (This
, MemOperation
, Width
, Address
,
878 if (EFI_ERROR (Status
)) {
882 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
883 Status
= RootBridgeIoGetMemTranslationByAddress (RootBridge
, Address
, &Translation
);
884 if (EFI_ERROR (Status
)) {
888 // Address passed to CpuIo->Mem.Write needs to be a host address instead of
890 return mCpuIo
->Mem
.Write (mCpuIo
, (EFI_CPU_IO_PROTOCOL_WIDTH
) Width
,
891 TO_HOST_ADDRESS (Address
, Translation
), Count
, Buffer
);
895 Enables a PCI driver to access PCI controller registers in the PCI root
898 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
899 @param[in] Width Signifies the width of the memory operations.
900 @param[in] Address The base address of the I/O operation. The caller is
901 responsible for aligning the Address if required.
902 @param[in] Count The number of I/O operations to perform. Bytes moved
903 is Width size * Count, starting at Address.
904 @param[out] Buffer For read operations, the destination buffer to store
905 the results. For write operations, the source buffer
908 @retval EFI_SUCCESS The data was read from or written to the PCI
910 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
911 @retval EFI_INVALID_PARAMETER Buffer is NULL.
912 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
918 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
919 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
926 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
928 Status
= RootBridgeIoCheckParameter (
929 This
, IoOperation
, Width
,
930 Address
, Count
, Buffer
932 if (EFI_ERROR (Status
)) {
936 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
938 // Address passed to CpuIo->Io.Read needs to be a host address instead of
940 return mCpuIo
->Io
.Read (mCpuIo
, (EFI_CPU_IO_PROTOCOL_WIDTH
) Width
,
941 TO_HOST_ADDRESS (Address
, RootBridge
->Io
.Translation
), Count
, Buffer
);
945 Enables a PCI driver to access PCI controller registers in the PCI root
948 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
949 @param[in] Width Signifies the width of the memory operations.
950 @param[in] Address The base address of the I/O operation. The caller is
951 responsible for aligning the Address if required.
952 @param[in] Count The number of I/O operations to perform. Bytes moved
953 is Width size * Count, starting at Address.
954 @param[in] Buffer For read operations, the destination buffer to store
955 the results. For write operations, the source buffer
958 @retval EFI_SUCCESS The data was read from or written to the PCI
960 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
961 @retval EFI_INVALID_PARAMETER Buffer is NULL.
962 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
967 RootBridgeIoIoWrite (
968 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
969 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
976 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
978 Status
= RootBridgeIoCheckParameter (
979 This
, IoOperation
, Width
,
980 Address
, Count
, Buffer
982 if (EFI_ERROR (Status
)) {
986 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
988 // Address passed to CpuIo->Io.Write needs to be a host address instead of
990 return mCpuIo
->Io
.Write (mCpuIo
, (EFI_CPU_IO_PROTOCOL_WIDTH
) Width
,
991 TO_HOST_ADDRESS (Address
, RootBridge
->Io
.Translation
), Count
, Buffer
);
995 Enables a PCI driver to copy one region of PCI root bridge memory space to
996 another region of PCI root bridge memory space.
998 The CopyMem() function enables a PCI driver to copy one region of PCI root
999 bridge memory space to another region of PCI root bridge memory space. This
1000 is especially useful for video scroll operation on a memory mapped video
1002 The memory operations are carried out exactly as requested. The caller is
1003 responsible for satisfying any alignment and memory width restrictions that a
1004 PCI root bridge on a platform might require.
1006 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
1008 @param[in] Width Signifies the width of the memory operations.
1009 @param[in] DestAddress The destination address of the memory operation. The
1010 caller is responsible for aligning the DestAddress if
1012 @param[in] SrcAddress The source address of the memory operation. The caller
1013 is responsible for aligning the SrcAddress if
1015 @param[in] Count The number of memory operations to perform. Bytes
1016 moved is Width size * Count, starting at DestAddress
1019 @retval EFI_SUCCESS The data was copied from one memory region
1020 to another memory region.
1021 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
1022 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
1027 RootBridgeIoCopyMem (
1028 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1029 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1030 IN UINT64 DestAddress
,
1031 IN UINT64 SrcAddress
,
1041 if ((UINT32
) Width
> EfiPciWidthUint64
) {
1042 return EFI_INVALID_PARAMETER
;
1045 if (DestAddress
== SrcAddress
) {
1049 Stride
= (UINTN
) (1 << Width
);
1052 if ((DestAddress
> SrcAddress
) &&
1053 (DestAddress
< (SrcAddress
+ Count
* Stride
))) {
1055 SrcAddress
= SrcAddress
+ (Count
- 1) * Stride
;
1056 DestAddress
= DestAddress
+ (Count
- 1) * Stride
;
1059 for (Index
= 0; Index
< Count
; Index
++) {
1060 Status
= RootBridgeIoMemRead (
1067 if (EFI_ERROR (Status
)) {
1070 Status
= RootBridgeIoMemWrite (
1077 if (EFI_ERROR (Status
)) {
1081 SrcAddress
+= Stride
;
1082 DestAddress
+= Stride
;
1084 SrcAddress
-= Stride
;
1085 DestAddress
-= Stride
;
1093 PCI configuration space access.
1095 @param This A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
1096 @param Read TRUE indicating it's a read operation.
1097 @param Width Signifies the width of the memory operation.
1098 @param Address The address within the PCI configuration space
1099 for the PCI controller.
1100 @param Count The number of PCI configuration operations
1102 @param Buffer The destination buffer to store the results.
1104 @retval EFI_SUCCESS The data was read/written from/to the PCI root bridge.
1105 @retval EFI_INVALID_PARAMETER Invalid parameters found.
1109 RootBridgeIoPciAccess (
1110 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1112 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1119 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1120 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress
;
1126 Status
= RootBridgeIoCheckParameter (This
, PciOperation
, Width
, Address
, Count
, Buffer
);
1127 if (EFI_ERROR (Status
)) {
1132 // Read Pci configuration space
1134 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1135 CopyMem (&PciAddress
, &Address
, sizeof (PciAddress
));
1137 if (PciAddress
.ExtendedRegister
== 0) {
1138 PciAddress
.ExtendedRegister
= PciAddress
.Register
;
1141 Address
= PCI_SEGMENT_LIB_ADDRESS (
1142 RootBridge
->RootBridgeIo
.SegmentNumber
,
1145 PciAddress
.Function
,
1146 PciAddress
.ExtendedRegister
1150 // Select loop based on the width of the transfer
1152 InStride
= mInStride
[Width
];
1153 OutStride
= mOutStride
[Width
];
1154 Size
= (UINTN
) (1 << (Width
& 0x03));
1155 for (Uint8Buffer
= Buffer
; Count
> 0; Address
+= InStride
, Uint8Buffer
+= OutStride
, Count
--) {
1157 PciSegmentReadBuffer (Address
, Size
, Uint8Buffer
);
1159 PciSegmentWriteBuffer (Address
, Size
, Uint8Buffer
);
1166 Allows read from PCI configuration space.
1168 @param This A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
1169 @param Width Signifies the width of the memory operation.
1170 @param Address The address within the PCI configuration space
1171 for the PCI controller.
1172 @param Count The number of PCI configuration operations
1174 @param Buffer The destination buffer to store the results.
1176 @retval EFI_SUCCESS The data was read from the PCI root bridge.
1177 @retval EFI_INVALID_PARAMETER Invalid parameters found.
1181 RootBridgeIoPciRead (
1182 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1183 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1189 return RootBridgeIoPciAccess (This
, TRUE
, Width
, Address
, Count
, Buffer
);
1193 Allows write to PCI configuration space.
1195 @param This A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
1196 @param Width Signifies the width of the memory operation.
1197 @param Address The address within the PCI configuration space
1198 for the PCI controller.
1199 @param Count The number of PCI configuration operations
1201 @param Buffer The source buffer to get the results.
1203 @retval EFI_SUCCESS The data was written to the PCI root bridge.
1204 @retval EFI_INVALID_PARAMETER Invalid parameters found.
1208 RootBridgeIoPciWrite (
1209 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1210 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1216 return RootBridgeIoPciAccess (This
, FALSE
, Width
, Address
, Count
, Buffer
);
1220 Provides the PCI controller-specific address needed to access
1221 system memory for DMA.
1223 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1224 @param Operation Indicate if the bus master is going to read or write
1226 @param HostAddress The system memory address to map on the PCI controller.
1227 @param NumberOfBytes On input the number of bytes to map.
1228 On output the number of bytes that were mapped.
1229 @param DeviceAddress The resulting map address for the bus master PCI
1230 controller to use to access the system memory's HostAddress.
1231 @param Mapping The value to pass to Unmap() when the bus master DMA
1232 operation is complete.
1234 @retval EFI_SUCCESS Success.
1235 @retval EFI_INVALID_PARAMETER Invalid parameters found.
1236 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
1237 @retval EFI_DEVICE_ERROR The System hardware could not map the requested address.
1238 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to lack of resources.
1243 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1244 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation
,
1245 IN VOID
*HostAddress
,
1246 IN OUT UINTN
*NumberOfBytes
,
1247 OUT EFI_PHYSICAL_ADDRESS
*DeviceAddress
,
1252 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1253 EFI_PHYSICAL_ADDRESS PhysicalAddress
;
1256 if (HostAddress
== NULL
|| NumberOfBytes
== NULL
|| DeviceAddress
== NULL
||
1258 return EFI_INVALID_PARAMETER
;
1262 // Make sure that Operation is valid
1264 if ((UINT32
) Operation
>= EfiPciOperationMaximum
) {
1265 return EFI_INVALID_PARAMETER
;
1268 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1270 if (mIoMmu
!= NULL
) {
1271 if (!RootBridge
->DmaAbove4G
) {
1273 // Clear 64bit support
1275 if (Operation
> EfiPciOperationBusMasterCommonBuffer
) {
1276 Operation
= (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION
) (Operation
- EfiPciOperationBusMasterRead64
);
1279 Status
= mIoMmu
->Map (
1281 (EDKII_IOMMU_OPERATION
) Operation
,
1290 PhysicalAddress
= (EFI_PHYSICAL_ADDRESS
) (UINTN
) HostAddress
;
1291 if ((!RootBridge
->DmaAbove4G
||
1292 (Operation
!= EfiPciOperationBusMasterRead64
&&
1293 Operation
!= EfiPciOperationBusMasterWrite64
&&
1294 Operation
!= EfiPciOperationBusMasterCommonBuffer64
)) &&
1295 ((PhysicalAddress
+ *NumberOfBytes
) > SIZE_4GB
)) {
1298 // If the root bridge or the device cannot handle performing DMA above
1299 // 4GB but any part of the DMA transfer being mapped is above 4GB, then
1300 // map the DMA transfer to a buffer below 4GB.
1303 if (Operation
== EfiPciOperationBusMasterCommonBuffer
||
1304 Operation
== EfiPciOperationBusMasterCommonBuffer64
) {
1306 // Common Buffer operations can not be remapped. If the common buffer
1307 // if above 4GB, then it is not possible to generate a mapping, so return
1310 return EFI_UNSUPPORTED
;
1314 // Allocate a MAP_INFO structure to remember the mapping when Unmap() is
1317 MapInfo
= AllocatePool (sizeof (MAP_INFO
));
1318 if (MapInfo
== NULL
) {
1320 return EFI_OUT_OF_RESOURCES
;
1324 // Initialize the MAP_INFO structure
1326 MapInfo
->Signature
= MAP_INFO_SIGNATURE
;
1327 MapInfo
->Operation
= Operation
;
1328 MapInfo
->NumberOfBytes
= *NumberOfBytes
;
1329 MapInfo
->NumberOfPages
= EFI_SIZE_TO_PAGES (MapInfo
->NumberOfBytes
);
1330 MapInfo
->HostAddress
= PhysicalAddress
;
1331 MapInfo
->MappedHostAddress
= SIZE_4GB
- 1;
1334 // Allocate a buffer below 4GB to map the transfer to.
1336 Status
= gBS
->AllocatePages (
1338 EfiBootServicesData
,
1339 MapInfo
->NumberOfPages
,
1340 &MapInfo
->MappedHostAddress
1342 if (EFI_ERROR (Status
)) {
1349 // If this is a read operation from the Bus Master's point of view,
1350 // then copy the contents of the real buffer into the mapped buffer
1351 // so the Bus Master can read the contents of the real buffer.
1353 if (Operation
== EfiPciOperationBusMasterRead
||
1354 Operation
== EfiPciOperationBusMasterRead64
) {
1356 (VOID
*) (UINTN
) MapInfo
->MappedHostAddress
,
1357 (VOID
*) (UINTN
) MapInfo
->HostAddress
,
1358 MapInfo
->NumberOfBytes
1362 InsertTailList (&RootBridge
->Maps
, &MapInfo
->Link
);
1365 // The DeviceAddress is the address of the maped buffer below 4GB
1367 *DeviceAddress
= MapInfo
->MappedHostAddress
;
1369 // Return a pointer to the MAP_INFO structure in Mapping
1374 // If the root bridge CAN handle performing DMA above 4GB or
1375 // the transfer is below 4GB, so the DeviceAddress is simply the
1378 *DeviceAddress
= PhysicalAddress
;
1379 *Mapping
= NO_MAPPING
;
1386 Completes the Map() operation and releases any corresponding resources.
1388 The Unmap() function completes the Map() operation and releases any
1389 corresponding resources.
1390 If the operation was an EfiPciOperationBusMasterWrite or
1391 EfiPciOperationBusMasterWrite64, the data is committed to the target system
1393 Any resources used for the mapping are freed.
1395 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1396 @param[in] Mapping The mapping value returned from Map().
1398 @retval EFI_SUCCESS The range was unmapped.
1399 @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().
1400 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
1405 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1411 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1414 if (mIoMmu
!= NULL
) {
1415 Status
= mIoMmu
->Unmap (
1422 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1425 // See if the Map() operation associated with this Unmap() required a mapping
1426 // buffer. If a mapping buffer was not required, then this function simply
1427 // returns EFI_SUCCESS.
1429 if (Mapping
== NO_MAPPING
) {
1433 MapInfo
= NO_MAPPING
;
1434 for (Link
= GetFirstNode (&RootBridge
->Maps
)
1435 ; !IsNull (&RootBridge
->Maps
, Link
)
1436 ; Link
= GetNextNode (&RootBridge
->Maps
, Link
)
1438 MapInfo
= MAP_INFO_FROM_LINK (Link
);
1439 if (MapInfo
== Mapping
) {
1444 // Mapping is not a valid value returned by Map()
1446 if (MapInfo
!= Mapping
) {
1447 return EFI_INVALID_PARAMETER
;
1449 RemoveEntryList (&MapInfo
->Link
);
1452 // If this is a write operation from the Bus Master's point of view,
1453 // then copy the contents of the mapped buffer into the real buffer
1454 // so the processor can read the contents of the real buffer.
1456 if (MapInfo
->Operation
== EfiPciOperationBusMasterWrite
||
1457 MapInfo
->Operation
== EfiPciOperationBusMasterWrite64
) {
1459 (VOID
*) (UINTN
) MapInfo
->HostAddress
,
1460 (VOID
*) (UINTN
) MapInfo
->MappedHostAddress
,
1461 MapInfo
->NumberOfBytes
1466 // Free the mapped buffer and the MAP_INFO structure.
1468 gBS
->FreePages (MapInfo
->MappedHostAddress
, MapInfo
->NumberOfPages
);
1474 Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer
1475 or EfiPciOperationBusMasterCommonBuffer64 mapping.
1477 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1478 @param Type This parameter is not used and must be ignored.
1479 @param MemoryType The type of memory to allocate, EfiBootServicesData or
1480 EfiRuntimeServicesData.
1481 @param Pages The number of pages to allocate.
1482 @param HostAddress A pointer to store the base system memory address of the
1484 @param Attributes The requested bit mask of attributes for the allocated
1485 range. Only the attributes
1486 EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE,
1487 EFI_PCI_ATTRIBUTE_MEMORY_CACHED, and
1488 EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this
1491 @retval EFI_SUCCESS The requested memory pages were allocated.
1492 @retval EFI_INVALID_PARAMETER MemoryType is invalid.
1493 @retval EFI_INVALID_PARAMETER HostAddress is NULL.
1494 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal
1495 attribute bits are MEMORY_WRITE_COMBINE,
1496 MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.
1497 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
1501 RootBridgeIoAllocateBuffer (
1502 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1503 IN EFI_ALLOCATE_TYPE Type
,
1504 IN EFI_MEMORY_TYPE MemoryType
,
1506 OUT VOID
**HostAddress
,
1507 IN UINT64 Attributes
1511 EFI_PHYSICAL_ADDRESS PhysicalAddress
;
1512 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1513 EFI_ALLOCATE_TYPE AllocateType
;
1516 // Validate Attributes
1518 if ((Attributes
& EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER
) != 0) {
1519 return EFI_UNSUPPORTED
;
1523 // Check for invalid inputs
1525 if (HostAddress
== NULL
) {
1526 return EFI_INVALID_PARAMETER
;
1530 // The only valid memory types are EfiBootServicesData and
1531 // EfiRuntimeServicesData
1533 if (MemoryType
!= EfiBootServicesData
&&
1534 MemoryType
!= EfiRuntimeServicesData
) {
1535 return EFI_INVALID_PARAMETER
;
1538 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1540 if (mIoMmu
!= NULL
) {
1541 if (!RootBridge
->DmaAbove4G
) {
1543 // Clear DUAL_ADDRESS_CYCLE
1545 Attributes
&= ~((UINT64
) EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE
);
1547 Status
= mIoMmu
->AllocateBuffer (
1558 AllocateType
= AllocateAnyPages
;
1559 if (!RootBridge
->DmaAbove4G
||
1560 (Attributes
& EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE
) == 0) {
1562 // Limit allocations to memory below 4GB
1564 AllocateType
= AllocateMaxAddress
;
1565 PhysicalAddress
= (EFI_PHYSICAL_ADDRESS
) (SIZE_4GB
- 1);
1567 Status
= gBS
->AllocatePages (
1573 if (!EFI_ERROR (Status
)) {
1574 *HostAddress
= (VOID
*) (UINTN
) PhysicalAddress
;
1581 Frees memory that was allocated with AllocateBuffer().
1583 The FreeBuffer() function frees memory that was allocated with
1586 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1587 @param Pages The number of pages to free.
1588 @param HostAddress The base system memory address of the allocated range.
1590 @retval EFI_SUCCESS The requested memory pages were freed.
1591 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and
1592 Pages was not allocated with AllocateBuffer().
1596 RootBridgeIoFreeBuffer (
1597 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1599 OUT VOID
*HostAddress
1604 if (mIoMmu
!= NULL
) {
1605 Status
= mIoMmu
->FreeBuffer (
1613 return gBS
->FreePages ((EFI_PHYSICAL_ADDRESS
) (UINTN
) HostAddress
, Pages
);
1617 Flushes all PCI posted write transactions from a PCI host bridge to system
1620 The Flush() function flushes any PCI posted write transactions from a PCI
1621 host bridge to system memory. Posted write transactions are generated by PCI
1622 bus masters when they perform write transactions to target addresses in
1624 This function does not flush posted write transactions from any PCI bridges.
1625 A PCI controller specific action must be taken to guarantee that the posted
1626 write transactions have been flushed from the PCI controller and from all the
1627 PCI bridges into the PCI host bridge. This is typically done with a PCI read
1628 transaction from the PCI controller prior to calling Flush().
1630 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1632 @retval EFI_SUCCESS The PCI posted write transactions were flushed
1633 from the PCI host bridge to system memory.
1634 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed
1635 from the PCI host bridge due to a hardware error.
1640 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
1647 Gets the attributes that a PCI root bridge supports setting with
1648 SetAttributes(), and the attributes that a PCI root bridge is currently
1651 The GetAttributes() function returns the mask of attributes that this PCI
1652 root bridge supports and the mask of attributes that the PCI root bridge is
1655 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1656 @param Supported A pointer to the mask of attributes that this PCI root
1657 bridge supports setting with SetAttributes().
1658 @param Attributes A pointer to the mask of attributes that this PCI root
1659 bridge is currently using.
1661 @retval EFI_SUCCESS If Supports is not NULL, then the attributes
1662 that the PCI root bridge supports is returned
1663 in Supports. If Attributes is not NULL, then
1664 the attributes that the PCI root bridge is
1665 currently using is returned in Attributes.
1666 @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
1670 RootBridgeIoGetAttributes (
1671 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1672 OUT UINT64
*Supported
,
1673 OUT UINT64
*Attributes
1676 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1678 if (Attributes
== NULL
&& Supported
== NULL
) {
1679 return EFI_INVALID_PARAMETER
;
1682 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1684 // Set the return value for Supported and Attributes
1686 if (Supported
!= NULL
) {
1687 *Supported
= RootBridge
->Supports
;
1690 if (Attributes
!= NULL
) {
1691 *Attributes
= RootBridge
->Attributes
;
1698 Sets attributes for a resource range on a PCI root bridge.
1700 The SetAttributes() function sets the attributes specified in Attributes for
1701 the PCI root bridge on the resource range specified by ResourceBase and
1702 ResourceLength. Since the granularity of setting these attributes may vary
1703 from resource type to resource type, and from platform to platform, the
1704 actual resource range and the one passed in by the caller may differ. As a
1705 result, this function may set the attributes specified by Attributes on a
1706 larger resource range than the caller requested. The actual range is returned
1707 in ResourceBase and ResourceLength. The caller is responsible for verifying
1708 that the actual range for which the attributes were set is acceptable.
1710 @param This A pointer to the
1711 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1712 @param Attributes The mask of attributes to set. If the
1713 attribute bit MEMORY_WRITE_COMBINE,
1714 MEMORY_CACHED, or MEMORY_DISABLE is set,
1715 then the resource range is specified by
1716 ResourceBase and ResourceLength. If
1717 MEMORY_WRITE_COMBINE, MEMORY_CACHED, and
1718 MEMORY_DISABLE are not set, then
1719 ResourceBase and ResourceLength are ignored,
1721 @param ResourceBase A pointer to the base address of the
1722 resource range to be modified by the
1723 attributes specified by Attributes.
1724 @param ResourceLength A pointer to the length of the resource
1725 range to be modified by the attributes
1726 specified by Attributes.
1728 @retval EFI_SUCCESS The current configuration of this PCI root bridge
1729 was returned in Resources.
1730 @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge
1731 could not be retrieved.
1735 RootBridgeIoSetAttributes (
1736 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1737 IN UINT64 Attributes
,
1738 IN OUT UINT64
*ResourceBase
,
1739 IN OUT UINT64
*ResourceLength
1742 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1744 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1746 if ((Attributes
& (~RootBridge
->Supports
)) != 0) {
1747 return EFI_UNSUPPORTED
;
1750 RootBridge
->Attributes
= Attributes
;
1755 Retrieves the current resource settings of this PCI root bridge in the form
1756 of a set of ACPI resource descriptors.
1758 There are only two resource descriptor types from the ACPI Specification that
1759 may be used to describe the current resources allocated to a PCI root bridge.
1760 These are the QWORD Address Space Descriptor, and the End Tag. The QWORD
1761 Address Space Descriptor can describe memory, I/O, and bus number ranges for
1762 dynamic or fixed resources. The configuration of a PCI root bridge is described
1763 with one or more QWORD Address Space Descriptors followed by an End Tag.
1765 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1766 @param[out] Resources A pointer to the resource descriptors that
1767 describe the current configuration of this PCI root
1768 bridge. The storage for the resource
1769 descriptors is allocated by this function. The
1770 caller must treat the return buffer as read-only
1771 data, and the buffer must not be freed by the
1774 @retval EFI_SUCCESS The current configuration of this PCI root bridge
1775 was returned in Resources.
1776 @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge
1777 could not be retrieved.
1781 RootBridgeIoConfiguration (
1782 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1783 OUT VOID
**Resources
1786 PCI_RESOURCE_TYPE Index
;
1787 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1788 PCI_RES_NODE
*ResAllocNode
;
1789 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptor
;
1790 EFI_ACPI_END_TAG_DESCRIPTOR
*End
;
1793 // Get this instance of the Root Bridge.
1795 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1797 RootBridge
->ConfigBuffer
,
1798 TypeMax
* sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR
)
1800 Descriptor
= RootBridge
->ConfigBuffer
;
1801 for (Index
= TypeIo
; Index
< TypeMax
; Index
++) {
1803 ResAllocNode
= &RootBridge
->ResAllocNode
[Index
];
1805 if (ResAllocNode
->Status
!= ResAllocated
) {
1809 Descriptor
->Desc
= ACPI_ADDRESS_SPACE_DESCRIPTOR
;
1810 Descriptor
->Len
= sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) - 3;
1811 // According to UEFI 2.7, RootBridgeIo->Configuration should return address
1812 // range in CPU view (host address), and ResAllocNode->Base is already a CPU
1813 // view address (host address).
1814 Descriptor
->AddrRangeMin
= ResAllocNode
->Base
;
1815 Descriptor
->AddrRangeMax
= ResAllocNode
->Base
+ ResAllocNode
->Length
- 1;
1816 Descriptor
->AddrLen
= ResAllocNode
->Length
;
1817 Descriptor
->AddrTranslationOffset
= GetTranslationByResourceType (
1822 switch (ResAllocNode
->Type
) {
1825 Descriptor
->ResType
= ACPI_ADDRESS_SPACE_TYPE_IO
;
1829 Descriptor
->SpecificFlag
= EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
;
1831 Descriptor
->ResType
= ACPI_ADDRESS_SPACE_TYPE_MEM
;
1832 Descriptor
->AddrSpaceGranularity
= 32;
1836 Descriptor
->SpecificFlag
= EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
;
1838 Descriptor
->ResType
= ACPI_ADDRESS_SPACE_TYPE_MEM
;
1839 Descriptor
->AddrSpaceGranularity
= 64;
1843 Descriptor
->ResType
= ACPI_ADDRESS_SPACE_TYPE_BUS
;
1853 // Terminate the entries.
1855 End
= (EFI_ACPI_END_TAG_DESCRIPTOR
*) Descriptor
;
1856 End
->Desc
= ACPI_END_TAG_DESCRIPTOR
;
1857 End
->Checksum
= 0x0;
1859 *Resources
= RootBridge
->ConfigBuffer
;