2 This driver is used to manage SD/MMC PCI host controllers which are compliance
3 with SD Host Controller Simplified Specification version 3.00.
5 It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
7 Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
8 This program and the accompanying materials
9 are licensed and made available under the terms and conditions of the BSD License
10 which accompanies this distribution. The full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #include "SdMmcPciHcDxe.h"
21 Dump the content of SD/MMC host controller's Capability Register.
23 @param[in] Slot The slot number of the SD card to send the command to.
24 @param[in] Capability The buffer to store the capability data.
30 IN SD_MMC_HC_SLOT_CAP
*Capability
34 // Dump Capability Data
36 DEBUG ((EFI_D_INFO
, " == Slot [%d] Capability is 0x%x ==\n", Slot
, Capability
));
37 DEBUG ((EFI_D_INFO
, " Timeout Clk Freq %d%a\n", Capability
->TimeoutFreq
, (Capability
->TimeoutUnit
) ? "MHz" : "KHz"));
38 DEBUG ((EFI_D_INFO
, " Base Clk Freq %dMHz\n", Capability
->BaseClkFreq
));
39 DEBUG ((EFI_D_INFO
, " Max Blk Len %dbytes\n", 512 * (1 << Capability
->MaxBlkLen
)));
40 DEBUG ((EFI_D_INFO
, " 8-bit Support %a\n", Capability
->BusWidth8
? "TRUE" : "FALSE"));
41 DEBUG ((EFI_D_INFO
, " ADMA2 Support %a\n", Capability
->Adma2
? "TRUE" : "FALSE"));
42 DEBUG ((EFI_D_INFO
, " HighSpeed Support %a\n", Capability
->HighSpeed
? "TRUE" : "FALSE"));
43 DEBUG ((EFI_D_INFO
, " SDMA Support %a\n", Capability
->Sdma
? "TRUE" : "FALSE"));
44 DEBUG ((EFI_D_INFO
, " Suspend/Resume %a\n", Capability
->SuspRes
? "TRUE" : "FALSE"));
45 DEBUG ((EFI_D_INFO
, " Voltage 3.3 %a\n", Capability
->Voltage33
? "TRUE" : "FALSE"));
46 DEBUG ((EFI_D_INFO
, " Voltage 3.0 %a\n", Capability
->Voltage30
? "TRUE" : "FALSE"));
47 DEBUG ((EFI_D_INFO
, " Voltage 1.8 %a\n", Capability
->Voltage18
? "TRUE" : "FALSE"));
48 DEBUG ((EFI_D_INFO
, " 64-bit Sys Bus %a\n", Capability
->SysBus64
? "TRUE" : "FALSE"));
49 DEBUG ((EFI_D_INFO
, " Async Interrupt %a\n", Capability
->AsyncInt
? "TRUE" : "FALSE"));
50 DEBUG ((EFI_D_INFO
, " SlotType "));
51 if (Capability
->SlotType
== 0x00) {
52 DEBUG ((EFI_D_INFO
, "%a\n", "Removable Slot"));
53 } else if (Capability
->SlotType
== 0x01) {
54 DEBUG ((EFI_D_INFO
, "%a\n", "Embedded Slot"));
55 } else if (Capability
->SlotType
== 0x02) {
56 DEBUG ((EFI_D_INFO
, "%a\n", "Shared Bus Slot"));
58 DEBUG ((EFI_D_INFO
, "%a\n", "Reserved"));
60 DEBUG ((EFI_D_INFO
, " SDR50 Support %a\n", Capability
->Sdr50
? "TRUE" : "FALSE"));
61 DEBUG ((EFI_D_INFO
, " SDR104 Support %a\n", Capability
->Sdr104
? "TRUE" : "FALSE"));
62 DEBUG ((EFI_D_INFO
, " DDR50 Support %a\n", Capability
->Ddr50
? "TRUE" : "FALSE"));
63 DEBUG ((EFI_D_INFO
, " Driver Type A %a\n", Capability
->DriverTypeA
? "TRUE" : "FALSE"));
64 DEBUG ((EFI_D_INFO
, " Driver Type C %a\n", Capability
->DriverTypeC
? "TRUE" : "FALSE"));
65 DEBUG ((EFI_D_INFO
, " Driver Type D %a\n", Capability
->DriverTypeD
? "TRUE" : "FALSE"));
66 DEBUG ((EFI_D_INFO
, " Driver Type 4 %a\n", Capability
->DriverType4
? "TRUE" : "FALSE"));
67 if (Capability
->TimerCount
== 0) {
68 DEBUG ((EFI_D_INFO
, " Retuning TimerCnt Disabled\n", 2 * (Capability
->TimerCount
- 1)));
70 DEBUG ((EFI_D_INFO
, " Retuning TimerCnt %dseconds\n", 2 * (Capability
->TimerCount
- 1)));
72 DEBUG ((EFI_D_INFO
, " SDR50 Tuning %a\n", Capability
->TuningSDR50
? "TRUE" : "FALSE"));
73 DEBUG ((EFI_D_INFO
, " Retuning Mode Mode %d\n", Capability
->RetuningMod
+ 1));
74 DEBUG ((EFI_D_INFO
, " Clock Multiplier M = %d\n", Capability
->ClkMultiplier
+ 1));
75 DEBUG ((EFI_D_INFO
, " HS 400 %a\n", Capability
->Hs400
? "TRUE" : "FALSE"));
80 Read SlotInfo register from SD/MMC host controller pci config space.
82 @param[in] PciIo The PCI IO protocol instance.
83 @param[out] FirstBar The buffer to store the first BAR value.
84 @param[out] SlotNum The buffer to store the supported slot number.
86 @retval EFI_SUCCESS The operation succeeds.
87 @retval Others The operation fails.
93 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
99 SD_MMC_HC_SLOT_INFO SlotInfo
;
101 Status
= PciIo
->Pci
.Read (
104 SD_MMC_HC_SLOT_OFFSET
,
108 if (EFI_ERROR (Status
)) {
112 *FirstBar
= SlotInfo
.FirstBar
;
113 *SlotNum
= SlotInfo
.SlotNum
+ 1;
114 ASSERT ((*FirstBar
+ *SlotNum
) < SD_MMC_HC_MAX_SLOT
);
119 Read/Write specified SD/MMC host controller mmio register.
121 @param[in] PciIo The PCI IO protocol instance.
122 @param[in] BarIndex The BAR index of the standard PCI Configuration
123 header to use as the base address for the memory
124 operation to perform.
125 @param[in] Offset The offset within the selected BAR to start the
127 @param[in] Read A boolean to indicate it's read or write operation.
128 @param[in] Count The width of the mmio register in bytes.
129 Must be 1, 2 , 4 or 8 bytes.
130 @param[in, out] Data For read operations, the destination buffer to store
131 the results. For write operations, the source buffer
132 to write data from. The caller is responsible for
133 having ownership of the data buffer and ensuring its
134 size not less than Count bytes.
136 @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
137 @retval EFI_SUCCESS The read/write operation succeeds.
138 @retval Others The read/write operation fails.
144 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
154 if ((PciIo
== NULL
) || (Data
== NULL
)) {
155 return EFI_INVALID_PARAMETER
;
158 if ((Count
!= 1) && (Count
!= 2) && (Count
!= 4) && (Count
!= 8)) {
159 return EFI_INVALID_PARAMETER
;
163 Status
= PciIo
->Mem
.Read (
172 Status
= PciIo
->Mem
.Write (
186 Do OR operation with the value of the specified SD/MMC host controller mmio register.
188 @param[in] PciIo The PCI IO protocol instance.
189 @param[in] BarIndex The BAR index of the standard PCI Configuration
190 header to use as the base address for the memory
191 operation to perform.
192 @param[in] Offset The offset within the selected BAR to start the
194 @param[in] Count The width of the mmio register in bytes.
195 Must be 1, 2 , 4 or 8 bytes.
196 @param[in] OrData The pointer to the data used to do OR operation.
197 The caller is responsible for having ownership of
198 the data buffer and ensuring its size not less than
201 @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
202 @retval EFI_SUCCESS The OR operation succeeds.
203 @retval Others The OR operation fails.
209 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
220 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, TRUE
, Count
, &Data
);
221 if (EFI_ERROR (Status
)) {
226 Or
= *(UINT8
*) OrData
;
227 } else if (Count
== 2) {
228 Or
= *(UINT16
*) OrData
;
229 } else if (Count
== 4) {
230 Or
= *(UINT32
*) OrData
;
231 } else if (Count
== 8) {
232 Or
= *(UINT64
*) OrData
;
234 return EFI_INVALID_PARAMETER
;
238 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, FALSE
, Count
, &Data
);
244 Do AND operation with the value of the specified SD/MMC host controller mmio register.
246 @param[in] PciIo The PCI IO protocol instance.
247 @param[in] BarIndex The BAR index of the standard PCI Configuration
248 header to use as the base address for the memory
249 operation to perform.
250 @param[in] Offset The offset within the selected BAR to start the
252 @param[in] Count The width of the mmio register in bytes.
253 Must be 1, 2 , 4 or 8 bytes.
254 @param[in] AndData The pointer to the data used to do AND operation.
255 The caller is responsible for having ownership of
256 the data buffer and ensuring its size not less than
259 @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
260 @retval EFI_SUCCESS The AND operation succeeds.
261 @retval Others The AND operation fails.
267 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
278 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, TRUE
, Count
, &Data
);
279 if (EFI_ERROR (Status
)) {
284 And
= *(UINT8
*) AndData
;
285 } else if (Count
== 2) {
286 And
= *(UINT16
*) AndData
;
287 } else if (Count
== 4) {
288 And
= *(UINT32
*) AndData
;
289 } else if (Count
== 8) {
290 And
= *(UINT64
*) AndData
;
292 return EFI_INVALID_PARAMETER
;
296 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, FALSE
, Count
, &Data
);
302 Wait for the value of the specified MMIO register set to the test value.
304 @param[in] PciIo The PCI IO protocol instance.
305 @param[in] BarIndex The BAR index of the standard PCI Configuration
306 header to use as the base address for the memory
307 operation to perform.
308 @param[in] Offset The offset within the selected BAR to start the
310 @param[in] Count The width of the mmio register in bytes.
311 Must be 1, 2, 4 or 8 bytes.
312 @param[in] MaskValue The mask value of memory.
313 @param[in] TestValue The test value of memory.
315 @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.
316 @retval EFI_SUCCESS The MMIO register has expected value.
317 @retval Others The MMIO operation fails.
322 SdMmcHcCheckMmioSet (
323 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
335 // Access PCI MMIO space to see if the value is the tested one.
338 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, TRUE
, Count
, &Value
);
339 if (EFI_ERROR (Status
)) {
345 if (Value
== TestValue
) {
349 return EFI_NOT_READY
;
353 Wait for the value of the specified MMIO register set to the test value.
355 @param[in] PciIo The PCI IO protocol instance.
356 @param[in] BarIndex The BAR index of the standard PCI Configuration
357 header to use as the base address for the memory
358 operation to perform.
359 @param[in] Offset The offset within the selected BAR to start the
361 @param[in] Count The width of the mmio register in bytes.
362 Must be 1, 2, 4 or 8 bytes.
363 @param[in] MaskValue The mask value of memory.
364 @param[in] TestValue The test value of memory.
365 @param[in] Timeout The time out value for wait memory set, uses 1
366 microsecond as a unit.
368 @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout
370 @retval EFI_SUCCESS The MMIO register has expected value.
371 @retval Others The MMIO operation fails.
377 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
387 BOOLEAN InfiniteWait
;
392 InfiniteWait
= FALSE
;
395 while (InfiniteWait
|| (Timeout
> 0)) {
396 Status
= SdMmcHcCheckMmioSet (
404 if (Status
!= EFI_NOT_READY
) {
409 // Stall for 1 microsecond.
420 Software reset the specified SD/MMC host controller and enable all interrupts.
422 @param[in] PciIo The PCI IO protocol instance.
423 @param[in] Slot The slot number of the SD card to send the command to.
425 @retval EFI_SUCCESS The software reset executes successfully.
426 @retval Others The software reset fails.
431 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
439 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_SW_RST
, FALSE
, sizeof (SwReset
), &SwReset
);
441 if (EFI_ERROR (Status
)) {
442 DEBUG ((EFI_D_ERROR
, "SdMmcHcReset: write full 1 fails: %r\n", Status
));
446 Status
= SdMmcHcWaitMmioSet (
453 SD_MMC_HC_GENERIC_TIMEOUT
455 if (EFI_ERROR (Status
)) {
456 DEBUG ((EFI_D_INFO
, "SdMmcHcReset: reset done with %r\n", Status
));
460 // Enable all interrupt after reset all.
462 Status
= SdMmcHcEnableInterrupt (PciIo
, Slot
);
468 Set all interrupt status bits in Normal and Error Interrupt Status Enable
471 @param[in] PciIo The PCI IO protocol instance.
472 @param[in] Slot The slot number of the SD card to send the command to.
474 @retval EFI_SUCCESS The operation executes successfully.
475 @retval Others The operation fails.
479 SdMmcHcEnableInterrupt (
480 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
488 // Enable all bits in Error Interrupt Status Enable Register
491 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_ERR_INT_STS_EN
, FALSE
, sizeof (IntStatus
), &IntStatus
);
492 if (EFI_ERROR (Status
)) {
496 // Enable all bits in Normal Interrupt Status Enable Register
499 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_NOR_INT_STS_EN
, FALSE
, sizeof (IntStatus
), &IntStatus
);
505 Get the capability data from the specified slot.
507 @param[in] PciIo The PCI IO protocol instance.
508 @param[in] Slot The slot number of the SD card to send the command to.
509 @param[out] Capability The buffer to store the capability data.
511 @retval EFI_SUCCESS The operation executes successfully.
512 @retval Others The operation fails.
516 SdMmcHcGetCapability (
517 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
519 OUT SD_MMC_HC_SLOT_CAP
*Capability
525 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_CAP
, TRUE
, sizeof (Cap
), &Cap
);
526 if (EFI_ERROR (Status
)) {
530 CopyMem (Capability
, &Cap
, sizeof (Cap
));
536 Get the maximum current capability data from the specified slot.
538 @param[in] PciIo The PCI IO protocol instance.
539 @param[in] Slot The slot number of the SD card to send the command to.
540 @param[out] MaxCurrent The buffer to store the maximum current capability data.
542 @retval EFI_SUCCESS The operation executes successfully.
543 @retval Others The operation fails.
547 SdMmcHcGetMaxCurrent (
548 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
550 OUT UINT64
*MaxCurrent
555 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_MAX_CURRENT_CAP
, TRUE
, sizeof (UINT64
), MaxCurrent
);
561 Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
564 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
566 @param[in] PciIo The PCI IO protocol instance.
567 @param[in] Slot The slot number of the SD card to send the command to.
568 @param[out] MediaPresent The pointer to the media present boolean value.
570 @retval EFI_SUCCESS There is no media change happened.
571 @retval EFI_MEDIA_CHANGED There is media change happened.
572 @retval Others The detection fails.
577 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
579 OUT BOOLEAN
*MediaPresent
587 // Check Present State Register to see if there is a card presented.
589 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_PRESENT_STATE
, TRUE
, sizeof (PresentState
), &PresentState
);
590 if (EFI_ERROR (Status
)) {
594 if ((PresentState
& BIT16
) != 0) {
595 *MediaPresent
= TRUE
;
597 *MediaPresent
= FALSE
;
601 // Check Normal Interrupt Status Register
603 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_NOR_INT_STS
, TRUE
, sizeof (Data
), &Data
);
604 if (EFI_ERROR (Status
)) {
608 if ((Data
& (BIT6
| BIT7
)) != 0) {
610 // Clear BIT6 and BIT7 by writing 1 to these two bits if set.
613 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_NOR_INT_STS
, FALSE
, sizeof (Data
), &Data
);
614 if (EFI_ERROR (Status
)) {
618 return EFI_MEDIA_CHANGED
;
625 Stop SD/MMC card clock.
627 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
629 @param[in] PciIo The PCI IO protocol instance.
630 @param[in] Slot The slot number of the SD card to send the command to.
632 @retval EFI_SUCCESS Succeed to stop SD/MMC clock.
633 @retval Others Fail to stop SD/MMC clock.
638 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
647 // Ensure no SD transactions are occurring on the SD Bus by
648 // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)
649 // in the Present State register to be 0.
651 Status
= SdMmcHcWaitMmioSet (
654 SD_MMC_HC_PRESENT_STATE
,
655 sizeof (PresentState
),
658 SD_MMC_HC_GENERIC_TIMEOUT
660 if (EFI_ERROR (Status
)) {
665 // Set SD Clock Enable in the Clock Control register to 0
667 ClockCtrl
= (UINT16
)~BIT2
;
668 Status
= SdMmcHcAndMmio (PciIo
, Slot
, SD_MMC_HC_CLOCK_CTRL
, sizeof (ClockCtrl
), &ClockCtrl
);
674 SD/MMC card clock supply.
676 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
678 @param[in] PciIo The PCI IO protocol instance.
679 @param[in] Slot The slot number of the SD card to send the command to.
680 @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
681 @param[in] Capability The capability of the slot.
683 @retval EFI_SUCCESS The clock is supplied successfully.
684 @retval Others The clock isn't supplied successfully.
689 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
692 IN SD_MMC_HC_SLOT_CAP Capability
700 UINT16 ControllerVer
;
704 // Calculate a divisor for SD clock frequency
706 ASSERT (Capability
.BaseClkFreq
!= 0);
708 BaseClkFreq
= Capability
.BaseClkFreq
;
709 if (ClockFreq
== 0) {
710 return EFI_INVALID_PARAMETER
;
713 if (ClockFreq
> (BaseClkFreq
* 1000)) {
714 ClockFreq
= BaseClkFreq
* 1000;
718 // Calculate the divisor of base frequency.
721 SettingFreq
= BaseClkFreq
* 1000;
722 while (ClockFreq
< SettingFreq
) {
725 SettingFreq
= (BaseClkFreq
* 1000) / (2 * Divisor
);
726 Remainder
= (BaseClkFreq
* 1000) % (2 * Divisor
);
727 if ((ClockFreq
== SettingFreq
) && (Remainder
== 0)) {
730 if ((ClockFreq
== SettingFreq
) && (Remainder
!= 0)) {
735 DEBUG ((EFI_D_INFO
, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq
, Divisor
, ClockFreq
));
737 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_CTRL_VER
, TRUE
, sizeof (ControllerVer
), &ControllerVer
);
738 if (EFI_ERROR (Status
)) {
742 // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.
744 if ((ControllerVer
& 0xFF) == 2) {
745 ASSERT (Divisor
<= 0x3FF);
746 ClockCtrl
= ((Divisor
& 0xFF) << 8) | ((Divisor
& 0x300) >> 2);
747 } else if (((ControllerVer
& 0xFF) == 0) || ((ControllerVer
& 0xFF) == 1)) {
749 // Only the most significant bit can be used as divisor.
751 if (((Divisor
- 1) & Divisor
) != 0) {
752 Divisor
= 1 << (HighBitSet32 (Divisor
) + 1);
754 ASSERT (Divisor
<= 0x80);
755 ClockCtrl
= (Divisor
& 0xFF) << 8;
757 DEBUG ((EFI_D_ERROR
, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer
));
758 return EFI_UNSUPPORTED
;
762 // Stop bus clock at first
764 Status
= SdMmcHcStopClock (PciIo
, Slot
);
765 if (EFI_ERROR (Status
)) {
770 // Supply clock frequency with specified divisor
773 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_CLOCK_CTRL
, FALSE
, sizeof (ClockCtrl
), &ClockCtrl
);
774 if (EFI_ERROR (Status
)) {
775 DEBUG ((EFI_D_ERROR
, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));
780 // Wait Internal Clock Stable in the Clock Control register to be 1
782 Status
= SdMmcHcWaitMmioSet (
785 SD_MMC_HC_CLOCK_CTRL
,
789 SD_MMC_HC_GENERIC_TIMEOUT
791 if (EFI_ERROR (Status
)) {
796 // Set SD Clock Enable in the Clock Control register to 1
799 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_CLOCK_CTRL
, sizeof (ClockCtrl
), &ClockCtrl
);
805 SD/MMC bus power control.
807 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
809 @param[in] PciIo The PCI IO protocol instance.
810 @param[in] Slot The slot number of the SD card to send the command to.
811 @param[in] PowerCtrl The value setting to the power control register.
813 @retval TRUE There is a SD/MMC card attached.
814 @retval FALSE There is no a SD/MMC card attached.
818 SdMmcHcPowerControl (
819 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
829 PowerCtrl
&= (UINT8
)~BIT0
;
830 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_POWER_CTRL
, FALSE
, sizeof (PowerCtrl
), &PowerCtrl
);
831 if (EFI_ERROR (Status
)) {
836 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
839 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_POWER_CTRL
, FALSE
, sizeof (PowerCtrl
), &PowerCtrl
);
845 Set the SD/MMC bus width.
847 Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
849 @param[in] PciIo The PCI IO protocol instance.
850 @param[in] Slot The slot number of the SD card to send the command to.
851 @param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.
853 @retval EFI_SUCCESS The bus width is set successfully.
854 @retval Others The bus width isn't set successfully.
859 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
868 HostCtrl1
= (UINT8
)~(BIT5
| BIT1
);
869 Status
= SdMmcHcAndMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
870 } else if (BusWidth
== 4) {
871 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, TRUE
, sizeof (HostCtrl1
), &HostCtrl1
);
872 if (EFI_ERROR (Status
)) {
876 HostCtrl1
&= (UINT8
)~BIT5
;
877 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, FALSE
, sizeof (HostCtrl1
), &HostCtrl1
);
878 } else if (BusWidth
== 8) {
879 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, TRUE
, sizeof (HostCtrl1
), &HostCtrl1
);
880 if (EFI_ERROR (Status
)) {
883 HostCtrl1
&= (UINT8
)~BIT1
;
885 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, FALSE
, sizeof (HostCtrl1
), &HostCtrl1
);
888 return EFI_INVALID_PARAMETER
;
895 Supply SD/MMC card with lowest clock frequency at initialization.
897 @param[in] PciIo The PCI IO protocol instance.
898 @param[in] Slot The slot number of the SD card to send the command to.
899 @param[in] Capability The capability of the slot.
901 @retval EFI_SUCCESS The clock is supplied successfully.
902 @retval Others The clock isn't supplied successfully.
906 SdMmcHcInitClockFreq (
907 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
909 IN SD_MMC_HC_SLOT_CAP Capability
916 // Calculate a divisor for SD clock frequency
918 if (Capability
.BaseClkFreq
== 0) {
920 // Don't support get Base Clock Frequency information via another method
922 return EFI_UNSUPPORTED
;
925 // Supply 400KHz clock frequency at initialization phase.
928 Status
= SdMmcHcClockSupply (PciIo
, Slot
, InitFreq
, Capability
);
933 Supply SD/MMC card with maximum voltage at initialization.
935 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
937 @param[in] PciIo The PCI IO protocol instance.
938 @param[in] Slot The slot number of the SD card to send the command to.
939 @param[in] Capability The capability of the slot.
941 @retval EFI_SUCCESS The voltage is supplied successfully.
942 @retval Others The voltage isn't supplied successfully.
946 SdMmcHcInitPowerVoltage (
947 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
949 IN SD_MMC_HC_SLOT_CAP Capability
957 // Calculate supported maximum voltage according to SD Bus Voltage Select
959 if (Capability
.Voltage33
!= 0) {
964 } else if (Capability
.Voltage30
!= 0) {
969 } else if (Capability
.Voltage18
!= 0) {
975 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL2
, sizeof (HostCtrl2
), &HostCtrl2
);
977 if (EFI_ERROR (Status
)) {
982 return EFI_DEVICE_ERROR
;
986 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
988 Status
= SdMmcHcPowerControl (PciIo
, Slot
, MaxVoltage
);
994 Initialize the Timeout Control register with most conservative value at initialization.
996 Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
998 @param[in] PciIo The PCI IO protocol instance.
999 @param[in] Slot The slot number of the SD card to send the command to.
1001 @retval EFI_SUCCESS The timeout control register is configured successfully.
1002 @retval Others The timeout control register isn't configured successfully.
1006 SdMmcHcInitTimeoutCtrl (
1007 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1015 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_TIMEOUT_CTRL
, FALSE
, sizeof (Timeout
), &Timeout
);
1021 Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value
1024 @param[in] PciIo The PCI IO protocol instance.
1025 @param[in] Slot The slot number of the SD card to send the command to.
1026 @param[in] Capability The capability of the slot.
1028 @retval EFI_SUCCESS The host controller is initialized successfully.
1029 @retval Others The host controller isn't initialized successfully.
1034 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1036 IN SD_MMC_HC_SLOT_CAP Capability
1041 Status
= SdMmcHcInitClockFreq (PciIo
, Slot
, Capability
);
1042 if (EFI_ERROR (Status
)) {
1046 Status
= SdMmcHcInitPowerVoltage (PciIo
, Slot
, Capability
);
1047 if (EFI_ERROR (Status
)) {
1051 Status
= SdMmcHcInitTimeoutCtrl (PciIo
, Slot
);
1058 @param[in] PciIo The PCI IO protocol instance.
1059 @param[in] Slot The slot number of the SD card to send the command to.
1060 @param[in] On The boolean to turn on/off LED.
1062 @retval EFI_SUCCESS The LED is turned on/off successfully.
1063 @retval Others The LED isn't turned on/off successfully.
1068 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1078 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
1080 HostCtrl1
= (UINT8
)~BIT0
;
1081 Status
= SdMmcHcAndMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
1088 Build ADMA descriptor table for transfer.
1090 Refer to SD Host Controller Simplified spec 3.0 Section 1.13 for details.
1092 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1094 @retval EFI_SUCCESS The ADMA descriptor table is created successfully.
1095 @retval Others The ADMA descriptor table isn't created successfully.
1099 BuildAdmaDescTable (
1100 IN SD_MMC_HC_TRB
*Trb
1103 EFI_PHYSICAL_ADDRESS Data
;
1110 EFI_PCI_IO_PROTOCOL
*PciIo
;
1114 Data
= Trb
->DataPhy
;
1115 DataLen
= Trb
->DataLen
;
1116 PciIo
= Trb
->Private
->PciIo
;
1118 // Only support 32bit ADMA Descriptor Table
1120 if ((Data
>= 0x100000000ul
) || ((Data
+ DataLen
) > 0x100000000ul
)) {
1121 return EFI_INVALID_PARAMETER
;
1124 // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)
1125 // for 32-bit address descriptor table.
1127 if ((Data
& (BIT0
| BIT1
)) != 0) {
1128 DEBUG ((EFI_D_INFO
, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data
));
1131 Entries
= DivU64x32 ((DataLen
+ ADMA_MAX_DATA_PER_LINE
- 1), ADMA_MAX_DATA_PER_LINE
);
1132 TableSize
= (UINTN
)MultU64x32 (Entries
, sizeof (SD_MMC_HC_ADMA_DESC_LINE
));
1133 Trb
->AdmaPages
= (UINT32
)EFI_SIZE_TO_PAGES (TableSize
);
1134 Status
= PciIo
->AllocateBuffer (
1137 EfiBootServicesData
,
1138 EFI_SIZE_TO_PAGES (TableSize
),
1139 (VOID
**)&Trb
->AdmaDesc
,
1142 if (EFI_ERROR (Status
)) {
1143 return EFI_OUT_OF_RESOURCES
;
1145 ZeroMem (Trb
->AdmaDesc
, TableSize
);
1147 Status
= PciIo
->Map (
1149 EfiPciIoOperationBusMasterCommonBuffer
,
1156 if (EFI_ERROR (Status
) || (Bytes
!= TableSize
)) {
1158 // Map error or unable to map the whole RFis buffer into a contiguous region.
1162 EFI_SIZE_TO_PAGES (TableSize
),
1165 return EFI_OUT_OF_RESOURCES
;
1168 if ((UINT64
)(UINTN
)Trb
->AdmaDescPhy
> 0x100000000ul
) {
1170 // The ADMA doesn't support 64bit addressing.
1178 EFI_SIZE_TO_PAGES (TableSize
),
1181 return EFI_DEVICE_ERROR
;
1184 Remaining
= DataLen
;
1185 Address
= (UINT32
)Data
;
1186 for (Index
= 0; Index
< Entries
; Index
++) {
1187 if (Remaining
<= ADMA_MAX_DATA_PER_LINE
) {
1188 Trb
->AdmaDesc
[Index
].Valid
= 1;
1189 Trb
->AdmaDesc
[Index
].Act
= 2;
1190 Trb
->AdmaDesc
[Index
].Length
= (UINT16
)Remaining
;
1191 Trb
->AdmaDesc
[Index
].Address
= Address
;
1194 Trb
->AdmaDesc
[Index
].Valid
= 1;
1195 Trb
->AdmaDesc
[Index
].Act
= 2;
1196 Trb
->AdmaDesc
[Index
].Length
= 0;
1197 Trb
->AdmaDesc
[Index
].Address
= Address
;
1200 Remaining
-= ADMA_MAX_DATA_PER_LINE
;
1201 Address
+= ADMA_MAX_DATA_PER_LINE
;
1205 // Set the last descriptor line as end of descriptor table
1207 Trb
->AdmaDesc
[Index
].End
= 1;
1212 Create a new TRB for the SD/MMC cmd request.
1214 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1215 @param[in] Slot The slot number of the SD card to send the command to.
1216 @param[in] Packet A pointer to the SD command data structure.
1217 @param[in] Event If Event is NULL, blocking I/O is performed. If Event is
1218 not NULL, then nonblocking I/O is performed, and Event
1219 will be signaled when the Packet completes.
1221 @return Created Trb or NULL.
1226 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1228 IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
,
1235 EFI_PCI_IO_PROTOCOL_OPERATION Flag
;
1236 EFI_PCI_IO_PROTOCOL
*PciIo
;
1239 Trb
= AllocateZeroPool (sizeof (SD_MMC_HC_TRB
));
1244 Trb
->Signature
= SD_MMC_HC_TRB_SIG
;
1246 Trb
->BlockSize
= 0x200;
1247 Trb
->Packet
= Packet
;
1249 Trb
->Started
= FALSE
;
1250 Trb
->Timeout
= Packet
->Timeout
;
1251 Trb
->Private
= Private
;
1253 if ((Packet
->InTransferLength
!= 0) && (Packet
->InDataBuffer
!= NULL
)) {
1254 Trb
->Data
= Packet
->InDataBuffer
;
1255 Trb
->DataLen
= Packet
->InTransferLength
;
1257 } else if ((Packet
->OutTransferLength
!= 0) && (Packet
->OutDataBuffer
!= NULL
)) {
1258 Trb
->Data
= Packet
->OutDataBuffer
;
1259 Trb
->DataLen
= Packet
->OutTransferLength
;
1261 } else if ((Packet
->InTransferLength
== 0) && (Packet
->OutTransferLength
== 0)) {
1268 if (Trb
->DataLen
< Trb
->BlockSize
) {
1269 Trb
->BlockSize
= (UINT16
)Trb
->DataLen
;
1272 if (((Private
->Slot
[Trb
->Slot
].CardType
== EmmcCardType
) &&
1273 (Packet
->SdMmcCmdBlk
->CommandIndex
== EMMC_SEND_TUNING_BLOCK
)) ||
1274 ((Private
->Slot
[Trb
->Slot
].CardType
== SdCardType
) &&
1275 (Packet
->SdMmcCmdBlk
->CommandIndex
== SD_SEND_TUNING_BLOCK
))) {
1276 Trb
->Mode
= SdMmcPioMode
;
1279 Flag
= EfiPciIoOperationBusMasterWrite
;
1281 Flag
= EfiPciIoOperationBusMasterRead
;
1284 PciIo
= Private
->PciIo
;
1285 if (Trb
->DataLen
!= 0) {
1286 MapLength
= Trb
->DataLen
;
1287 Status
= PciIo
->Map (
1295 if (EFI_ERROR (Status
) || (Trb
->DataLen
!= MapLength
)) {
1296 Status
= EFI_BAD_BUFFER_SIZE
;
1301 if (Trb
->DataLen
== 0) {
1302 Trb
->Mode
= SdMmcNoData
;
1303 } else if (Private
->Capability
[Slot
].Adma2
!= 0) {
1304 Trb
->Mode
= SdMmcAdmaMode
;
1305 Status
= BuildAdmaDescTable (Trb
);
1306 if (EFI_ERROR (Status
)) {
1307 PciIo
->Unmap (PciIo
, Trb
->DataMap
);
1310 } else if (Private
->Capability
[Slot
].Sdma
!= 0) {
1311 Trb
->Mode
= SdMmcSdmaMode
;
1313 Trb
->Mode
= SdMmcPioMode
;
1317 if (Event
!= NULL
) {
1318 OldTpl
= gBS
->RaiseTPL (TPL_CALLBACK
);
1319 InsertTailList (&Private
->Queue
, &Trb
->TrbList
);
1320 gBS
->RestoreTPL (OldTpl
);
1331 Free the resource used by the TRB.
1333 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1338 IN SD_MMC_HC_TRB
*Trb
1341 EFI_PCI_IO_PROTOCOL
*PciIo
;
1343 PciIo
= Trb
->Private
->PciIo
;
1345 if (Trb
->AdmaMap
!= NULL
) {
1351 if (Trb
->AdmaDesc
!= NULL
) {
1358 if (Trb
->DataMap
!= NULL
) {
1369 Check if the env is ready for execute specified TRB.
1371 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1372 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1374 @retval EFI_SUCCESS The env is ready for TRB execution.
1375 @retval EFI_NOT_READY The env is not ready for TRB execution.
1376 @retval Others Some erros happen.
1381 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1382 IN SD_MMC_HC_TRB
*Trb
1386 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
1387 EFI_PCI_IO_PROTOCOL
*PciIo
;
1388 UINT32 PresentState
;
1390 Packet
= Trb
->Packet
;
1392 if ((Packet
->SdMmcCmdBlk
->CommandType
== SdMmcCommandTypeAdtc
) ||
1393 (Packet
->SdMmcCmdBlk
->ResponseType
== SdMmcResponseTypeR1b
) ||
1394 (Packet
->SdMmcCmdBlk
->ResponseType
== SdMmcResponseTypeR5b
)) {
1396 // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in
1397 // the Present State register to be 0
1399 PresentState
= BIT0
| BIT1
;
1402 // Wait Command Inhibit (CMD) in the Present State register
1405 PresentState
= BIT0
;
1408 PciIo
= Private
->PciIo
;
1409 Status
= SdMmcHcCheckMmioSet (
1412 SD_MMC_HC_PRESENT_STATE
,
1413 sizeof (PresentState
),
1422 Wait for the env to be ready for execute specified TRB.
1424 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1425 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1427 @retval EFI_SUCCESS The env is ready for TRB execution.
1428 @retval EFI_TIMEOUT The env is not ready for TRB execution in time.
1429 @retval Others Some erros happen.
1434 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1435 IN SD_MMC_HC_TRB
*Trb
1439 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
1441 BOOLEAN InfiniteWait
;
1444 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1446 Packet
= Trb
->Packet
;
1447 Timeout
= Packet
->Timeout
;
1449 InfiniteWait
= TRUE
;
1451 InfiniteWait
= FALSE
;
1454 while (InfiniteWait
|| (Timeout
> 0)) {
1456 // Check Trb execution result by reading Normal Interrupt Status register.
1458 Status
= SdMmcCheckTrbEnv (Private
, Trb
);
1459 if (Status
!= EFI_NOT_READY
) {
1463 // Stall for 1 microsecond.
1474 Execute the specified TRB.
1476 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1477 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1479 @retval EFI_SUCCESS The TRB is sent to host controller successfully.
1480 @retval Others Some erros happen when sending this request to the host controller.
1485 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1486 IN SD_MMC_HC_TRB
*Trb
1490 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
1491 EFI_PCI_IO_PROTOCOL
*PciIo
;
1502 Packet
= Trb
->Packet
;
1503 PciIo
= Trb
->Private
->PciIo
;
1505 // Clear all bits in Error Interrupt Status Register
1508 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_ERR_INT_STS
, FALSE
, sizeof (IntStatus
), &IntStatus
);
1509 if (EFI_ERROR (Status
)) {
1513 // Clear all bits in Normal Interrupt Status Register excepts for Card Removal & Card Insertion bits.
1516 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_NOR_INT_STS
, FALSE
, sizeof (IntStatus
), &IntStatus
);
1517 if (EFI_ERROR (Status
)) {
1521 // Set Host Control 1 register DMA Select field
1523 if (Trb
->Mode
== SdMmcAdmaMode
) {
1525 Status
= SdMmcHcOrMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
1526 if (EFI_ERROR (Status
)) {
1531 SdMmcHcLedOnOff (PciIo
, Trb
->Slot
, TRUE
);
1533 if (Trb
->Mode
== SdMmcSdmaMode
) {
1534 if ((UINT64
)(UINTN
)Trb
->DataPhy
>= 0x100000000ul
) {
1535 return EFI_INVALID_PARAMETER
;
1538 SdmaAddr
= (UINT32
)(UINTN
)Trb
->DataPhy
;
1539 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_SDMA_ADDR
, FALSE
, sizeof (SdmaAddr
), &SdmaAddr
);
1540 if (EFI_ERROR (Status
)) {
1543 } else if (Trb
->Mode
== SdMmcAdmaMode
) {
1544 AdmaAddr
= (UINT64
)(UINTN
)Trb
->AdmaDescPhy
;
1545 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_ADMA_SYS_ADDR
, FALSE
, sizeof (AdmaAddr
), &AdmaAddr
);
1546 if (EFI_ERROR (Status
)) {
1551 BlkSize
= Trb
->BlockSize
;
1552 if (Trb
->Mode
== SdMmcSdmaMode
) {
1554 // Set SDMA boundary to be 512K bytes.
1559 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_BLK_SIZE
, FALSE
, sizeof (BlkSize
), &BlkSize
);
1560 if (EFI_ERROR (Status
)) {
1565 if (Trb
->Mode
!= SdMmcNoData
) {
1567 // Calcuate Block Count.
1569 BlkCount
= (UINT16
)(Trb
->DataLen
/ Trb
->BlockSize
);
1571 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_BLK_COUNT
, FALSE
, sizeof (BlkCount
), &BlkCount
);
1572 if (EFI_ERROR (Status
)) {
1576 Argument
= Packet
->SdMmcCmdBlk
->CommandArgument
;
1577 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_ARG1
, FALSE
, sizeof (Argument
), &Argument
);
1578 if (EFI_ERROR (Status
)) {
1583 if (Trb
->Mode
!= SdMmcNoData
) {
1584 if (Trb
->Mode
!= SdMmcPioMode
) {
1591 TransMode
|= BIT5
| BIT1
;
1594 // Only SD memory card needs to use AUTO CMD12 feature.
1596 if (Private
->Slot
[Trb
->Slot
].CardType
== SdCardType
) {
1603 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_TRANS_MOD
, FALSE
, sizeof (TransMode
), &TransMode
);
1604 if (EFI_ERROR (Status
)) {
1608 Cmd
= (UINT16
)LShiftU64(Packet
->SdMmcCmdBlk
->CommandIndex
, 8);
1609 if (Packet
->SdMmcCmdBlk
->CommandType
== SdMmcCommandTypeAdtc
) {
1613 // Convert ResponseType to value
1615 if (Packet
->SdMmcCmdBlk
->CommandType
!= SdMmcCommandTypeBc
) {
1616 switch (Packet
->SdMmcCmdBlk
->ResponseType
) {
1617 case SdMmcResponseTypeR1
:
1618 case SdMmcResponseTypeR5
:
1619 case SdMmcResponseTypeR6
:
1620 case SdMmcResponseTypeR7
:
1621 Cmd
|= (BIT1
| BIT3
| BIT4
);
1623 case SdMmcResponseTypeR2
:
1624 Cmd
|= (BIT0
| BIT3
);
1626 case SdMmcResponseTypeR3
:
1627 case SdMmcResponseTypeR4
:
1630 case SdMmcResponseTypeR1b
:
1631 case SdMmcResponseTypeR5b
:
1632 Cmd
|= (BIT0
| BIT1
| BIT3
| BIT4
);
1642 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_COMMAND
, FALSE
, sizeof (Cmd
), &Cmd
);
1647 Check the TRB execution result.
1649 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1650 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1652 @retval EFI_SUCCESS The TRB is executed successfully.
1653 @retval EFI_NOT_READY The TRB is not completed for execution.
1654 @retval Others Some erros happen when executing this request.
1658 SdMmcCheckTrbResult (
1659 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1660 IN SD_MMC_HC_TRB
*Trb
1664 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
1673 Packet
= Trb
->Packet
;
1675 // Check Trb execution result by reading Normal Interrupt Status register.
1677 Status
= SdMmcHcRwMmio (
1680 SD_MMC_HC_NOR_INT_STS
,
1685 if (EFI_ERROR (Status
)) {
1689 // Check Transfer Complete bit is set or not.
1691 if ((IntStatus
& BIT1
) == BIT1
) {
1692 if ((IntStatus
& BIT15
) == BIT15
) {
1694 // Read Error Interrupt Status register to check if the error is
1695 // Data Timeout Error.
1696 // If yes, treat it as success as Transfer Complete has higher
1697 // priority than Data Timeout Error.
1699 Status
= SdMmcHcRwMmio (
1702 SD_MMC_HC_ERR_INT_STS
,
1707 if (!EFI_ERROR (Status
)) {
1708 if ((IntStatus
& BIT4
) == BIT4
) {
1709 Status
= EFI_SUCCESS
;
1711 Status
= EFI_DEVICE_ERROR
;
1719 // Check if there is a error happened during cmd execution.
1720 // If yes, then do error recovery procedure to follow SD Host Controller
1721 // Simplified Spec 3.0 section 3.10.1.
1723 if ((IntStatus
& BIT15
) == BIT15
) {
1724 Status
= SdMmcHcRwMmio (
1727 SD_MMC_HC_ERR_INT_STS
,
1732 if (EFI_ERROR (Status
)) {
1735 if ((IntStatus
& 0x0F) != 0) {
1738 if ((IntStatus
& 0xF0) != 0) {
1742 Status
= SdMmcHcRwMmio (
1750 if (EFI_ERROR (Status
)) {
1753 Status
= SdMmcHcWaitMmioSet (
1760 SD_MMC_HC_GENERIC_TIMEOUT
1762 if (EFI_ERROR (Status
)) {
1766 Status
= EFI_DEVICE_ERROR
;
1770 // Check if DMA interrupt is signalled for the SDMA transfer.
1772 if ((Trb
->Mode
== SdMmcSdmaMode
) && ((IntStatus
& BIT3
) == BIT3
)) {
1774 // Clear DMA interrupt bit.
1777 Status
= SdMmcHcRwMmio (
1780 SD_MMC_HC_NOR_INT_STS
,
1785 if (EFI_ERROR (Status
)) {
1789 // Update SDMA Address register.
1791 SdmaAddr
= SD_MMC_SDMA_ROUND_UP ((UINT32
)(UINTN
)Trb
->DataPhy
, SD_MMC_SDMA_BOUNDARY
);
1792 Status
= SdMmcHcRwMmio (
1795 SD_MMC_HC_SDMA_ADDR
,
1800 if (EFI_ERROR (Status
)) {
1803 Trb
->DataPhy
= (UINT32
)(UINTN
)SdmaAddr
;
1806 if ((Packet
->SdMmcCmdBlk
->CommandType
!= SdMmcCommandTypeAdtc
) &&
1807 (Packet
->SdMmcCmdBlk
->ResponseType
!= SdMmcResponseTypeR1b
) &&
1808 (Packet
->SdMmcCmdBlk
->ResponseType
!= SdMmcResponseTypeR5b
)) {
1809 if ((IntStatus
& BIT0
) == BIT0
) {
1810 Status
= EFI_SUCCESS
;
1815 if (((Private
->Slot
[Trb
->Slot
].CardType
== EmmcCardType
) &&
1816 (Packet
->SdMmcCmdBlk
->CommandIndex
== EMMC_SEND_TUNING_BLOCK
)) ||
1817 ((Private
->Slot
[Trb
->Slot
].CardType
== SdCardType
) &&
1818 (Packet
->SdMmcCmdBlk
->CommandIndex
== SD_SEND_TUNING_BLOCK
))) {
1820 // When performing tuning procedure (Execute Tuning is set to 1) through PIO mode,
1821 // wait Buffer Read Ready bit of Normal Interrupt Status Register to be 1.
1822 // Refer to SD Host Controller Simplified Specification 3.0 figure 2-29 for details.
1824 if ((IntStatus
& BIT5
) == BIT5
) {
1826 // Clear Buffer Read Ready interrupt at first.
1829 SdMmcHcRwMmio (Private
->PciIo
, Trb
->Slot
, SD_MMC_HC_NOR_INT_STS
, FALSE
, sizeof (IntStatus
), &IntStatus
);
1831 // Read data out from Buffer Port register
1833 for (PioLength
= 0; PioLength
< Trb
->DataLen
; PioLength
+= 4) {
1834 SdMmcHcRwMmio (Private
->PciIo
, Trb
->Slot
, SD_MMC_HC_BUF_DAT_PORT
, TRUE
, 4, (UINT8
*)Trb
->Data
+ PioLength
);
1836 Status
= EFI_SUCCESS
;
1841 Status
= EFI_NOT_READY
;
1844 // Get response data when the cmd is executed successfully.
1846 if (!EFI_ERROR (Status
)) {
1847 if (Packet
->SdMmcCmdBlk
->CommandType
!= SdMmcCommandTypeBc
) {
1848 for (Index
= 0; Index
< 4; Index
++) {
1849 Status
= SdMmcHcRwMmio (
1852 SD_MMC_HC_RESPONSE
+ Index
* 4,
1857 if (EFI_ERROR (Status
)) {
1858 SdMmcHcLedOnOff (Private
->PciIo
, Trb
->Slot
, FALSE
);
1862 CopyMem (Packet
->SdMmcStatusBlk
, Response
, sizeof (Response
));
1866 if (Status
!= EFI_NOT_READY
) {
1867 SdMmcHcLedOnOff (Private
->PciIo
, Trb
->Slot
, FALSE
);
1874 Wait for the TRB execution result.
1876 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1877 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1879 @retval EFI_SUCCESS The TRB is executed successfully.
1880 @retval Others Some erros happen when executing this request.
1884 SdMmcWaitTrbResult (
1885 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1886 IN SD_MMC_HC_TRB
*Trb
1890 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
1892 BOOLEAN InfiniteWait
;
1894 Packet
= Trb
->Packet
;
1896 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1898 Timeout
= Packet
->Timeout
;
1900 InfiniteWait
= TRUE
;
1902 InfiniteWait
= FALSE
;
1905 while (InfiniteWait
|| (Timeout
> 0)) {
1907 // Check Trb execution result by reading Normal Interrupt Status register.
1909 Status
= SdMmcCheckTrbResult (Private
, Trb
);
1910 if (Status
!= EFI_NOT_READY
) {
1914 // Stall for 1 microsecond.