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UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / SdMmcPciHcDxe / SdMmcPciHci.c
1 /** @file
2 This driver is used to manage SD/MMC PCI host controllers which are compliance
3 with SD Host Controller Simplified Specification version 3.00 plus the 64-bit
4 System Addressing support in SD Host Controller Simplified Specification version
5 4.20.
6
7 It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
8
9 Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
10 Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.<BR>
11 SPDX-License-Identifier: BSD-2-Clause-Patent
12
13 **/
14
15 #include "SdMmcPciHcDxe.h"
16
17 /**
18 Dump the content of SD/MMC host controller's Capability Register.
19
20 @param[in] Slot The slot number of the SD card to send the command to.
21 @param[in] Capability The buffer to store the capability data.
22
23 **/
24 VOID
25 DumpCapabilityReg (
26 IN UINT8 Slot,
27 IN SD_MMC_HC_SLOT_CAP *Capability
28 )
29 {
30 //
31 // Dump Capability Data
32 //
33 DEBUG ((DEBUG_INFO, " == Slot [%d] Capability is 0x%x ==\n", Slot, Capability));
34 DEBUG ((DEBUG_INFO, " Timeout Clk Freq %d%a\n", Capability->TimeoutFreq, (Capability->TimeoutUnit) ? "MHz" : "KHz"));
35 DEBUG ((DEBUG_INFO, " Base Clk Freq %dMHz\n", Capability->BaseClkFreq));
36 DEBUG ((DEBUG_INFO, " Max Blk Len %dbytes\n", 512 * (1 << Capability->MaxBlkLen)));
37 DEBUG ((DEBUG_INFO, " 8-bit Support %a\n", Capability->BusWidth8 ? "TRUE" : "FALSE"));
38 DEBUG ((DEBUG_INFO, " ADMA2 Support %a\n", Capability->Adma2 ? "TRUE" : "FALSE"));
39 DEBUG ((DEBUG_INFO, " HighSpeed Support %a\n", Capability->HighSpeed ? "TRUE" : "FALSE"));
40 DEBUG ((DEBUG_INFO, " SDMA Support %a\n", Capability->Sdma ? "TRUE" : "FALSE"));
41 DEBUG ((DEBUG_INFO, " Suspend/Resume %a\n", Capability->SuspRes ? "TRUE" : "FALSE"));
42 DEBUG ((DEBUG_INFO, " Voltage 3.3 %a\n", Capability->Voltage33 ? "TRUE" : "FALSE"));
43 DEBUG ((DEBUG_INFO, " Voltage 3.0 %a\n", Capability->Voltage30 ? "TRUE" : "FALSE"));
44 DEBUG ((DEBUG_INFO, " Voltage 1.8 %a\n", Capability->Voltage18 ? "TRUE" : "FALSE"));
45 DEBUG ((DEBUG_INFO, " V4 64-bit Sys Bus %a\n", Capability->SysBus64V4 ? "TRUE" : "FALSE"));
46 DEBUG ((DEBUG_INFO, " V3 64-bit Sys Bus %a\n", Capability->SysBus64V3 ? "TRUE" : "FALSE"));
47 DEBUG ((DEBUG_INFO, " Async Interrupt %a\n", Capability->AsyncInt ? "TRUE" : "FALSE"));
48 DEBUG ((DEBUG_INFO, " SlotType "));
49 if (Capability->SlotType == 0x00) {
50 DEBUG ((DEBUG_INFO, "%a\n", "Removable Slot"));
51 } else if (Capability->SlotType == 0x01) {
52 DEBUG ((DEBUG_INFO, "%a\n", "Embedded Slot"));
53 } else if (Capability->SlotType == 0x02) {
54 DEBUG ((DEBUG_INFO, "%a\n", "Shared Bus Slot"));
55 } else {
56 DEBUG ((DEBUG_INFO, "%a\n", "Reserved"));
57 }
58
59 DEBUG ((DEBUG_INFO, " SDR50 Support %a\n", Capability->Sdr50 ? "TRUE" : "FALSE"));
60 DEBUG ((DEBUG_INFO, " SDR104 Support %a\n", Capability->Sdr104 ? "TRUE" : "FALSE"));
61 DEBUG ((DEBUG_INFO, " DDR50 Support %a\n", Capability->Ddr50 ? "TRUE" : "FALSE"));
62 DEBUG ((DEBUG_INFO, " Driver Type A %a\n", Capability->DriverTypeA ? "TRUE" : "FALSE"));
63 DEBUG ((DEBUG_INFO, " Driver Type C %a\n", Capability->DriverTypeC ? "TRUE" : "FALSE"));
64 DEBUG ((DEBUG_INFO, " Driver Type D %a\n", Capability->DriverTypeD ? "TRUE" : "FALSE"));
65 DEBUG ((DEBUG_INFO, " Driver Type 4 %a\n", Capability->DriverType4 ? "TRUE" : "FALSE"));
66 if (Capability->TimerCount == 0) {
67 DEBUG ((DEBUG_INFO, " Retuning TimerCnt Disabled\n"));
68 } else {
69 DEBUG ((DEBUG_INFO, " Retuning TimerCnt %dseconds\n", 2 * (Capability->TimerCount - 1)));
70 }
71
72 DEBUG ((DEBUG_INFO, " SDR50 Tuning %a\n", Capability->TuningSDR50 ? "TRUE" : "FALSE"));
73 DEBUG ((DEBUG_INFO, " Retuning Mode Mode %d\n", Capability->RetuningMod + 1));
74 DEBUG ((DEBUG_INFO, " Clock Multiplier M = %d\n", Capability->ClkMultiplier + 1));
75 DEBUG ((DEBUG_INFO, " HS 400 %a\n", Capability->Hs400 ? "TRUE" : "FALSE"));
76 return;
77 }
78
79 /**
80 Read SlotInfo register from SD/MMC host controller pci config space.
81
82 @param[in] PciIo The PCI IO protocol instance.
83 @param[out] FirstBar The buffer to store the first BAR value.
84 @param[out] SlotNum The buffer to store the supported slot number.
85
86 @retval EFI_SUCCESS The operation succeeds.
87 @retval Others The operation fails.
88
89 **/
90 EFI_STATUS
91 EFIAPI
92 SdMmcHcGetSlotInfo (
93 IN EFI_PCI_IO_PROTOCOL *PciIo,
94 OUT UINT8 *FirstBar,
95 OUT UINT8 *SlotNum
96 )
97 {
98 EFI_STATUS Status;
99 SD_MMC_HC_SLOT_INFO SlotInfo;
100
101 Status = PciIo->Pci.Read (
102 PciIo,
103 EfiPciIoWidthUint8,
104 SD_MMC_HC_SLOT_OFFSET,
105 sizeof (SlotInfo),
106 &SlotInfo
107 );
108 if (EFI_ERROR (Status)) {
109 return Status;
110 }
111
112 *FirstBar = SlotInfo.FirstBar;
113 *SlotNum = SlotInfo.SlotNum + 1;
114 ASSERT ((*FirstBar + *SlotNum) < SD_MMC_HC_MAX_SLOT);
115 return EFI_SUCCESS;
116 }
117
118 /**
119 Read/Write specified SD/MMC host controller mmio register.
120
121 @param[in] PciIo The PCI IO protocol instance.
122 @param[in] BarIndex The BAR index of the standard PCI Configuration
123 header to use as the base address for the memory
124 operation to perform.
125 @param[in] Offset The offset within the selected BAR to start the
126 memory operation.
127 @param[in] Read A boolean to indicate it's read or write operation.
128 @param[in] Count The width of the mmio register in bytes.
129 Must be 1, 2 , 4 or 8 bytes.
130 @param[in, out] Data For read operations, the destination buffer to store
131 the results. For write operations, the source buffer
132 to write data from. The caller is responsible for
133 having ownership of the data buffer and ensuring its
134 size not less than Count bytes.
135
136 @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
137 @retval EFI_SUCCESS The read/write operation succeeds.
138 @retval Others The read/write operation fails.
139
140 **/
141 EFI_STATUS
142 EFIAPI
143 SdMmcHcRwMmio (
144 IN EFI_PCI_IO_PROTOCOL *PciIo,
145 IN UINT8 BarIndex,
146 IN UINT32 Offset,
147 IN BOOLEAN Read,
148 IN UINT8 Count,
149 IN OUT VOID *Data
150 )
151 {
152 EFI_STATUS Status;
153 EFI_PCI_IO_PROTOCOL_WIDTH Width;
154
155 if ((PciIo == NULL) || (Data == NULL)) {
156 return EFI_INVALID_PARAMETER;
157 }
158
159 switch (Count) {
160 case 1:
161 Width = EfiPciIoWidthUint8;
162 break;
163 case 2:
164 Width = EfiPciIoWidthUint16;
165 Count = 1;
166 break;
167 case 4:
168 Width = EfiPciIoWidthUint32;
169 Count = 1;
170 break;
171 case 8:
172 Width = EfiPciIoWidthUint32;
173 Count = 2;
174 break;
175 default:
176 return EFI_INVALID_PARAMETER;
177 }
178
179 if (Read) {
180 Status = PciIo->Mem.Read (
181 PciIo,
182 Width,
183 BarIndex,
184 (UINT64)Offset,
185 Count,
186 Data
187 );
188 } else {
189 Status = PciIo->Mem.Write (
190 PciIo,
191 Width,
192 BarIndex,
193 (UINT64)Offset,
194 Count,
195 Data
196 );
197 }
198
199 return Status;
200 }
201
202 /**
203 Do OR operation with the value of the specified SD/MMC host controller mmio register.
204
205 @param[in] PciIo The PCI IO protocol instance.
206 @param[in] BarIndex The BAR index of the standard PCI Configuration
207 header to use as the base address for the memory
208 operation to perform.
209 @param[in] Offset The offset within the selected BAR to start the
210 memory operation.
211 @param[in] Count The width of the mmio register in bytes.
212 Must be 1, 2 , 4 or 8 bytes.
213 @param[in] OrData The pointer to the data used to do OR operation.
214 The caller is responsible for having ownership of
215 the data buffer and ensuring its size not less than
216 Count bytes.
217
218 @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
219 @retval EFI_SUCCESS The OR operation succeeds.
220 @retval Others The OR operation fails.
221
222 **/
223 EFI_STATUS
224 EFIAPI
225 SdMmcHcOrMmio (
226 IN EFI_PCI_IO_PROTOCOL *PciIo,
227 IN UINT8 BarIndex,
228 IN UINT32 Offset,
229 IN UINT8 Count,
230 IN VOID *OrData
231 )
232 {
233 EFI_STATUS Status;
234 UINT64 Data;
235 UINT64 Or;
236
237 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
238 if (EFI_ERROR (Status)) {
239 return Status;
240 }
241
242 if (Count == 1) {
243 Or = *(UINT8 *)OrData;
244 } else if (Count == 2) {
245 Or = *(UINT16 *)OrData;
246 } else if (Count == 4) {
247 Or = *(UINT32 *)OrData;
248 } else if (Count == 8) {
249 Or = *(UINT64 *)OrData;
250 } else {
251 return EFI_INVALID_PARAMETER;
252 }
253
254 Data |= Or;
255 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
256
257 return Status;
258 }
259
260 /**
261 Do AND operation with the value of the specified SD/MMC host controller mmio register.
262
263 @param[in] PciIo The PCI IO protocol instance.
264 @param[in] BarIndex The BAR index of the standard PCI Configuration
265 header to use as the base address for the memory
266 operation to perform.
267 @param[in] Offset The offset within the selected BAR to start the
268 memory operation.
269 @param[in] Count The width of the mmio register in bytes.
270 Must be 1, 2 , 4 or 8 bytes.
271 @param[in] AndData The pointer to the data used to do AND operation.
272 The caller is responsible for having ownership of
273 the data buffer and ensuring its size not less than
274 Count bytes.
275
276 @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
277 @retval EFI_SUCCESS The AND operation succeeds.
278 @retval Others The AND operation fails.
279
280 **/
281 EFI_STATUS
282 EFIAPI
283 SdMmcHcAndMmio (
284 IN EFI_PCI_IO_PROTOCOL *PciIo,
285 IN UINT8 BarIndex,
286 IN UINT32 Offset,
287 IN UINT8 Count,
288 IN VOID *AndData
289 )
290 {
291 EFI_STATUS Status;
292 UINT64 Data;
293 UINT64 And;
294
295 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
296 if (EFI_ERROR (Status)) {
297 return Status;
298 }
299
300 if (Count == 1) {
301 And = *(UINT8 *)AndData;
302 } else if (Count == 2) {
303 And = *(UINT16 *)AndData;
304 } else if (Count == 4) {
305 And = *(UINT32 *)AndData;
306 } else if (Count == 8) {
307 And = *(UINT64 *)AndData;
308 } else {
309 return EFI_INVALID_PARAMETER;
310 }
311
312 Data &= And;
313 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
314
315 return Status;
316 }
317
318 /**
319 Wait for the value of the specified MMIO register set to the test value.
320
321 @param[in] PciIo The PCI IO protocol instance.
322 @param[in] BarIndex The BAR index of the standard PCI Configuration
323 header to use as the base address for the memory
324 operation to perform.
325 @param[in] Offset The offset within the selected BAR to start the
326 memory operation.
327 @param[in] Count The width of the mmio register in bytes.
328 Must be 1, 2, 4 or 8 bytes.
329 @param[in] MaskValue The mask value of memory.
330 @param[in] TestValue The test value of memory.
331
332 @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.
333 @retval EFI_SUCCESS The MMIO register has expected value.
334 @retval Others The MMIO operation fails.
335
336 **/
337 EFI_STATUS
338 EFIAPI
339 SdMmcHcCheckMmioSet (
340 IN EFI_PCI_IO_PROTOCOL *PciIo,
341 IN UINT8 BarIndex,
342 IN UINT32 Offset,
343 IN UINT8 Count,
344 IN UINT64 MaskValue,
345 IN UINT64 TestValue
346 )
347 {
348 EFI_STATUS Status;
349 UINT64 Value;
350
351 //
352 // Access PCI MMIO space to see if the value is the tested one.
353 //
354 Value = 0;
355 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Value);
356 if (EFI_ERROR (Status)) {
357 return Status;
358 }
359
360 Value &= MaskValue;
361
362 if (Value == TestValue) {
363 return EFI_SUCCESS;
364 }
365
366 return EFI_NOT_READY;
367 }
368
369 /**
370 Wait for the value of the specified MMIO register set to the test value.
371
372 @param[in] PciIo The PCI IO protocol instance.
373 @param[in] BarIndex The BAR index of the standard PCI Configuration
374 header to use as the base address for the memory
375 operation to perform.
376 @param[in] Offset The offset within the selected BAR to start the
377 memory operation.
378 @param[in] Count The width of the mmio register in bytes.
379 Must be 1, 2, 4 or 8 bytes.
380 @param[in] MaskValue The mask value of memory.
381 @param[in] TestValue The test value of memory.
382 @param[in] Timeout The time out value for wait memory set, uses 1
383 microsecond as a unit.
384
385 @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout
386 range.
387 @retval EFI_SUCCESS The MMIO register has expected value.
388 @retval Others The MMIO operation fails.
389
390 **/
391 EFI_STATUS
392 EFIAPI
393 SdMmcHcWaitMmioSet (
394 IN EFI_PCI_IO_PROTOCOL *PciIo,
395 IN UINT8 BarIndex,
396 IN UINT32 Offset,
397 IN UINT8 Count,
398 IN UINT64 MaskValue,
399 IN UINT64 TestValue,
400 IN UINT64 Timeout
401 )
402 {
403 EFI_STATUS Status;
404 BOOLEAN InfiniteWait;
405
406 if (Timeout == 0) {
407 InfiniteWait = TRUE;
408 } else {
409 InfiniteWait = FALSE;
410 }
411
412 while (InfiniteWait || (Timeout > 0)) {
413 Status = SdMmcHcCheckMmioSet (
414 PciIo,
415 BarIndex,
416 Offset,
417 Count,
418 MaskValue,
419 TestValue
420 );
421 if (Status != EFI_NOT_READY) {
422 return Status;
423 }
424
425 //
426 // Stall for 1 microsecond.
427 //
428 gBS->Stall (1);
429
430 Timeout--;
431 }
432
433 return EFI_TIMEOUT;
434 }
435
436 /**
437 Get the controller version information from the specified slot.
438
439 @param[in] PciIo The PCI IO protocol instance.
440 @param[in] Slot The slot number of the SD card to send the command to.
441 @param[out] Version The buffer to store the version information.
442
443 @retval EFI_SUCCESS The operation executes successfully.
444 @retval Others The operation fails.
445
446 **/
447 EFI_STATUS
448 SdMmcHcGetControllerVersion (
449 IN EFI_PCI_IO_PROTOCOL *PciIo,
450 IN UINT8 Slot,
451 OUT UINT16 *Version
452 )
453 {
454 EFI_STATUS Status;
455
456 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CTRL_VER, TRUE, sizeof (UINT16), Version);
457 if (EFI_ERROR (Status)) {
458 return Status;
459 }
460
461 *Version &= 0xFF;
462
463 return EFI_SUCCESS;
464 }
465
466 /**
467 Software reset the specified SD/MMC host controller and enable all interrupts.
468
469 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
470 @param[in] Slot The slot number of the SD card to send the command to.
471
472 @retval EFI_SUCCESS The software reset executes successfully.
473 @retval Others The software reset fails.
474
475 **/
476 EFI_STATUS
477 SdMmcHcReset (
478 IN SD_MMC_HC_PRIVATE_DATA *Private,
479 IN UINT8 Slot
480 )
481 {
482 EFI_STATUS Status;
483 UINT8 SwReset;
484 EFI_PCI_IO_PROTOCOL *PciIo;
485
486 //
487 // Notify the SD/MMC override protocol that we are about to reset
488 // the SD/MMC host controller.
489 //
490 if ((mOverride != NULL) && (mOverride->NotifyPhase != NULL)) {
491 Status = mOverride->NotifyPhase (
492 Private->ControllerHandle,
493 Slot,
494 EdkiiSdMmcResetPre,
495 NULL
496 );
497 if (EFI_ERROR (Status)) {
498 DEBUG ((
499 DEBUG_WARN,
500 "%a: SD/MMC pre reset notifier callback failed - %r\n",
501 __FUNCTION__,
502 Status
503 ));
504 return Status;
505 }
506 }
507
508 PciIo = Private->PciIo;
509 SwReset = BIT0;
510 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_SW_RST, sizeof (SwReset), &SwReset);
511
512 if (EFI_ERROR (Status)) {
513 DEBUG ((DEBUG_ERROR, "SdMmcHcReset: write SW Reset for All fails: %r\n", Status));
514 return Status;
515 }
516
517 Status = SdMmcHcWaitMmioSet (
518 PciIo,
519 Slot,
520 SD_MMC_HC_SW_RST,
521 sizeof (SwReset),
522 BIT0,
523 0x00,
524 SD_MMC_HC_GENERIC_TIMEOUT
525 );
526 if (EFI_ERROR (Status)) {
527 DEBUG ((DEBUG_INFO, "SdMmcHcReset: reset done with %r\n", Status));
528 return Status;
529 }
530
531 //
532 // Enable all interrupt after reset all.
533 //
534 Status = SdMmcHcEnableInterrupt (PciIo, Slot);
535 if (EFI_ERROR (Status)) {
536 DEBUG ((
537 DEBUG_INFO,
538 "SdMmcHcReset: SdMmcHcEnableInterrupt done with %r\n",
539 Status
540 ));
541 return Status;
542 }
543
544 //
545 // Notify the SD/MMC override protocol that we have just reset
546 // the SD/MMC host controller.
547 //
548 if ((mOverride != NULL) && (mOverride->NotifyPhase != NULL)) {
549 Status = mOverride->NotifyPhase (
550 Private->ControllerHandle,
551 Slot,
552 EdkiiSdMmcResetPost,
553 NULL
554 );
555 if (EFI_ERROR (Status)) {
556 DEBUG ((
557 DEBUG_WARN,
558 "%a: SD/MMC post reset notifier callback failed - %r\n",
559 __FUNCTION__,
560 Status
561 ));
562 }
563 }
564
565 return Status;
566 }
567
568 /**
569 Set all interrupt status bits in Normal and Error Interrupt Status Enable
570 register.
571
572 @param[in] PciIo The PCI IO protocol instance.
573 @param[in] Slot The slot number of the SD card to send the command to.
574
575 @retval EFI_SUCCESS The operation executes successfully.
576 @retval Others The operation fails.
577
578 **/
579 EFI_STATUS
580 SdMmcHcEnableInterrupt (
581 IN EFI_PCI_IO_PROTOCOL *PciIo,
582 IN UINT8 Slot
583 )
584 {
585 EFI_STATUS Status;
586 UINT16 IntStatus;
587
588 //
589 // Enable all bits in Error Interrupt Status Enable Register
590 //
591 IntStatus = 0xFFFF;
592 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
593 if (EFI_ERROR (Status)) {
594 return Status;
595 }
596
597 //
598 // Enable all bits in Normal Interrupt Status Enable Register
599 //
600 IntStatus = 0xFFFF;
601 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
602
603 return Status;
604 }
605
606 /**
607 Get the capability data from the specified slot.
608
609 @param[in] PciIo The PCI IO protocol instance.
610 @param[in] Slot The slot number of the SD card to send the command to.
611 @param[out] Capability The buffer to store the capability data.
612
613 @retval EFI_SUCCESS The operation executes successfully.
614 @retval Others The operation fails.
615
616 **/
617 EFI_STATUS
618 SdMmcHcGetCapability (
619 IN EFI_PCI_IO_PROTOCOL *PciIo,
620 IN UINT8 Slot,
621 OUT SD_MMC_HC_SLOT_CAP *Capability
622 )
623 {
624 EFI_STATUS Status;
625 UINT64 Cap;
626
627 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CAP, TRUE, sizeof (Cap), &Cap);
628 if (EFI_ERROR (Status)) {
629 return Status;
630 }
631
632 CopyMem (Capability, &Cap, sizeof (Cap));
633
634 return EFI_SUCCESS;
635 }
636
637 /**
638 Get the maximum current capability data from the specified slot.
639
640 @param[in] PciIo The PCI IO protocol instance.
641 @param[in] Slot The slot number of the SD card to send the command to.
642 @param[out] MaxCurrent The buffer to store the maximum current capability data.
643
644 @retval EFI_SUCCESS The operation executes successfully.
645 @retval Others The operation fails.
646
647 **/
648 EFI_STATUS
649 SdMmcHcGetMaxCurrent (
650 IN EFI_PCI_IO_PROTOCOL *PciIo,
651 IN UINT8 Slot,
652 OUT UINT64 *MaxCurrent
653 )
654 {
655 EFI_STATUS Status;
656
657 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_MAX_CURRENT_CAP, TRUE, sizeof (UINT64), MaxCurrent);
658
659 return Status;
660 }
661
662 /**
663 Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
664 slot.
665
666 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
667
668 @param[in] PciIo The PCI IO protocol instance.
669 @param[in] Slot The slot number of the SD card to send the command to.
670 @param[out] MediaPresent The pointer to the media present boolean value.
671
672 @retval EFI_SUCCESS There is no media change happened.
673 @retval EFI_MEDIA_CHANGED There is media change happened.
674 @retval Others The detection fails.
675
676 **/
677 EFI_STATUS
678 SdMmcHcCardDetect (
679 IN EFI_PCI_IO_PROTOCOL *PciIo,
680 IN UINT8 Slot,
681 OUT BOOLEAN *MediaPresent
682 )
683 {
684 EFI_STATUS Status;
685 UINT16 Data;
686 UINT32 PresentState;
687
688 //
689 // Check Present State Register to see if there is a card presented.
690 //
691 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);
692 if (EFI_ERROR (Status)) {
693 return Status;
694 }
695
696 if ((PresentState & BIT16) != 0) {
697 *MediaPresent = TRUE;
698 } else {
699 *MediaPresent = FALSE;
700 }
701
702 //
703 // Check Normal Interrupt Status Register
704 //
705 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, TRUE, sizeof (Data), &Data);
706 if (EFI_ERROR (Status)) {
707 return Status;
708 }
709
710 if ((Data & (BIT6 | BIT7)) != 0) {
711 //
712 // Clear BIT6 and BIT7 by writing 1 to these two bits if set.
713 //
714 Data &= BIT6 | BIT7;
715 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data), &Data);
716 if (EFI_ERROR (Status)) {
717 return Status;
718 }
719
720 return EFI_MEDIA_CHANGED;
721 }
722
723 return EFI_SUCCESS;
724 }
725
726 /**
727 Stop SD/MMC card clock.
728
729 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
730
731 @param[in] PciIo The PCI IO protocol instance.
732 @param[in] Slot The slot number of the SD card to send the command to.
733
734 @retval EFI_SUCCESS Succeed to stop SD/MMC clock.
735 @retval Others Fail to stop SD/MMC clock.
736
737 **/
738 EFI_STATUS
739 SdMmcHcStopClock (
740 IN EFI_PCI_IO_PROTOCOL *PciIo,
741 IN UINT8 Slot
742 )
743 {
744 EFI_STATUS Status;
745 UINT32 PresentState;
746 UINT16 ClockCtrl;
747
748 //
749 // Ensure no SD transactions are occurring on the SD Bus by
750 // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)
751 // in the Present State register to be 0.
752 //
753 Status = SdMmcHcWaitMmioSet (
754 PciIo,
755 Slot,
756 SD_MMC_HC_PRESENT_STATE,
757 sizeof (PresentState),
758 BIT0 | BIT1,
759 0,
760 SD_MMC_HC_GENERIC_TIMEOUT
761 );
762 if (EFI_ERROR (Status)) {
763 return Status;
764 }
765
766 //
767 // Set SD Clock Enable in the Clock Control register to 0
768 //
769 ClockCtrl = (UINT16) ~BIT2;
770 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
771
772 return Status;
773 }
774
775 /**
776 Start the SD clock.
777
778 @param[in] PciIo The PCI IO protocol instance.
779 @param[in] Slot The slot number.
780
781 @retval EFI_SUCCESS Succeeded to start the SD clock.
782 @retval Others Failed to start the SD clock.
783 **/
784 EFI_STATUS
785 SdMmcHcStartSdClock (
786 IN EFI_PCI_IO_PROTOCOL *PciIo,
787 IN UINT8 Slot
788 )
789 {
790 UINT16 ClockCtrl;
791
792 //
793 // Set SD Clock Enable in the Clock Control register to 1
794 //
795 ClockCtrl = BIT2;
796 return SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
797 }
798
799 /**
800 SD/MMC card clock supply.
801
802 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
803
804 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
805 @param[in] Slot The slot number of the SD card to send the command to.
806 @param[in] BusTiming BusTiming at which the frequency change is done.
807 @param[in] FirstTimeSetup Flag to indicate whether the clock is being setup for the first time.
808 @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
809
810 @retval EFI_SUCCESS The clock is supplied successfully.
811 @retval Others The clock isn't supplied successfully.
812
813 **/
814 EFI_STATUS
815 SdMmcHcClockSupply (
816 IN SD_MMC_HC_PRIVATE_DATA *Private,
817 IN UINT8 Slot,
818 IN SD_MMC_BUS_MODE BusTiming,
819 IN BOOLEAN FirstTimeSetup,
820 IN UINT64 ClockFreq
821 )
822 {
823 EFI_STATUS Status;
824 UINT32 SettingFreq;
825 UINT32 Divisor;
826 UINT32 Remainder;
827 UINT16 ClockCtrl;
828 UINT32 BaseClkFreq;
829 UINT16 ControllerVer;
830 EFI_PCI_IO_PROTOCOL *PciIo;
831
832 PciIo = Private->PciIo;
833 BaseClkFreq = Private->BaseClkFreq[Slot];
834 ControllerVer = Private->ControllerVersion[Slot];
835
836 if ((BaseClkFreq == 0) || (ClockFreq == 0)) {
837 return EFI_INVALID_PARAMETER;
838 }
839
840 if (ClockFreq > (BaseClkFreq * 1000)) {
841 ClockFreq = BaseClkFreq * 1000;
842 }
843
844 //
845 // Calculate the divisor of base frequency.
846 //
847 Divisor = 0;
848 SettingFreq = BaseClkFreq * 1000;
849 while (ClockFreq < SettingFreq) {
850 Divisor++;
851
852 SettingFreq = (BaseClkFreq * 1000) / (2 * Divisor);
853 Remainder = (BaseClkFreq * 1000) % (2 * Divisor);
854 if ((ClockFreq == SettingFreq) && (Remainder == 0)) {
855 break;
856 }
857
858 if ((ClockFreq == SettingFreq) && (Remainder != 0)) {
859 SettingFreq++;
860 }
861 }
862
863 DEBUG ((DEBUG_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq, Divisor, ClockFreq));
864
865 //
866 // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.
867 //
868 if ((ControllerVer >= SD_MMC_HC_CTRL_VER_300) &&
869 (ControllerVer <= SD_MMC_HC_CTRL_VER_420))
870 {
871 ASSERT (Divisor <= 0x3FF);
872 ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);
873 } else if ((ControllerVer == SD_MMC_HC_CTRL_VER_100) ||
874 (ControllerVer == SD_MMC_HC_CTRL_VER_200))
875 {
876 //
877 // Only the most significant bit can be used as divisor.
878 //
879 if (((Divisor - 1) & Divisor) != 0) {
880 Divisor = 1 << (HighBitSet32 (Divisor) + 1);
881 }
882
883 ASSERT (Divisor <= 0x80);
884 ClockCtrl = (Divisor & 0xFF) << 8;
885 } else {
886 DEBUG ((DEBUG_ERROR, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer));
887 return EFI_UNSUPPORTED;
888 }
889
890 //
891 // Stop bus clock at first
892 //
893 Status = SdMmcHcStopClock (PciIo, Slot);
894 if (EFI_ERROR (Status)) {
895 return Status;
896 }
897
898 //
899 // Supply clock frequency with specified divisor
900 //
901 ClockCtrl |= BIT0;
902 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);
903 if (EFI_ERROR (Status)) {
904 DEBUG ((DEBUG_ERROR, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));
905 return Status;
906 }
907
908 //
909 // Wait Internal Clock Stable in the Clock Control register to be 1
910 //
911 Status = SdMmcHcWaitMmioSet (
912 PciIo,
913 Slot,
914 SD_MMC_HC_CLOCK_CTRL,
915 sizeof (ClockCtrl),
916 BIT1,
917 BIT1,
918 SD_MMC_HC_GENERIC_TIMEOUT
919 );
920 if (EFI_ERROR (Status)) {
921 return Status;
922 }
923
924 Status = SdMmcHcStartSdClock (PciIo, Slot);
925 if (EFI_ERROR (Status)) {
926 return Status;
927 }
928
929 //
930 // We don't notify the platform on first time setup to avoid changing
931 // legacy behavior. During first time setup we also don't know what type
932 // of the card slot it is and which enum value of BusTiming applies.
933 //
934 if (!FirstTimeSetup && (mOverride != NULL) && (mOverride->NotifyPhase != NULL)) {
935 Status = mOverride->NotifyPhase (
936 Private->ControllerHandle,
937 Slot,
938 EdkiiSdMmcSwitchClockFreqPost,
939 &BusTiming
940 );
941 if (EFI_ERROR (Status)) {
942 DEBUG ((
943 DEBUG_ERROR,
944 "%a: SD/MMC switch clock freq post notifier callback failed - %r\n",
945 __FUNCTION__,
946 Status
947 ));
948 return Status;
949 }
950 }
951
952 Private->Slot[Slot].CurrentFreq = ClockFreq;
953
954 return Status;
955 }
956
957 /**
958 SD/MMC bus power control.
959
960 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
961
962 @param[in] PciIo The PCI IO protocol instance.
963 @param[in] Slot The slot number of the SD card to send the command to.
964 @param[in] PowerCtrl The value setting to the power control register.
965
966 @retval TRUE There is a SD/MMC card attached.
967 @retval FALSE There is no a SD/MMC card attached.
968
969 **/
970 EFI_STATUS
971 SdMmcHcPowerControl (
972 IN EFI_PCI_IO_PROTOCOL *PciIo,
973 IN UINT8 Slot,
974 IN UINT8 PowerCtrl
975 )
976 {
977 EFI_STATUS Status;
978
979 //
980 // Clr SD Bus Power
981 //
982 PowerCtrl &= (UINT8) ~BIT0;
983 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
984 if (EFI_ERROR (Status)) {
985 return Status;
986 }
987
988 //
989 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
990 //
991 PowerCtrl |= BIT0;
992 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
993
994 return Status;
995 }
996
997 /**
998 Set the SD/MMC bus width.
999
1000 Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
1001
1002 @param[in] PciIo The PCI IO protocol instance.
1003 @param[in] Slot The slot number of the SD card to send the command to.
1004 @param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.
1005
1006 @retval EFI_SUCCESS The bus width is set successfully.
1007 @retval Others The bus width isn't set successfully.
1008
1009 **/
1010 EFI_STATUS
1011 SdMmcHcSetBusWidth (
1012 IN EFI_PCI_IO_PROTOCOL *PciIo,
1013 IN UINT8 Slot,
1014 IN UINT16 BusWidth
1015 )
1016 {
1017 EFI_STATUS Status;
1018 UINT8 HostCtrl1;
1019
1020 if (BusWidth == 1) {
1021 HostCtrl1 = (UINT8) ~(BIT5 | BIT1);
1022 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1023 } else if (BusWidth == 4) {
1024 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
1025 if (EFI_ERROR (Status)) {
1026 return Status;
1027 }
1028
1029 HostCtrl1 |= BIT1;
1030 HostCtrl1 &= (UINT8) ~BIT5;
1031 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
1032 } else if (BusWidth == 8) {
1033 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
1034 if (EFI_ERROR (Status)) {
1035 return Status;
1036 }
1037
1038 HostCtrl1 &= (UINT8) ~BIT1;
1039 HostCtrl1 |= BIT5;
1040 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
1041 } else {
1042 ASSERT (FALSE);
1043 return EFI_INVALID_PARAMETER;
1044 }
1045
1046 return Status;
1047 }
1048
1049 /**
1050 Configure V4 controller enhancements at initialization.
1051
1052 @param[in] PciIo The PCI IO protocol instance.
1053 @param[in] Slot The slot number of the SD card to send the command to.
1054 @param[in] Capability The capability of the slot.
1055 @param[in] ControllerVer The version of host controller.
1056
1057 @retval EFI_SUCCESS The clock is supplied successfully.
1058
1059 **/
1060 EFI_STATUS
1061 SdMmcHcInitV4Enhancements (
1062 IN EFI_PCI_IO_PROTOCOL *PciIo,
1063 IN UINT8 Slot,
1064 IN SD_MMC_HC_SLOT_CAP Capability,
1065 IN UINT16 ControllerVer
1066 )
1067 {
1068 EFI_STATUS Status;
1069 UINT16 HostCtrl2;
1070
1071 //
1072 // Check if controller version V4 or higher
1073 //
1074 if (ControllerVer >= SD_MMC_HC_CTRL_VER_400) {
1075 HostCtrl2 = SD_MMC_HC_V4_EN;
1076 //
1077 // Check if controller version V4.0
1078 //
1079 if (ControllerVer == SD_MMC_HC_CTRL_VER_400) {
1080 //
1081 // Check if 64bit support is available
1082 //
1083 if (Capability.SysBus64V3 != 0) {
1084 HostCtrl2 |= SD_MMC_HC_64_ADDR_EN;
1085 DEBUG ((DEBUG_INFO, "Enabled V4 64 bit system bus support\n"));
1086 }
1087 }
1088 //
1089 // Check if controller version V4.10 or higher
1090 //
1091 else if (ControllerVer >= SD_MMC_HC_CTRL_VER_410) {
1092 //
1093 // Check if 64bit support is available
1094 //
1095 if (Capability.SysBus64V4 != 0) {
1096 HostCtrl2 |= SD_MMC_HC_64_ADDR_EN;
1097 DEBUG ((DEBUG_INFO, "Enabled V4 64 bit system bus support\n"));
1098 }
1099
1100 HostCtrl2 |= SD_MMC_HC_26_DATA_LEN_ADMA_EN;
1101 DEBUG ((DEBUG_INFO, "Enabled V4 26 bit data length ADMA support\n"));
1102 }
1103
1104 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1105 if (EFI_ERROR (Status)) {
1106 return Status;
1107 }
1108 }
1109
1110 return EFI_SUCCESS;
1111 }
1112
1113 /**
1114 Supply SD/MMC card with maximum voltage at initialization.
1115
1116 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
1117
1118 @param[in] PciIo The PCI IO protocol instance.
1119 @param[in] Slot The slot number of the SD card to send the command to.
1120 @param[in] Capability The capability of the slot.
1121
1122 @retval EFI_SUCCESS The voltage is supplied successfully.
1123 @retval Others The voltage isn't supplied successfully.
1124
1125 **/
1126 EFI_STATUS
1127 SdMmcHcInitPowerVoltage (
1128 IN EFI_PCI_IO_PROTOCOL *PciIo,
1129 IN UINT8 Slot,
1130 IN SD_MMC_HC_SLOT_CAP Capability
1131 )
1132 {
1133 EFI_STATUS Status;
1134 UINT8 MaxVoltage;
1135 UINT8 HostCtrl2;
1136
1137 //
1138 // Calculate supported maximum voltage according to SD Bus Voltage Select
1139 //
1140 if (Capability.Voltage33 != 0) {
1141 //
1142 // Support 3.3V
1143 //
1144 MaxVoltage = 0x0E;
1145 } else if (Capability.Voltage30 != 0) {
1146 //
1147 // Support 3.0V
1148 //
1149 MaxVoltage = 0x0C;
1150 } else if (Capability.Voltage18 != 0) {
1151 //
1152 // Support 1.8V
1153 //
1154 MaxVoltage = 0x0A;
1155 HostCtrl2 = BIT3;
1156 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1157 gBS->Stall (5000);
1158 if (EFI_ERROR (Status)) {
1159 return Status;
1160 }
1161 } else {
1162 ASSERT (FALSE);
1163 return EFI_DEVICE_ERROR;
1164 }
1165
1166 //
1167 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
1168 //
1169 Status = SdMmcHcPowerControl (PciIo, Slot, MaxVoltage);
1170
1171 return Status;
1172 }
1173
1174 /**
1175 Initialize the Timeout Control register with most conservative value at initialization.
1176
1177 Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
1178
1179 @param[in] PciIo The PCI IO protocol instance.
1180 @param[in] Slot The slot number of the SD card to send the command to.
1181
1182 @retval EFI_SUCCESS The timeout control register is configured successfully.
1183 @retval Others The timeout control register isn't configured successfully.
1184
1185 **/
1186 EFI_STATUS
1187 SdMmcHcInitTimeoutCtrl (
1188 IN EFI_PCI_IO_PROTOCOL *PciIo,
1189 IN UINT8 Slot
1190 )
1191 {
1192 EFI_STATUS Status;
1193 UINT8 Timeout;
1194
1195 Timeout = 0x0E;
1196 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_TIMEOUT_CTRL, FALSE, sizeof (Timeout), &Timeout);
1197
1198 return Status;
1199 }
1200
1201 /**
1202 Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value
1203 at initialization.
1204
1205 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1206 @param[in] Slot The slot number of the SD card to send the command to.
1207
1208 @retval EFI_SUCCESS The host controller is initialized successfully.
1209 @retval Others The host controller isn't initialized successfully.
1210
1211 **/
1212 EFI_STATUS
1213 SdMmcHcInitHost (
1214 IN SD_MMC_HC_PRIVATE_DATA *Private,
1215 IN UINT8 Slot
1216 )
1217 {
1218 EFI_STATUS Status;
1219 EFI_PCI_IO_PROTOCOL *PciIo;
1220 SD_MMC_HC_SLOT_CAP Capability;
1221
1222 //
1223 // Notify the SD/MMC override protocol that we are about to initialize
1224 // the SD/MMC host controller.
1225 //
1226 if ((mOverride != NULL) && (mOverride->NotifyPhase != NULL)) {
1227 Status = mOverride->NotifyPhase (
1228 Private->ControllerHandle,
1229 Slot,
1230 EdkiiSdMmcInitHostPre,
1231 NULL
1232 );
1233 if (EFI_ERROR (Status)) {
1234 DEBUG ((
1235 DEBUG_WARN,
1236 "%a: SD/MMC pre init notifier callback failed - %r\n",
1237 __FUNCTION__,
1238 Status
1239 ));
1240 return Status;
1241 }
1242 }
1243
1244 PciIo = Private->PciIo;
1245 Capability = Private->Capability[Slot];
1246
1247 Status = SdMmcHcInitV4Enhancements (PciIo, Slot, Capability, Private->ControllerVersion[Slot]);
1248 if (EFI_ERROR (Status)) {
1249 return Status;
1250 }
1251
1252 //
1253 // Perform first time clock setup with 400 KHz frequency.
1254 // We send the 0 as the BusTiming value because at this time
1255 // we still do not know the slot type and which enum value will apply.
1256 // Since it is a first time setup SdMmcHcClockSupply won't notify
1257 // the platofrm driver anyway so it doesn't matter.
1258 //
1259 Status = SdMmcHcClockSupply (Private, Slot, 0, TRUE, 400);
1260 if (EFI_ERROR (Status)) {
1261 return Status;
1262 }
1263
1264 Status = SdMmcHcInitPowerVoltage (PciIo, Slot, Capability);
1265 if (EFI_ERROR (Status)) {
1266 return Status;
1267 }
1268
1269 Status = SdMmcHcInitTimeoutCtrl (PciIo, Slot);
1270 if (EFI_ERROR (Status)) {
1271 return Status;
1272 }
1273
1274 //
1275 // Notify the SD/MMC override protocol that we are have just initialized
1276 // the SD/MMC host controller.
1277 //
1278 if ((mOverride != NULL) && (mOverride->NotifyPhase != NULL)) {
1279 Status = mOverride->NotifyPhase (
1280 Private->ControllerHandle,
1281 Slot,
1282 EdkiiSdMmcInitHostPost,
1283 NULL
1284 );
1285 if (EFI_ERROR (Status)) {
1286 DEBUG ((
1287 DEBUG_WARN,
1288 "%a: SD/MMC post init notifier callback failed - %r\n",
1289 __FUNCTION__,
1290 Status
1291 ));
1292 }
1293 }
1294
1295 return Status;
1296 }
1297
1298 /**
1299 Set SD Host Controler control 2 registry according to selected speed.
1300
1301 @param[in] ControllerHandle The handle of the controller.
1302 @param[in] PciIo The PCI IO protocol instance.
1303 @param[in] Slot The slot number of the SD card to send the command to.
1304 @param[in] Timing The timing to select.
1305
1306 @retval EFI_SUCCESS The timing is set successfully.
1307 @retval Others The timing isn't set successfully.
1308 **/
1309 EFI_STATUS
1310 SdMmcHcUhsSignaling (
1311 IN EFI_HANDLE ControllerHandle,
1312 IN EFI_PCI_IO_PROTOCOL *PciIo,
1313 IN UINT8 Slot,
1314 IN SD_MMC_BUS_MODE Timing
1315 )
1316 {
1317 EFI_STATUS Status;
1318 UINT8 HostCtrl2;
1319
1320 HostCtrl2 = (UINT8) ~SD_MMC_HC_CTRL_UHS_MASK;
1321 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1322 if (EFI_ERROR (Status)) {
1323 return Status;
1324 }
1325
1326 switch (Timing) {
1327 case SdMmcUhsSdr12:
1328 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR12;
1329 break;
1330 case SdMmcUhsSdr25:
1331 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR25;
1332 break;
1333 case SdMmcUhsSdr50:
1334 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR50;
1335 break;
1336 case SdMmcUhsSdr104:
1337 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR104;
1338 break;
1339 case SdMmcUhsDdr50:
1340 HostCtrl2 = SD_MMC_HC_CTRL_UHS_DDR50;
1341 break;
1342 case SdMmcMmcLegacy:
1343 HostCtrl2 = SD_MMC_HC_CTRL_MMC_LEGACY;
1344 break;
1345 case SdMmcMmcHsSdr:
1346 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_SDR;
1347 break;
1348 case SdMmcMmcHsDdr:
1349 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_DDR;
1350 break;
1351 case SdMmcMmcHs200:
1352 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS200;
1353 break;
1354 case SdMmcMmcHs400:
1355 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS400;
1356 break;
1357 default:
1358 HostCtrl2 = 0;
1359 break;
1360 }
1361
1362 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1363 if (EFI_ERROR (Status)) {
1364 return Status;
1365 }
1366
1367 if ((mOverride != NULL) && (mOverride->NotifyPhase != NULL)) {
1368 Status = mOverride->NotifyPhase (
1369 ControllerHandle,
1370 Slot,
1371 EdkiiSdMmcUhsSignaling,
1372 &Timing
1373 );
1374 if (EFI_ERROR (Status)) {
1375 DEBUG ((
1376 DEBUG_ERROR,
1377 "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
1378 __FUNCTION__,
1379 Status
1380 ));
1381 return Status;
1382 }
1383 }
1384
1385 return EFI_SUCCESS;
1386 }
1387
1388 /**
1389 Set driver strength in host controller.
1390
1391 @param[in] PciIo The PCI IO protocol instance.
1392 @param[in] SlotIndex The slot index of the card.
1393 @param[in] DriverStrength DriverStrength to set in the controller.
1394
1395 @retval EFI_SUCCESS Driver strength programmed successfully.
1396 @retval Others Failed to set driver strength.
1397 **/
1398 EFI_STATUS
1399 SdMmcSetDriverStrength (
1400 IN EFI_PCI_IO_PROTOCOL *PciIo,
1401 IN UINT8 SlotIndex,
1402 IN SD_DRIVER_STRENGTH_TYPE DriverStrength
1403 )
1404 {
1405 EFI_STATUS Status;
1406 UINT16 HostCtrl2;
1407
1408 if (DriverStrength == SdDriverStrengthIgnore) {
1409 return EFI_SUCCESS;
1410 }
1411
1412 HostCtrl2 = (UINT16) ~SD_MMC_HC_CTRL_DRIVER_STRENGTH_MASK;
1413 Status = SdMmcHcAndMmio (PciIo, SlotIndex, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1414 if (EFI_ERROR (Status)) {
1415 return Status;
1416 }
1417
1418 HostCtrl2 = (DriverStrength << 4) & SD_MMC_HC_CTRL_DRIVER_STRENGTH_MASK;
1419 return SdMmcHcOrMmio (PciIo, SlotIndex, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1420 }
1421
1422 /**
1423 Turn on/off LED.
1424
1425 @param[in] PciIo The PCI IO protocol instance.
1426 @param[in] Slot The slot number of the SD card to send the command to.
1427 @param[in] On The boolean to turn on/off LED.
1428
1429 @retval EFI_SUCCESS The LED is turned on/off successfully.
1430 @retval Others The LED isn't turned on/off successfully.
1431
1432 **/
1433 EFI_STATUS
1434 SdMmcHcLedOnOff (
1435 IN EFI_PCI_IO_PROTOCOL *PciIo,
1436 IN UINT8 Slot,
1437 IN BOOLEAN On
1438 )
1439 {
1440 EFI_STATUS Status;
1441 UINT8 HostCtrl1;
1442
1443 if (On) {
1444 HostCtrl1 = BIT0;
1445 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1446 } else {
1447 HostCtrl1 = (UINT8) ~BIT0;
1448 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1449 }
1450
1451 return Status;
1452 }
1453
1454 /**
1455 Build ADMA descriptor table for transfer.
1456
1457 Refer to SD Host Controller Simplified spec 4.2 Section 1.13 for details.
1458
1459 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1460 @param[in] ControllerVer The version of host controller.
1461
1462 @retval EFI_SUCCESS The ADMA descriptor table is created successfully.
1463 @retval Others The ADMA descriptor table isn't created successfully.
1464
1465 **/
1466 EFI_STATUS
1467 BuildAdmaDescTable (
1468 IN SD_MMC_HC_TRB *Trb,
1469 IN UINT16 ControllerVer
1470 )
1471 {
1472 EFI_PHYSICAL_ADDRESS Data;
1473 UINT64 DataLen;
1474 UINT64 Entries;
1475 UINT32 Index;
1476 UINT64 Remaining;
1477 UINT64 Address;
1478 UINTN TableSize;
1479 EFI_PCI_IO_PROTOCOL *PciIo;
1480 EFI_STATUS Status;
1481 UINTN Bytes;
1482 UINT32 AdmaMaxDataPerLine;
1483 UINT32 DescSize;
1484 VOID *AdmaDesc;
1485
1486 AdmaMaxDataPerLine = ADMA_MAX_DATA_PER_LINE_16B;
1487 DescSize = sizeof (SD_MMC_HC_ADMA_32_DESC_LINE);
1488 AdmaDesc = NULL;
1489
1490 Data = Trb->DataPhy;
1491 DataLen = Trb->DataLen;
1492 PciIo = Trb->Private->PciIo;
1493
1494 //
1495 // Check for valid ranges in 32bit ADMA Descriptor Table
1496 //
1497 if ((Trb->Mode == SdMmcAdma32bMode) &&
1498 ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul)))
1499 {
1500 return EFI_INVALID_PARAMETER;
1501 }
1502
1503 //
1504 // Check address field alignment
1505 //
1506 if (Trb->Mode != SdMmcAdma32bMode) {
1507 //
1508 // Address field shall be set on 64-bit boundary (Lower 3-bit is always set to 0)
1509 //
1510 if ((Data & (BIT0 | BIT1 | BIT2)) != 0) {
1511 DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 8 bytes boundary!\n", Data));
1512 }
1513 } else {
1514 //
1515 // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)
1516 //
1517 if ((Data & (BIT0 | BIT1)) != 0) {
1518 DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data));
1519 }
1520 }
1521
1522 //
1523 // Configure 64b ADMA.
1524 //
1525 if (Trb->Mode == SdMmcAdma64bV3Mode) {
1526 DescSize = sizeof (SD_MMC_HC_ADMA_64_V3_DESC_LINE);
1527 } else if (Trb->Mode == SdMmcAdma64bV4Mode) {
1528 DescSize = sizeof (SD_MMC_HC_ADMA_64_V4_DESC_LINE);
1529 }
1530
1531 //
1532 // Configure 26b data length.
1533 //
1534 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1535 AdmaMaxDataPerLine = ADMA_MAX_DATA_PER_LINE_26B;
1536 }
1537
1538 Entries = DivU64x32 ((DataLen + AdmaMaxDataPerLine - 1), AdmaMaxDataPerLine);
1539 TableSize = (UINTN)MultU64x32 (Entries, DescSize);
1540 Trb->AdmaPages = (UINT32)EFI_SIZE_TO_PAGES (TableSize);
1541 Status = PciIo->AllocateBuffer (
1542 PciIo,
1543 AllocateAnyPages,
1544 EfiBootServicesData,
1545 EFI_SIZE_TO_PAGES (TableSize),
1546 (VOID **)&AdmaDesc,
1547 0
1548 );
1549 if (EFI_ERROR (Status)) {
1550 return EFI_OUT_OF_RESOURCES;
1551 }
1552
1553 ZeroMem (AdmaDesc, TableSize);
1554 Bytes = TableSize;
1555 Status = PciIo->Map (
1556 PciIo,
1557 EfiPciIoOperationBusMasterCommonBuffer,
1558 AdmaDesc,
1559 &Bytes,
1560 &Trb->AdmaDescPhy,
1561 &Trb->AdmaMap
1562 );
1563
1564 if (EFI_ERROR (Status) || (Bytes != TableSize)) {
1565 //
1566 // Map error or unable to map the whole RFis buffer into a contiguous region.
1567 //
1568 PciIo->FreeBuffer (
1569 PciIo,
1570 EFI_SIZE_TO_PAGES (TableSize),
1571 AdmaDesc
1572 );
1573 return EFI_OUT_OF_RESOURCES;
1574 }
1575
1576 if ((Trb->Mode == SdMmcAdma32bMode) &&
1577 ((UINT64)(UINTN)Trb->AdmaDescPhy > 0x100000000ul))
1578 {
1579 //
1580 // The ADMA doesn't support 64bit addressing.
1581 //
1582 PciIo->Unmap (
1583 PciIo,
1584 Trb->AdmaMap
1585 );
1586 Trb->AdmaMap = NULL;
1587
1588 PciIo->FreeBuffer (
1589 PciIo,
1590 EFI_SIZE_TO_PAGES (TableSize),
1591 AdmaDesc
1592 );
1593 return EFI_DEVICE_ERROR;
1594 }
1595
1596 Remaining = DataLen;
1597 Address = Data;
1598 if (Trb->Mode == SdMmcAdma32bMode) {
1599 Trb->Adma32Desc = AdmaDesc;
1600 } else if (Trb->Mode == SdMmcAdma64bV3Mode) {
1601 Trb->Adma64V3Desc = AdmaDesc;
1602 } else {
1603 Trb->Adma64V4Desc = AdmaDesc;
1604 }
1605
1606 for (Index = 0; Index < Entries; Index++) {
1607 if (Trb->Mode == SdMmcAdma32bMode) {
1608 if (Remaining <= AdmaMaxDataPerLine) {
1609 Trb->Adma32Desc[Index].Valid = 1;
1610 Trb->Adma32Desc[Index].Act = 2;
1611 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1612 Trb->Adma32Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);
1613 }
1614
1615 Trb->Adma32Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);
1616 Trb->Adma32Desc[Index].Address = (UINT32)Address;
1617 break;
1618 } else {
1619 Trb->Adma32Desc[Index].Valid = 1;
1620 Trb->Adma32Desc[Index].Act = 2;
1621 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1622 Trb->Adma32Desc[Index].UpperLength = 0;
1623 }
1624
1625 Trb->Adma32Desc[Index].LowerLength = 0;
1626 Trb->Adma32Desc[Index].Address = (UINT32)Address;
1627 }
1628 } else if (Trb->Mode == SdMmcAdma64bV3Mode) {
1629 if (Remaining <= AdmaMaxDataPerLine) {
1630 Trb->Adma64V3Desc[Index].Valid = 1;
1631 Trb->Adma64V3Desc[Index].Act = 2;
1632 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1633 Trb->Adma64V3Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);
1634 }
1635
1636 Trb->Adma64V3Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);
1637 Trb->Adma64V3Desc[Index].LowerAddress = (UINT32)Address;
1638 Trb->Adma64V3Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);
1639 break;
1640 } else {
1641 Trb->Adma64V3Desc[Index].Valid = 1;
1642 Trb->Adma64V3Desc[Index].Act = 2;
1643 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1644 Trb->Adma64V3Desc[Index].UpperLength = 0;
1645 }
1646
1647 Trb->Adma64V3Desc[Index].LowerLength = 0;
1648 Trb->Adma64V3Desc[Index].LowerAddress = (UINT32)Address;
1649 Trb->Adma64V3Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);
1650 }
1651 } else {
1652 if (Remaining <= AdmaMaxDataPerLine) {
1653 Trb->Adma64V4Desc[Index].Valid = 1;
1654 Trb->Adma64V4Desc[Index].Act = 2;
1655 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1656 Trb->Adma64V4Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);
1657 }
1658
1659 Trb->Adma64V4Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);
1660 Trb->Adma64V4Desc[Index].LowerAddress = (UINT32)Address;
1661 Trb->Adma64V4Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);
1662 break;
1663 } else {
1664 Trb->Adma64V4Desc[Index].Valid = 1;
1665 Trb->Adma64V4Desc[Index].Act = 2;
1666 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1667 Trb->Adma64V4Desc[Index].UpperLength = 0;
1668 }
1669
1670 Trb->Adma64V4Desc[Index].LowerLength = 0;
1671 Trb->Adma64V4Desc[Index].LowerAddress = (UINT32)Address;
1672 Trb->Adma64V4Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);
1673 }
1674 }
1675
1676 Remaining -= AdmaMaxDataPerLine;
1677 Address += AdmaMaxDataPerLine;
1678 }
1679
1680 //
1681 // Set the last descriptor line as end of descriptor table
1682 //
1683 if (Trb->Mode == SdMmcAdma32bMode) {
1684 Trb->Adma32Desc[Index].End = 1;
1685 } else if (Trb->Mode == SdMmcAdma64bV3Mode) {
1686 Trb->Adma64V3Desc[Index].End = 1;
1687 } else {
1688 Trb->Adma64V4Desc[Index].End = 1;
1689 }
1690
1691 return EFI_SUCCESS;
1692 }
1693
1694 /**
1695 Prints the contents of the command packet to the debug port.
1696
1697 @param[in] DebugLevel Debug level at which the packet should be printed.
1698 @param[in] Packet Pointer to packet to print.
1699 **/
1700 VOID
1701 SdMmcPrintPacket (
1702 IN UINT32 DebugLevel,
1703 IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet
1704 )
1705 {
1706 if (Packet == NULL) {
1707 return;
1708 }
1709
1710 DEBUG ((DebugLevel, "Printing EFI_SD_MMC_PASS_THRU_COMMAND_PACKET\n"));
1711 if (Packet->SdMmcCmdBlk != NULL) {
1712 DEBUG ((DebugLevel, "Command index: %d, argument: %X\n", Packet->SdMmcCmdBlk->CommandIndex, Packet->SdMmcCmdBlk->CommandArgument));
1713 DEBUG ((DebugLevel, "Command type: %d, response type: %d\n", Packet->SdMmcCmdBlk->CommandType, Packet->SdMmcCmdBlk->ResponseType));
1714 }
1715
1716 if (Packet->SdMmcStatusBlk != NULL) {
1717 DEBUG ((
1718 DebugLevel,
1719 "Response 0: %X, 1: %X, 2: %X, 3: %X\n",
1720 Packet->SdMmcStatusBlk->Resp0,
1721 Packet->SdMmcStatusBlk->Resp1,
1722 Packet->SdMmcStatusBlk->Resp2,
1723 Packet->SdMmcStatusBlk->Resp3
1724 ));
1725 }
1726
1727 DEBUG ((DebugLevel, "Timeout: %ld\n", Packet->Timeout));
1728 DEBUG ((DebugLevel, "InDataBuffer: %p\n", Packet->InDataBuffer));
1729 DEBUG ((DebugLevel, "OutDataBuffer: %p\n", Packet->OutDataBuffer));
1730 DEBUG ((DebugLevel, "InTransferLength: %d\n", Packet->InTransferLength));
1731 DEBUG ((DebugLevel, "OutTransferLength: %d\n", Packet->OutTransferLength));
1732 DEBUG ((DebugLevel, "TransactionStatus: %r\n", Packet->TransactionStatus));
1733 }
1734
1735 /**
1736 Prints the contents of the TRB to the debug port.
1737
1738 @param[in] DebugLevel Debug level at which the TRB should be printed.
1739 @param[in] Trb Pointer to the TRB structure.
1740 **/
1741 VOID
1742 SdMmcPrintTrb (
1743 IN UINT32 DebugLevel,
1744 IN SD_MMC_HC_TRB *Trb
1745 )
1746 {
1747 if (Trb == NULL) {
1748 return;
1749 }
1750
1751 DEBUG ((DebugLevel, "Printing SD_MMC_HC_TRB\n"));
1752 DEBUG ((DebugLevel, "Slot: %d\n", Trb->Slot));
1753 DEBUG ((DebugLevel, "BlockSize: %d\n", Trb->BlockSize));
1754 DEBUG ((DebugLevel, "Data: %p\n", Trb->Data));
1755 DEBUG ((DebugLevel, "DataLen: %d\n", Trb->DataLen));
1756 DEBUG ((DebugLevel, "Read: %d\n", Trb->Read));
1757 DEBUG ((DebugLevel, "DataPhy: %lX\n", Trb->DataPhy));
1758 DEBUG ((DebugLevel, "DataMap: %p\n", Trb->DataMap));
1759 DEBUG ((DebugLevel, "Mode: %d\n", Trb->Mode));
1760 DEBUG ((DebugLevel, "AdmaLengthMode: %d\n", Trb->AdmaLengthMode));
1761 DEBUG ((DebugLevel, "Event: %p\n", Trb->Event));
1762 DEBUG ((DebugLevel, "Started: %d\n", Trb->Started));
1763 DEBUG ((DebugLevel, "CommandComplete: %d\n", Trb->CommandComplete));
1764 DEBUG ((DebugLevel, "Timeout: %ld\n", Trb->Timeout));
1765 DEBUG ((DebugLevel, "Retries: %d\n", Trb->Retries));
1766 DEBUG ((DebugLevel, "PioModeTransferCompleted: %d\n", Trb->PioModeTransferCompleted));
1767 DEBUG ((DebugLevel, "PioBlockIndex: %d\n", Trb->PioBlockIndex));
1768 DEBUG ((DebugLevel, "Adma32Desc: %p\n", Trb->Adma32Desc));
1769 DEBUG ((DebugLevel, "Adma64V3Desc: %p\n", Trb->Adma64V3Desc));
1770 DEBUG ((DebugLevel, "Adma64V4Desc: %p\n", Trb->Adma64V4Desc));
1771 DEBUG ((DebugLevel, "AdmaMap: %p\n", Trb->AdmaMap));
1772 DEBUG ((DebugLevel, "AdmaPages: %X\n", Trb->AdmaPages));
1773
1774 SdMmcPrintPacket (DebugLevel, Trb->Packet);
1775 }
1776
1777 /**
1778 Sets up host memory to allow DMA transfer.
1779
1780 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1781 @param[in] Slot The slot number of the SD card to send the command to.
1782 @param[in] Packet A pointer to the SD command data structure.
1783
1784 @retval EFI_SUCCESS Memory has been mapped for DMA transfer.
1785 @retval Others Memory has not been mapped.
1786 **/
1787 EFI_STATUS
1788 SdMmcSetupMemoryForDmaTransfer (
1789 IN SD_MMC_HC_PRIVATE_DATA *Private,
1790 IN UINT8 Slot,
1791 IN SD_MMC_HC_TRB *Trb
1792 )
1793 {
1794 EFI_PCI_IO_PROTOCOL_OPERATION Flag;
1795 EFI_PCI_IO_PROTOCOL *PciIo;
1796 UINTN MapLength;
1797 EFI_STATUS Status;
1798
1799 if (Trb->Read) {
1800 Flag = EfiPciIoOperationBusMasterWrite;
1801 } else {
1802 Flag = EfiPciIoOperationBusMasterRead;
1803 }
1804
1805 PciIo = Private->PciIo;
1806 if ((Trb->Data != NULL) && (Trb->DataLen != 0)) {
1807 MapLength = Trb->DataLen;
1808 Status = PciIo->Map (
1809 PciIo,
1810 Flag,
1811 Trb->Data,
1812 &MapLength,
1813 &Trb->DataPhy,
1814 &Trb->DataMap
1815 );
1816 if (EFI_ERROR (Status) || (Trb->DataLen != MapLength)) {
1817 return EFI_BAD_BUFFER_SIZE;
1818 }
1819 }
1820
1821 if ((Trb->Mode == SdMmcAdma32bMode) ||
1822 (Trb->Mode == SdMmcAdma64bV3Mode) ||
1823 (Trb->Mode == SdMmcAdma64bV4Mode))
1824 {
1825 Status = BuildAdmaDescTable (Trb, Private->ControllerVersion[Slot]);
1826 if (EFI_ERROR (Status)) {
1827 return Status;
1828 }
1829 }
1830
1831 return EFI_SUCCESS;
1832 }
1833
1834 /**
1835 Create a new TRB for the SD/MMC cmd request.
1836
1837 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1838 @param[in] Slot The slot number of the SD card to send the command to.
1839 @param[in] Packet A pointer to the SD command data structure.
1840 @param[in] Event If Event is NULL, blocking I/O is performed. If Event is
1841 not NULL, then nonblocking I/O is performed, and Event
1842 will be signaled when the Packet completes.
1843
1844 @return Created Trb or NULL.
1845
1846 **/
1847 SD_MMC_HC_TRB *
1848 SdMmcCreateTrb (
1849 IN SD_MMC_HC_PRIVATE_DATA *Private,
1850 IN UINT8 Slot,
1851 IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
1852 IN EFI_EVENT Event
1853 )
1854 {
1855 SD_MMC_HC_TRB *Trb;
1856 EFI_STATUS Status;
1857 EFI_TPL OldTpl;
1858
1859 Trb = AllocateZeroPool (sizeof (SD_MMC_HC_TRB));
1860 if (Trb == NULL) {
1861 return NULL;
1862 }
1863
1864 Trb->Signature = SD_MMC_HC_TRB_SIG;
1865 Trb->Slot = Slot;
1866 Trb->BlockSize = 0x200;
1867 Trb->Packet = Packet;
1868 Trb->Event = Event;
1869 Trb->Started = FALSE;
1870 Trb->CommandComplete = FALSE;
1871 Trb->Timeout = Packet->Timeout;
1872 Trb->Retries = SD_MMC_TRB_RETRIES;
1873 Trb->PioModeTransferCompleted = FALSE;
1874 Trb->PioBlockIndex = 0;
1875 Trb->Private = Private;
1876
1877 if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {
1878 Trb->Data = Packet->InDataBuffer;
1879 Trb->DataLen = Packet->InTransferLength;
1880 Trb->Read = TRUE;
1881 } else if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {
1882 Trb->Data = Packet->OutDataBuffer;
1883 Trb->DataLen = Packet->OutTransferLength;
1884 Trb->Read = FALSE;
1885 } else if ((Packet->InTransferLength == 0) && (Packet->OutTransferLength == 0)) {
1886 Trb->Data = NULL;
1887 Trb->DataLen = 0;
1888 } else {
1889 goto Error;
1890 }
1891
1892 if ((Trb->DataLen != 0) && (Trb->DataLen < Trb->BlockSize)) {
1893 Trb->BlockSize = (UINT16)Trb->DataLen;
1894 }
1895
1896 if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
1897 (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
1898 ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
1899 (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK)))
1900 {
1901 Trb->Mode = SdMmcPioMode;
1902 } else {
1903 if (Trb->DataLen == 0) {
1904 Trb->Mode = SdMmcNoData;
1905 } else if (Private->Capability[Slot].Adma2 != 0) {
1906 Trb->Mode = SdMmcAdma32bMode;
1907 Trb->AdmaLengthMode = SdMmcAdmaLen16b;
1908 if ((Private->ControllerVersion[Slot] == SD_MMC_HC_CTRL_VER_300) &&
1909 (Private->Capability[Slot].SysBus64V3 == 1))
1910 {
1911 Trb->Mode = SdMmcAdma64bV3Mode;
1912 } else if (((Private->ControllerVersion[Slot] == SD_MMC_HC_CTRL_VER_400) &&
1913 (Private->Capability[Slot].SysBus64V3 == 1)) ||
1914 ((Private->ControllerVersion[Slot] >= SD_MMC_HC_CTRL_VER_410) &&
1915 (Private->Capability[Slot].SysBus64V4 == 1)))
1916 {
1917 Trb->Mode = SdMmcAdma64bV4Mode;
1918 }
1919
1920 if (Private->ControllerVersion[Slot] >= SD_MMC_HC_CTRL_VER_410) {
1921 Trb->AdmaLengthMode = SdMmcAdmaLen26b;
1922 }
1923
1924 Status = SdMmcSetupMemoryForDmaTransfer (Private, Slot, Trb);
1925 if (EFI_ERROR (Status)) {
1926 goto Error;
1927 }
1928 } else if (Private->Capability[Slot].Sdma != 0) {
1929 Trb->Mode = SdMmcSdmaMode;
1930 Status = SdMmcSetupMemoryForDmaTransfer (Private, Slot, Trb);
1931 if (EFI_ERROR (Status)) {
1932 goto Error;
1933 }
1934 } else {
1935 Trb->Mode = SdMmcPioMode;
1936 }
1937 }
1938
1939 if (Event != NULL) {
1940 OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
1941 InsertTailList (&Private->Queue, &Trb->TrbList);
1942 gBS->RestoreTPL (OldTpl);
1943 }
1944
1945 return Trb;
1946
1947 Error:
1948 SdMmcFreeTrb (Trb);
1949 return NULL;
1950 }
1951
1952 /**
1953 Free the resource used by the TRB.
1954
1955 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1956
1957 **/
1958 VOID
1959 SdMmcFreeTrb (
1960 IN SD_MMC_HC_TRB *Trb
1961 )
1962 {
1963 EFI_PCI_IO_PROTOCOL *PciIo;
1964
1965 PciIo = Trb->Private->PciIo;
1966
1967 if (Trb->AdmaMap != NULL) {
1968 PciIo->Unmap (
1969 PciIo,
1970 Trb->AdmaMap
1971 );
1972 }
1973
1974 if (Trb->Adma32Desc != NULL) {
1975 PciIo->FreeBuffer (
1976 PciIo,
1977 Trb->AdmaPages,
1978 Trb->Adma32Desc
1979 );
1980 }
1981
1982 if (Trb->Adma64V3Desc != NULL) {
1983 PciIo->FreeBuffer (
1984 PciIo,
1985 Trb->AdmaPages,
1986 Trb->Adma64V3Desc
1987 );
1988 }
1989
1990 if (Trb->Adma64V4Desc != NULL) {
1991 PciIo->FreeBuffer (
1992 PciIo,
1993 Trb->AdmaPages,
1994 Trb->Adma64V4Desc
1995 );
1996 }
1997
1998 if (Trb->DataMap != NULL) {
1999 PciIo->Unmap (
2000 PciIo,
2001 Trb->DataMap
2002 );
2003 }
2004
2005 FreePool (Trb);
2006 return;
2007 }
2008
2009 /**
2010 Check if the env is ready for execute specified TRB.
2011
2012 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2013 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2014
2015 @retval EFI_SUCCESS The env is ready for TRB execution.
2016 @retval EFI_NOT_READY The env is not ready for TRB execution.
2017 @retval Others Some erros happen.
2018
2019 **/
2020 EFI_STATUS
2021 SdMmcCheckTrbEnv (
2022 IN SD_MMC_HC_PRIVATE_DATA *Private,
2023 IN SD_MMC_HC_TRB *Trb
2024 )
2025 {
2026 EFI_STATUS Status;
2027 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
2028 EFI_PCI_IO_PROTOCOL *PciIo;
2029 UINT32 PresentState;
2030
2031 Packet = Trb->Packet;
2032
2033 if ((Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) ||
2034 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b) ||
2035 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b))
2036 {
2037 //
2038 // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in
2039 // the Present State register to be 0
2040 //
2041 PresentState = BIT0 | BIT1;
2042 } else {
2043 //
2044 // Wait Command Inhibit (CMD) in the Present State register
2045 // to be 0
2046 //
2047 PresentState = BIT0;
2048 }
2049
2050 PciIo = Private->PciIo;
2051 Status = SdMmcHcCheckMmioSet (
2052 PciIo,
2053 Trb->Slot,
2054 SD_MMC_HC_PRESENT_STATE,
2055 sizeof (PresentState),
2056 PresentState,
2057 0
2058 );
2059
2060 return Status;
2061 }
2062
2063 /**
2064 Wait for the env to be ready for execute specified TRB.
2065
2066 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2067 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2068
2069 @retval EFI_SUCCESS The env is ready for TRB execution.
2070 @retval EFI_TIMEOUT The env is not ready for TRB execution in time.
2071 @retval Others Some erros happen.
2072
2073 **/
2074 EFI_STATUS
2075 SdMmcWaitTrbEnv (
2076 IN SD_MMC_HC_PRIVATE_DATA *Private,
2077 IN SD_MMC_HC_TRB *Trb
2078 )
2079 {
2080 EFI_STATUS Status;
2081 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
2082 UINT64 Timeout;
2083 BOOLEAN InfiniteWait;
2084
2085 //
2086 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
2087 //
2088 Packet = Trb->Packet;
2089 Timeout = Packet->Timeout;
2090 if (Timeout == 0) {
2091 InfiniteWait = TRUE;
2092 } else {
2093 InfiniteWait = FALSE;
2094 }
2095
2096 while (InfiniteWait || (Timeout > 0)) {
2097 //
2098 // Check Trb execution result by reading Normal Interrupt Status register.
2099 //
2100 Status = SdMmcCheckTrbEnv (Private, Trb);
2101 if (Status != EFI_NOT_READY) {
2102 return Status;
2103 }
2104
2105 //
2106 // Stall for 1 microsecond.
2107 //
2108 gBS->Stall (1);
2109
2110 Timeout--;
2111 }
2112
2113 return EFI_TIMEOUT;
2114 }
2115
2116 /**
2117 Execute the specified TRB.
2118
2119 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2120 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2121
2122 @retval EFI_SUCCESS The TRB is sent to host controller successfully.
2123 @retval Others Some erros happen when sending this request to the host controller.
2124
2125 **/
2126 EFI_STATUS
2127 SdMmcExecTrb (
2128 IN SD_MMC_HC_PRIVATE_DATA *Private,
2129 IN SD_MMC_HC_TRB *Trb
2130 )
2131 {
2132 EFI_STATUS Status;
2133 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
2134 EFI_PCI_IO_PROTOCOL *PciIo;
2135 UINT16 Cmd;
2136 UINT16 IntStatus;
2137 UINT32 Argument;
2138 UINT32 BlkCount;
2139 UINT16 BlkSize;
2140 UINT16 TransMode;
2141 UINT8 HostCtrl1;
2142 UINT64 SdmaAddr;
2143 UINT64 AdmaAddr;
2144 BOOLEAN AddressingMode64;
2145
2146 AddressingMode64 = FALSE;
2147
2148 Packet = Trb->Packet;
2149 PciIo = Trb->Private->PciIo;
2150 //
2151 // Clear all bits in Error Interrupt Status Register
2152 //
2153 IntStatus = 0xFFFF;
2154 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ERR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
2155 if (EFI_ERROR (Status)) {
2156 return Status;
2157 }
2158
2159 //
2160 // Clear all bits in Normal Interrupt Status Register excepts for Card Removal & Card Insertion bits.
2161 //
2162 IntStatus = 0xFF3F;
2163 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
2164 if (EFI_ERROR (Status)) {
2165 return Status;
2166 }
2167
2168 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {
2169 Status = SdMmcHcCheckMmioSet (
2170 PciIo,
2171 Trb->Slot,
2172 SD_MMC_HC_HOST_CTRL2,
2173 sizeof (UINT16),
2174 SD_MMC_HC_64_ADDR_EN,
2175 SD_MMC_HC_64_ADDR_EN
2176 );
2177 if (!EFI_ERROR (Status)) {
2178 AddressingMode64 = TRUE;
2179 }
2180 }
2181
2182 //
2183 // Set Host Control 1 register DMA Select field
2184 //
2185 if ((Trb->Mode == SdMmcAdma32bMode) ||
2186 (Trb->Mode == SdMmcAdma64bV4Mode))
2187 {
2188 HostCtrl1 = BIT4;
2189 Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
2190 if (EFI_ERROR (Status)) {
2191 return Status;
2192 }
2193 } else if (Trb->Mode == SdMmcAdma64bV3Mode) {
2194 HostCtrl1 = BIT4|BIT3;
2195 Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
2196 if (EFI_ERROR (Status)) {
2197 return Status;
2198 }
2199 }
2200
2201 SdMmcHcLedOnOff (PciIo, Trb->Slot, TRUE);
2202
2203 if (Trb->Mode == SdMmcSdmaMode) {
2204 if ((!AddressingMode64) &&
2205 ((UINT64)(UINTN)Trb->DataPhy >= 0x100000000ul))
2206 {
2207 return EFI_INVALID_PARAMETER;
2208 }
2209
2210 SdmaAddr = (UINT64)(UINTN)Trb->DataPhy;
2211
2212 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {
2213 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (UINT64), &SdmaAddr);
2214 } else {
2215 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (UINT32), &SdmaAddr);
2216 }
2217
2218 if (EFI_ERROR (Status)) {
2219 return Status;
2220 }
2221 } else if ((Trb->Mode == SdMmcAdma32bMode) ||
2222 (Trb->Mode == SdMmcAdma64bV3Mode) ||
2223 (Trb->Mode == SdMmcAdma64bV4Mode))
2224 {
2225 AdmaAddr = (UINT64)(UINTN)Trb->AdmaDescPhy;
2226 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (AdmaAddr), &AdmaAddr);
2227 if (EFI_ERROR (Status)) {
2228 return Status;
2229 }
2230 }
2231
2232 BlkSize = Trb->BlockSize;
2233 if (Trb->Mode == SdMmcSdmaMode) {
2234 //
2235 // Set SDMA boundary to be 512K bytes.
2236 //
2237 BlkSize |= 0x7000;
2238 }
2239
2240 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_SIZE, FALSE, sizeof (BlkSize), &BlkSize);
2241 if (EFI_ERROR (Status)) {
2242 return Status;
2243 }
2244
2245 BlkCount = 0;
2246 if (Trb->Mode != SdMmcNoData) {
2247 //
2248 // Calcuate Block Count.
2249 //
2250 BlkCount = (Trb->DataLen / Trb->BlockSize);
2251 }
2252
2253 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_410) {
2254 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (UINT32), &BlkCount);
2255 } else {
2256 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_COUNT, FALSE, sizeof (UINT16), &BlkCount);
2257 }
2258
2259 if (EFI_ERROR (Status)) {
2260 return Status;
2261 }
2262
2263 Argument = Packet->SdMmcCmdBlk->CommandArgument;
2264 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ARG1, FALSE, sizeof (Argument), &Argument);
2265 if (EFI_ERROR (Status)) {
2266 return Status;
2267 }
2268
2269 TransMode = 0;
2270 if (Trb->Mode != SdMmcNoData) {
2271 if (Trb->Mode != SdMmcPioMode) {
2272 TransMode |= BIT0;
2273 }
2274
2275 if (Trb->Read) {
2276 TransMode |= BIT4;
2277 }
2278
2279 if (BlkCount > 1) {
2280 TransMode |= BIT5 | BIT1;
2281 }
2282
2283 //
2284 // Only SD memory card needs to use AUTO CMD12 feature.
2285 //
2286 if (Private->Slot[Trb->Slot].CardType == SdCardType) {
2287 if (BlkCount > 1) {
2288 TransMode |= BIT2;
2289 }
2290 }
2291 }
2292
2293 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_TRANS_MOD, FALSE, sizeof (TransMode), &TransMode);
2294 if (EFI_ERROR (Status)) {
2295 return Status;
2296 }
2297
2298 Cmd = (UINT16)LShiftU64 (Packet->SdMmcCmdBlk->CommandIndex, 8);
2299 if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) {
2300 Cmd |= BIT5;
2301 }
2302
2303 //
2304 // Convert ResponseType to value
2305 //
2306 if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
2307 switch (Packet->SdMmcCmdBlk->ResponseType) {
2308 case SdMmcResponseTypeR1:
2309 case SdMmcResponseTypeR5:
2310 case SdMmcResponseTypeR6:
2311 case SdMmcResponseTypeR7:
2312 Cmd |= (BIT1 | BIT3 | BIT4);
2313 break;
2314 case SdMmcResponseTypeR2:
2315 Cmd |= (BIT0 | BIT3);
2316 break;
2317 case SdMmcResponseTypeR3:
2318 case SdMmcResponseTypeR4:
2319 Cmd |= BIT1;
2320 break;
2321 case SdMmcResponseTypeR1b:
2322 case SdMmcResponseTypeR5b:
2323 Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);
2324 break;
2325 default:
2326 ASSERT (FALSE);
2327 break;
2328 }
2329 }
2330
2331 //
2332 // Execute cmd
2333 //
2334 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_COMMAND, FALSE, sizeof (Cmd), &Cmd);
2335 return Status;
2336 }
2337
2338 /**
2339 Performs SW reset based on passed error status mask.
2340
2341 @param[in] Private Pointer to driver private data.
2342 @param[in] Slot Index of the slot to reset.
2343 @param[in] ErrIntStatus Error interrupt status mask.
2344
2345 @retval EFI_SUCCESS Software reset performed successfully.
2346 @retval Other Software reset failed.
2347 **/
2348 EFI_STATUS
2349 SdMmcSoftwareReset (
2350 IN SD_MMC_HC_PRIVATE_DATA *Private,
2351 IN UINT8 Slot,
2352 IN UINT16 ErrIntStatus
2353 )
2354 {
2355 UINT8 SwReset;
2356 EFI_STATUS Status;
2357
2358 SwReset = 0;
2359 if ((ErrIntStatus & 0x0F) != 0) {
2360 SwReset |= BIT1;
2361 }
2362
2363 if ((ErrIntStatus & 0x70) != 0) {
2364 SwReset |= BIT2;
2365 }
2366
2367 Status = SdMmcHcRwMmio (
2368 Private->PciIo,
2369 Slot,
2370 SD_MMC_HC_SW_RST,
2371 FALSE,
2372 sizeof (SwReset),
2373 &SwReset
2374 );
2375 if (EFI_ERROR (Status)) {
2376 return Status;
2377 }
2378
2379 Status = SdMmcHcWaitMmioSet (
2380 Private->PciIo,
2381 Slot,
2382 SD_MMC_HC_SW_RST,
2383 sizeof (SwReset),
2384 0xFF,
2385 0,
2386 SD_MMC_HC_GENERIC_TIMEOUT
2387 );
2388 if (EFI_ERROR (Status)) {
2389 return Status;
2390 }
2391
2392 return EFI_SUCCESS;
2393 }
2394
2395 /**
2396 Checks the error status in error status register
2397 and issues appropriate software reset as described in
2398 SD specification section 3.10.
2399
2400 @param[in] Private Pointer to driver private data.
2401 @param[in] Slot Index of the slot for device.
2402 @param[in] IntStatus Normal interrupt status mask.
2403
2404 @retval EFI_CRC_ERROR CRC error happened during CMD execution.
2405 @retval EFI_SUCCESS No error reported.
2406 @retval Others Some other error happened.
2407
2408 **/
2409 EFI_STATUS
2410 SdMmcCheckAndRecoverErrors (
2411 IN SD_MMC_HC_PRIVATE_DATA *Private,
2412 IN UINT8 Slot,
2413 IN UINT16 IntStatus
2414 )
2415 {
2416 UINT16 ErrIntStatus;
2417 EFI_STATUS Status;
2418 EFI_STATUS ErrorStatus;
2419
2420 if ((IntStatus & BIT15) == 0) {
2421 return EFI_SUCCESS;
2422 }
2423
2424 Status = SdMmcHcRwMmio (
2425 Private->PciIo,
2426 Slot,
2427 SD_MMC_HC_ERR_INT_STS,
2428 TRUE,
2429 sizeof (ErrIntStatus),
2430 &ErrIntStatus
2431 );
2432 if (EFI_ERROR (Status)) {
2433 return Status;
2434 }
2435
2436 DEBUG ((DEBUG_ERROR, "Error reported by SDHCI\n"));
2437 DEBUG ((DEBUG_ERROR, "Interrupt status = %X\n", IntStatus));
2438 DEBUG ((DEBUG_ERROR, "Error interrupt status = %X\n", ErrIntStatus));
2439
2440 //
2441 // If the data timeout error is reported
2442 // but data transfer is signaled as completed we
2443 // have to ignore data timeout. We also assume that no
2444 // other error is present on the link since data transfer
2445 // completed successfully. Error interrupt status
2446 // register is going to be reset when the next command
2447 // is started.
2448 //
2449 if (((ErrIntStatus & BIT4) != 0) && ((IntStatus & BIT1) != 0)) {
2450 return EFI_SUCCESS;
2451 }
2452
2453 //
2454 // We treat both CMD and DAT CRC errors and
2455 // end bits errors as EFI_CRC_ERROR. This will
2456 // let higher layer know that the error possibly
2457 // happened due to random bus condition and the
2458 // command can be retried.
2459 //
2460 if ((ErrIntStatus & (BIT1 | BIT2 | BIT5 | BIT6)) != 0) {
2461 ErrorStatus = EFI_CRC_ERROR;
2462 } else {
2463 ErrorStatus = EFI_DEVICE_ERROR;
2464 }
2465
2466 Status = SdMmcSoftwareReset (Private, Slot, ErrIntStatus);
2467 if (EFI_ERROR (Status)) {
2468 return Status;
2469 }
2470
2471 return ErrorStatus;
2472 }
2473
2474 /**
2475 Reads the response data into the TRB buffer.
2476 This function assumes that caller made sure that
2477 command has completed.
2478
2479 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2480 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2481
2482 @retval EFI_SUCCESS Response read successfully.
2483 @retval Others Failed to get response.
2484 **/
2485 EFI_STATUS
2486 SdMmcGetResponse (
2487 IN SD_MMC_HC_PRIVATE_DATA *Private,
2488 IN SD_MMC_HC_TRB *Trb
2489 )
2490 {
2491 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
2492 UINT8 Index;
2493 UINT32 Response[4];
2494 EFI_STATUS Status;
2495
2496 Packet = Trb->Packet;
2497
2498 if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeBc) {
2499 return EFI_SUCCESS;
2500 }
2501
2502 for (Index = 0; Index < 4; Index++) {
2503 Status = SdMmcHcRwMmio (
2504 Private->PciIo,
2505 Trb->Slot,
2506 SD_MMC_HC_RESPONSE + Index * 4,
2507 TRUE,
2508 sizeof (UINT32),
2509 &Response[Index]
2510 );
2511 if (EFI_ERROR (Status)) {
2512 return Status;
2513 }
2514 }
2515
2516 CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response));
2517
2518 return EFI_SUCCESS;
2519 }
2520
2521 /**
2522 Checks if the command completed. If the command
2523 completed it gets the response and records the
2524 command completion in the TRB.
2525
2526 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2527 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2528 @param[in] IntStatus Snapshot of the normal interrupt status register.
2529
2530 @retval EFI_SUCCESS Command completed successfully.
2531 @retval EFI_NOT_READY Command completion still pending.
2532 @retval Others Command failed to complete.
2533 **/
2534 EFI_STATUS
2535 SdMmcCheckCommandComplete (
2536 IN SD_MMC_HC_PRIVATE_DATA *Private,
2537 IN SD_MMC_HC_TRB *Trb,
2538 IN UINT16 IntStatus
2539 )
2540 {
2541 UINT16 Data16;
2542 EFI_STATUS Status;
2543
2544 if ((IntStatus & BIT0) != 0) {
2545 Data16 = BIT0;
2546 Status = SdMmcHcRwMmio (
2547 Private->PciIo,
2548 Trb->Slot,
2549 SD_MMC_HC_NOR_INT_STS,
2550 FALSE,
2551 sizeof (Data16),
2552 &Data16
2553 );
2554 if (EFI_ERROR (Status)) {
2555 return Status;
2556 }
2557
2558 Status = SdMmcGetResponse (Private, Trb);
2559 if (EFI_ERROR (Status)) {
2560 return Status;
2561 }
2562
2563 Trb->CommandComplete = TRUE;
2564 return EFI_SUCCESS;
2565 }
2566
2567 return EFI_NOT_READY;
2568 }
2569
2570 /**
2571 Transfers data from card using PIO method.
2572
2573 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2574 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2575 @param[in] IntStatus Snapshot of the normal interrupt status register.
2576
2577 @retval EFI_SUCCESS PIO transfer completed successfully.
2578 @retval EFI_NOT_READY PIO transfer completion still pending.
2579 @retval Others PIO transfer failed to complete.
2580 **/
2581 EFI_STATUS
2582 SdMmcTransferDataWithPio (
2583 IN SD_MMC_HC_PRIVATE_DATA *Private,
2584 IN SD_MMC_HC_TRB *Trb,
2585 IN UINT16 IntStatus
2586 )
2587 {
2588 EFI_STATUS Status;
2589 UINT16 Data16;
2590 UINT32 BlockCount;
2591 EFI_PCI_IO_PROTOCOL_WIDTH Width;
2592 UINTN Count;
2593
2594 BlockCount = (Trb->DataLen / Trb->BlockSize);
2595 if (Trb->DataLen % Trb->BlockSize != 0) {
2596 BlockCount += 1;
2597 }
2598
2599 if (Trb->PioBlockIndex >= BlockCount) {
2600 return EFI_SUCCESS;
2601 }
2602
2603 switch (Trb->BlockSize % sizeof (UINT32)) {
2604 case 0:
2605 Width = EfiPciIoWidthFifoUint32;
2606 Count = Trb->BlockSize / sizeof (UINT32);
2607 break;
2608 case 2:
2609 Width = EfiPciIoWidthFifoUint16;
2610 Count = Trb->BlockSize / sizeof (UINT16);
2611 break;
2612 case 1:
2613 case 3:
2614 default:
2615 Width = EfiPciIoWidthFifoUint8;
2616 Count = Trb->BlockSize;
2617 break;
2618 }
2619
2620 if (Trb->Read) {
2621 if ((IntStatus & BIT5) == 0) {
2622 return EFI_NOT_READY;
2623 }
2624
2625 Data16 = BIT5;
2626 SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data16), &Data16);
2627
2628 Status = Private->PciIo->Mem.Read (
2629 Private->PciIo,
2630 Width,
2631 Trb->Slot,
2632 SD_MMC_HC_BUF_DAT_PORT,
2633 Count,
2634 (VOID *)((UINT8 *)Trb->Data + (Trb->BlockSize * Trb->PioBlockIndex))
2635 );
2636 if (EFI_ERROR (Status)) {
2637 return Status;
2638 }
2639
2640 Trb->PioBlockIndex++;
2641 } else {
2642 if ((IntStatus & BIT4) == 0) {
2643 return EFI_NOT_READY;
2644 }
2645
2646 Data16 = BIT4;
2647 SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data16), &Data16);
2648
2649 Status = Private->PciIo->Mem.Write (
2650 Private->PciIo,
2651 Width,
2652 Trb->Slot,
2653 SD_MMC_HC_BUF_DAT_PORT,
2654 Count,
2655 (VOID *)((UINT8 *)Trb->Data + (Trb->BlockSize * Trb->PioBlockIndex))
2656 );
2657 if (EFI_ERROR (Status)) {
2658 return Status;
2659 }
2660
2661 Trb->PioBlockIndex++;
2662 }
2663
2664 if (Trb->PioBlockIndex >= BlockCount) {
2665 Trb->PioModeTransferCompleted = TRUE;
2666 return EFI_SUCCESS;
2667 } else {
2668 return EFI_NOT_READY;
2669 }
2670 }
2671
2672 /**
2673 Update the SDMA address on the SDMA buffer boundary interrupt.
2674
2675 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2676 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2677
2678 @retval EFI_SUCCESS Updated SDMA buffer address.
2679 @retval Others Failed to update SDMA buffer address.
2680 **/
2681 EFI_STATUS
2682 SdMmcUpdateSdmaAddress (
2683 IN SD_MMC_HC_PRIVATE_DATA *Private,
2684 IN SD_MMC_HC_TRB *Trb
2685 )
2686 {
2687 UINT64 SdmaAddr;
2688 EFI_STATUS Status;
2689
2690 SdmaAddr = SD_MMC_SDMA_ROUND_UP ((UINTN)Trb->DataPhy, SD_MMC_SDMA_BOUNDARY);
2691
2692 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {
2693 Status = SdMmcHcRwMmio (
2694 Private->PciIo,
2695 Trb->Slot,
2696 SD_MMC_HC_ADMA_SYS_ADDR,
2697 FALSE,
2698 sizeof (UINT64),
2699 &SdmaAddr
2700 );
2701 } else {
2702 Status = SdMmcHcRwMmio (
2703 Private->PciIo,
2704 Trb->Slot,
2705 SD_MMC_HC_SDMA_ADDR,
2706 FALSE,
2707 sizeof (UINT32),
2708 &SdmaAddr
2709 );
2710 }
2711
2712 if (EFI_ERROR (Status)) {
2713 return Status;
2714 }
2715
2716 Trb->DataPhy = (UINT64)(UINTN)SdmaAddr;
2717 return EFI_SUCCESS;
2718 }
2719
2720 /**
2721 Checks if the data transfer completed and performs any actions
2722 neccessary to continue the data transfer such as SDMA system
2723 address fixup or PIO data transfer.
2724
2725 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2726 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2727 @param[in] IntStatus Snapshot of the normal interrupt status register.
2728
2729 @retval EFI_SUCCESS Data transfer completed successfully.
2730 @retval EFI_NOT_READY Data transfer completion still pending.
2731 @retval Others Data transfer failed to complete.
2732 **/
2733 EFI_STATUS
2734 SdMmcCheckDataTransfer (
2735 IN SD_MMC_HC_PRIVATE_DATA *Private,
2736 IN SD_MMC_HC_TRB *Trb,
2737 IN UINT16 IntStatus
2738 )
2739 {
2740 UINT16 Data16;
2741 EFI_STATUS Status;
2742
2743 if ((IntStatus & BIT1) != 0) {
2744 Data16 = BIT1;
2745 Status = SdMmcHcRwMmio (
2746 Private->PciIo,
2747 Trb->Slot,
2748 SD_MMC_HC_NOR_INT_STS,
2749 FALSE,
2750 sizeof (Data16),
2751 &Data16
2752 );
2753 return Status;
2754 }
2755
2756 if ((Trb->Mode == SdMmcPioMode) && !Trb->PioModeTransferCompleted) {
2757 Status = SdMmcTransferDataWithPio (Private, Trb, IntStatus);
2758 if (EFI_ERROR (Status)) {
2759 return Status;
2760 }
2761 }
2762
2763 if ((Trb->Mode == SdMmcSdmaMode) && ((IntStatus & BIT3) != 0)) {
2764 Data16 = BIT3;
2765 Status = SdMmcHcRwMmio (
2766 Private->PciIo,
2767 Trb->Slot,
2768 SD_MMC_HC_NOR_INT_STS,
2769 FALSE,
2770 sizeof (Data16),
2771 &Data16
2772 );
2773 if (EFI_ERROR (Status)) {
2774 return Status;
2775 }
2776
2777 Status = SdMmcUpdateSdmaAddress (Private, Trb);
2778 if (EFI_ERROR (Status)) {
2779 return Status;
2780 }
2781 }
2782
2783 return EFI_NOT_READY;
2784 }
2785
2786 /**
2787 Check the TRB execution result.
2788
2789 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2790 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2791
2792 @retval EFI_SUCCESS The TRB is executed successfully.
2793 @retval EFI_NOT_READY The TRB is not completed for execution.
2794 @retval Others Some erros happen when executing this request.
2795
2796 **/
2797 EFI_STATUS
2798 SdMmcCheckTrbResult (
2799 IN SD_MMC_HC_PRIVATE_DATA *Private,
2800 IN SD_MMC_HC_TRB *Trb
2801 )
2802 {
2803 EFI_STATUS Status;
2804 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
2805 UINT16 IntStatus;
2806
2807 Packet = Trb->Packet;
2808 //
2809 // Check Trb execution result by reading Normal Interrupt Status register.
2810 //
2811 Status = SdMmcHcRwMmio (
2812 Private->PciIo,
2813 Trb->Slot,
2814 SD_MMC_HC_NOR_INT_STS,
2815 TRUE,
2816 sizeof (IntStatus),
2817 &IntStatus
2818 );
2819 if (EFI_ERROR (Status)) {
2820 goto Done;
2821 }
2822
2823 //
2824 // Check if there are any errors reported by host controller
2825 // and if neccessary recover the controller before next command is executed.
2826 //
2827 Status = SdMmcCheckAndRecoverErrors (Private, Trb->Slot, IntStatus);
2828 if (EFI_ERROR (Status)) {
2829 goto Done;
2830 }
2831
2832 //
2833 // Tuning commands are the only ones that do not generate command
2834 // complete interrupt. Process them here before entering the code
2835 // that waits for command completion.
2836 //
2837 if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
2838 (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
2839 ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
2840 (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK)))
2841 {
2842 Status = SdMmcTransferDataWithPio (Private, Trb, IntStatus);
2843 goto Done;
2844 }
2845
2846 if (!Trb->CommandComplete) {
2847 Status = SdMmcCheckCommandComplete (Private, Trb, IntStatus);
2848 if (EFI_ERROR (Status)) {
2849 goto Done;
2850 }
2851 }
2852
2853 if ((Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) ||
2854 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b) ||
2855 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b))
2856 {
2857 Status = SdMmcCheckDataTransfer (Private, Trb, IntStatus);
2858 } else {
2859 Status = EFI_SUCCESS;
2860 }
2861
2862 Done:
2863 if (Status != EFI_NOT_READY) {
2864 SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);
2865 if (EFI_ERROR (Status)) {
2866 DEBUG ((DEBUG_ERROR, "TRB failed with %r\n", Status));
2867 SdMmcPrintTrb (DEBUG_ERROR, Trb);
2868 } else {
2869 DEBUG ((DEBUG_VERBOSE, "TRB success\n"));
2870 SdMmcPrintTrb (DEBUG_VERBOSE, Trb);
2871 }
2872 }
2873
2874 return Status;
2875 }
2876
2877 /**
2878 Wait for the TRB execution result.
2879
2880 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2881 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2882
2883 @retval EFI_SUCCESS The TRB is executed successfully.
2884 @retval Others Some erros happen when executing this request.
2885
2886 **/
2887 EFI_STATUS
2888 SdMmcWaitTrbResult (
2889 IN SD_MMC_HC_PRIVATE_DATA *Private,
2890 IN SD_MMC_HC_TRB *Trb
2891 )
2892 {
2893 EFI_STATUS Status;
2894 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
2895 UINT64 Timeout;
2896 BOOLEAN InfiniteWait;
2897
2898 Packet = Trb->Packet;
2899 //
2900 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
2901 //
2902 Timeout = Packet->Timeout;
2903 if (Timeout == 0) {
2904 InfiniteWait = TRUE;
2905 } else {
2906 InfiniteWait = FALSE;
2907 }
2908
2909 while (InfiniteWait || (Timeout > 0)) {
2910 //
2911 // Check Trb execution result by reading Normal Interrupt Status register.
2912 //
2913 Status = SdMmcCheckTrbResult (Private, Trb);
2914 if (Status != EFI_NOT_READY) {
2915 return Status;
2916 }
2917
2918 //
2919 // Stall for 1 microsecond.
2920 //
2921 gBS->Stall (1);
2922
2923 Timeout--;
2924 }
2925
2926 return EFI_TIMEOUT;
2927 }
EFI Development Kit II mirror for PVE