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MdeModulePkg/SdMmcPciHcDxe: Hook SwitchClockFreq after SD clock start
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / SdMmcPciHcDxe / SdMmcPciHci.c
1 /** @file
2 This driver is used to manage SD/MMC PCI host controllers which are compliance
3 with SD Host Controller Simplified Specification version 3.00 plus the 64-bit
4 System Addressing support in SD Host Controller Simplified Specification version
5 4.20.
6
7 It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
8
9 Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
10 Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
11 SPDX-License-Identifier: BSD-2-Clause-Patent
12
13 **/
14
15 #include "SdMmcPciHcDxe.h"
16
17 /**
18 Dump the content of SD/MMC host controller's Capability Register.
19
20 @param[in] Slot The slot number of the SD card to send the command to.
21 @param[in] Capability The buffer to store the capability data.
22
23 **/
24 VOID
25 DumpCapabilityReg (
26 IN UINT8 Slot,
27 IN SD_MMC_HC_SLOT_CAP *Capability
28 )
29 {
30 //
31 // Dump Capability Data
32 //
33 DEBUG ((DEBUG_INFO, " == Slot [%d] Capability is 0x%x ==\n", Slot, Capability));
34 DEBUG ((DEBUG_INFO, " Timeout Clk Freq %d%a\n", Capability->TimeoutFreq, (Capability->TimeoutUnit) ? "MHz" : "KHz"));
35 DEBUG ((DEBUG_INFO, " Base Clk Freq %dMHz\n", Capability->BaseClkFreq));
36 DEBUG ((DEBUG_INFO, " Max Blk Len %dbytes\n", 512 * (1 << Capability->MaxBlkLen)));
37 DEBUG ((DEBUG_INFO, " 8-bit Support %a\n", Capability->BusWidth8 ? "TRUE" : "FALSE"));
38 DEBUG ((DEBUG_INFO, " ADMA2 Support %a\n", Capability->Adma2 ? "TRUE" : "FALSE"));
39 DEBUG ((DEBUG_INFO, " HighSpeed Support %a\n", Capability->HighSpeed ? "TRUE" : "FALSE"));
40 DEBUG ((DEBUG_INFO, " SDMA Support %a\n", Capability->Sdma ? "TRUE" : "FALSE"));
41 DEBUG ((DEBUG_INFO, " Suspend/Resume %a\n", Capability->SuspRes ? "TRUE" : "FALSE"));
42 DEBUG ((DEBUG_INFO, " Voltage 3.3 %a\n", Capability->Voltage33 ? "TRUE" : "FALSE"));
43 DEBUG ((DEBUG_INFO, " Voltage 3.0 %a\n", Capability->Voltage30 ? "TRUE" : "FALSE"));
44 DEBUG ((DEBUG_INFO, " Voltage 1.8 %a\n", Capability->Voltage18 ? "TRUE" : "FALSE"));
45 DEBUG ((DEBUG_INFO, " V4 64-bit Sys Bus %a\n", Capability->SysBus64V4 ? "TRUE" : "FALSE"));
46 DEBUG ((DEBUG_INFO, " V3 64-bit Sys Bus %a\n", Capability->SysBus64V3 ? "TRUE" : "FALSE"));
47 DEBUG ((DEBUG_INFO, " Async Interrupt %a\n", Capability->AsyncInt ? "TRUE" : "FALSE"));
48 DEBUG ((DEBUG_INFO, " SlotType "));
49 if (Capability->SlotType == 0x00) {
50 DEBUG ((DEBUG_INFO, "%a\n", "Removable Slot"));
51 } else if (Capability->SlotType == 0x01) {
52 DEBUG ((DEBUG_INFO, "%a\n", "Embedded Slot"));
53 } else if (Capability->SlotType == 0x02) {
54 DEBUG ((DEBUG_INFO, "%a\n", "Shared Bus Slot"));
55 } else {
56 DEBUG ((DEBUG_INFO, "%a\n", "Reserved"));
57 }
58 DEBUG ((DEBUG_INFO, " SDR50 Support %a\n", Capability->Sdr50 ? "TRUE" : "FALSE"));
59 DEBUG ((DEBUG_INFO, " SDR104 Support %a\n", Capability->Sdr104 ? "TRUE" : "FALSE"));
60 DEBUG ((DEBUG_INFO, " DDR50 Support %a\n", Capability->Ddr50 ? "TRUE" : "FALSE"));
61 DEBUG ((DEBUG_INFO, " Driver Type A %a\n", Capability->DriverTypeA ? "TRUE" : "FALSE"));
62 DEBUG ((DEBUG_INFO, " Driver Type C %a\n", Capability->DriverTypeC ? "TRUE" : "FALSE"));
63 DEBUG ((DEBUG_INFO, " Driver Type D %a\n", Capability->DriverTypeD ? "TRUE" : "FALSE"));
64 DEBUG ((DEBUG_INFO, " Driver Type 4 %a\n", Capability->DriverType4 ? "TRUE" : "FALSE"));
65 if (Capability->TimerCount == 0) {
66 DEBUG ((DEBUG_INFO, " Retuning TimerCnt Disabled\n", 2 * (Capability->TimerCount - 1)));
67 } else {
68 DEBUG ((DEBUG_INFO, " Retuning TimerCnt %dseconds\n", 2 * (Capability->TimerCount - 1)));
69 }
70 DEBUG ((DEBUG_INFO, " SDR50 Tuning %a\n", Capability->TuningSDR50 ? "TRUE" : "FALSE"));
71 DEBUG ((DEBUG_INFO, " Retuning Mode Mode %d\n", Capability->RetuningMod + 1));
72 DEBUG ((DEBUG_INFO, " Clock Multiplier M = %d\n", Capability->ClkMultiplier + 1));
73 DEBUG ((DEBUG_INFO, " HS 400 %a\n", Capability->Hs400 ? "TRUE" : "FALSE"));
74 return;
75 }
76
77 /**
78 Read SlotInfo register from SD/MMC host controller pci config space.
79
80 @param[in] PciIo The PCI IO protocol instance.
81 @param[out] FirstBar The buffer to store the first BAR value.
82 @param[out] SlotNum The buffer to store the supported slot number.
83
84 @retval EFI_SUCCESS The operation succeeds.
85 @retval Others The operation fails.
86
87 **/
88 EFI_STATUS
89 EFIAPI
90 SdMmcHcGetSlotInfo (
91 IN EFI_PCI_IO_PROTOCOL *PciIo,
92 OUT UINT8 *FirstBar,
93 OUT UINT8 *SlotNum
94 )
95 {
96 EFI_STATUS Status;
97 SD_MMC_HC_SLOT_INFO SlotInfo;
98
99 Status = PciIo->Pci.Read (
100 PciIo,
101 EfiPciIoWidthUint8,
102 SD_MMC_HC_SLOT_OFFSET,
103 sizeof (SlotInfo),
104 &SlotInfo
105 );
106 if (EFI_ERROR (Status)) {
107 return Status;
108 }
109
110 *FirstBar = SlotInfo.FirstBar;
111 *SlotNum = SlotInfo.SlotNum + 1;
112 ASSERT ((*FirstBar + *SlotNum) < SD_MMC_HC_MAX_SLOT);
113 return EFI_SUCCESS;
114 }
115
116 /**
117 Read/Write specified SD/MMC host controller mmio register.
118
119 @param[in] PciIo The PCI IO protocol instance.
120 @param[in] BarIndex The BAR index of the standard PCI Configuration
121 header to use as the base address for the memory
122 operation to perform.
123 @param[in] Offset The offset within the selected BAR to start the
124 memory operation.
125 @param[in] Read A boolean to indicate it's read or write operation.
126 @param[in] Count The width of the mmio register in bytes.
127 Must be 1, 2 , 4 or 8 bytes.
128 @param[in, out] Data For read operations, the destination buffer to store
129 the results. For write operations, the source buffer
130 to write data from. The caller is responsible for
131 having ownership of the data buffer and ensuring its
132 size not less than Count bytes.
133
134 @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
135 @retval EFI_SUCCESS The read/write operation succeeds.
136 @retval Others The read/write operation fails.
137
138 **/
139 EFI_STATUS
140 EFIAPI
141 SdMmcHcRwMmio (
142 IN EFI_PCI_IO_PROTOCOL *PciIo,
143 IN UINT8 BarIndex,
144 IN UINT32 Offset,
145 IN BOOLEAN Read,
146 IN UINT8 Count,
147 IN OUT VOID *Data
148 )
149 {
150 EFI_STATUS Status;
151 EFI_PCI_IO_PROTOCOL_WIDTH Width;
152
153 if ((PciIo == NULL) || (Data == NULL)) {
154 return EFI_INVALID_PARAMETER;
155 }
156
157 switch (Count) {
158 case 1:
159 Width = EfiPciIoWidthUint8;
160 break;
161 case 2:
162 Width = EfiPciIoWidthUint16;
163 Count = 1;
164 break;
165 case 4:
166 Width = EfiPciIoWidthUint32;
167 Count = 1;
168 break;
169 case 8:
170 Width = EfiPciIoWidthUint32;
171 Count = 2;
172 break;
173 default:
174 return EFI_INVALID_PARAMETER;
175 }
176
177 if (Read) {
178 Status = PciIo->Mem.Read (
179 PciIo,
180 Width,
181 BarIndex,
182 (UINT64) Offset,
183 Count,
184 Data
185 );
186 } else {
187 Status = PciIo->Mem.Write (
188 PciIo,
189 Width,
190 BarIndex,
191 (UINT64) Offset,
192 Count,
193 Data
194 );
195 }
196
197 return Status;
198 }
199
200 /**
201 Do OR operation with the value of the specified SD/MMC host controller mmio register.
202
203 @param[in] PciIo The PCI IO protocol instance.
204 @param[in] BarIndex The BAR index of the standard PCI Configuration
205 header to use as the base address for the memory
206 operation to perform.
207 @param[in] Offset The offset within the selected BAR to start the
208 memory operation.
209 @param[in] Count The width of the mmio register in bytes.
210 Must be 1, 2 , 4 or 8 bytes.
211 @param[in] OrData The pointer to the data used to do OR operation.
212 The caller is responsible for having ownership of
213 the data buffer and ensuring its size not less than
214 Count bytes.
215
216 @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
217 @retval EFI_SUCCESS The OR operation succeeds.
218 @retval Others The OR operation fails.
219
220 **/
221 EFI_STATUS
222 EFIAPI
223 SdMmcHcOrMmio (
224 IN EFI_PCI_IO_PROTOCOL *PciIo,
225 IN UINT8 BarIndex,
226 IN UINT32 Offset,
227 IN UINT8 Count,
228 IN VOID *OrData
229 )
230 {
231 EFI_STATUS Status;
232 UINT64 Data;
233 UINT64 Or;
234
235 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
236 if (EFI_ERROR (Status)) {
237 return Status;
238 }
239
240 if (Count == 1) {
241 Or = *(UINT8*) OrData;
242 } else if (Count == 2) {
243 Or = *(UINT16*) OrData;
244 } else if (Count == 4) {
245 Or = *(UINT32*) OrData;
246 } else if (Count == 8) {
247 Or = *(UINT64*) OrData;
248 } else {
249 return EFI_INVALID_PARAMETER;
250 }
251
252 Data |= Or;
253 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
254
255 return Status;
256 }
257
258 /**
259 Do AND operation with the value of the specified SD/MMC host controller mmio register.
260
261 @param[in] PciIo The PCI IO protocol instance.
262 @param[in] BarIndex The BAR index of the standard PCI Configuration
263 header to use as the base address for the memory
264 operation to perform.
265 @param[in] Offset The offset within the selected BAR to start the
266 memory operation.
267 @param[in] Count The width of the mmio register in bytes.
268 Must be 1, 2 , 4 or 8 bytes.
269 @param[in] AndData The pointer to the data used to do AND operation.
270 The caller is responsible for having ownership of
271 the data buffer and ensuring its size not less than
272 Count bytes.
273
274 @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
275 @retval EFI_SUCCESS The AND operation succeeds.
276 @retval Others The AND operation fails.
277
278 **/
279 EFI_STATUS
280 EFIAPI
281 SdMmcHcAndMmio (
282 IN EFI_PCI_IO_PROTOCOL *PciIo,
283 IN UINT8 BarIndex,
284 IN UINT32 Offset,
285 IN UINT8 Count,
286 IN VOID *AndData
287 )
288 {
289 EFI_STATUS Status;
290 UINT64 Data;
291 UINT64 And;
292
293 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
294 if (EFI_ERROR (Status)) {
295 return Status;
296 }
297
298 if (Count == 1) {
299 And = *(UINT8*) AndData;
300 } else if (Count == 2) {
301 And = *(UINT16*) AndData;
302 } else if (Count == 4) {
303 And = *(UINT32*) AndData;
304 } else if (Count == 8) {
305 And = *(UINT64*) AndData;
306 } else {
307 return EFI_INVALID_PARAMETER;
308 }
309
310 Data &= And;
311 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
312
313 return Status;
314 }
315
316 /**
317 Wait for the value of the specified MMIO register set to the test value.
318
319 @param[in] PciIo The PCI IO protocol instance.
320 @param[in] BarIndex The BAR index of the standard PCI Configuration
321 header to use as the base address for the memory
322 operation to perform.
323 @param[in] Offset The offset within the selected BAR to start the
324 memory operation.
325 @param[in] Count The width of the mmio register in bytes.
326 Must be 1, 2, 4 or 8 bytes.
327 @param[in] MaskValue The mask value of memory.
328 @param[in] TestValue The test value of memory.
329
330 @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.
331 @retval EFI_SUCCESS The MMIO register has expected value.
332 @retval Others The MMIO operation fails.
333
334 **/
335 EFI_STATUS
336 EFIAPI
337 SdMmcHcCheckMmioSet (
338 IN EFI_PCI_IO_PROTOCOL *PciIo,
339 IN UINT8 BarIndex,
340 IN UINT32 Offset,
341 IN UINT8 Count,
342 IN UINT64 MaskValue,
343 IN UINT64 TestValue
344 )
345 {
346 EFI_STATUS Status;
347 UINT64 Value;
348
349 //
350 // Access PCI MMIO space to see if the value is the tested one.
351 //
352 Value = 0;
353 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Value);
354 if (EFI_ERROR (Status)) {
355 return Status;
356 }
357
358 Value &= MaskValue;
359
360 if (Value == TestValue) {
361 return EFI_SUCCESS;
362 }
363
364 return EFI_NOT_READY;
365 }
366
367 /**
368 Wait for the value of the specified MMIO register set to the test value.
369
370 @param[in] PciIo The PCI IO protocol instance.
371 @param[in] BarIndex The BAR index of the standard PCI Configuration
372 header to use as the base address for the memory
373 operation to perform.
374 @param[in] Offset The offset within the selected BAR to start the
375 memory operation.
376 @param[in] Count The width of the mmio register in bytes.
377 Must be 1, 2, 4 or 8 bytes.
378 @param[in] MaskValue The mask value of memory.
379 @param[in] TestValue The test value of memory.
380 @param[in] Timeout The time out value for wait memory set, uses 1
381 microsecond as a unit.
382
383 @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout
384 range.
385 @retval EFI_SUCCESS The MMIO register has expected value.
386 @retval Others The MMIO operation fails.
387
388 **/
389 EFI_STATUS
390 EFIAPI
391 SdMmcHcWaitMmioSet (
392 IN EFI_PCI_IO_PROTOCOL *PciIo,
393 IN UINT8 BarIndex,
394 IN UINT32 Offset,
395 IN UINT8 Count,
396 IN UINT64 MaskValue,
397 IN UINT64 TestValue,
398 IN UINT64 Timeout
399 )
400 {
401 EFI_STATUS Status;
402 BOOLEAN InfiniteWait;
403
404 if (Timeout == 0) {
405 InfiniteWait = TRUE;
406 } else {
407 InfiniteWait = FALSE;
408 }
409
410 while (InfiniteWait || (Timeout > 0)) {
411 Status = SdMmcHcCheckMmioSet (
412 PciIo,
413 BarIndex,
414 Offset,
415 Count,
416 MaskValue,
417 TestValue
418 );
419 if (Status != EFI_NOT_READY) {
420 return Status;
421 }
422
423 //
424 // Stall for 1 microsecond.
425 //
426 gBS->Stall (1);
427
428 Timeout--;
429 }
430
431 return EFI_TIMEOUT;
432 }
433
434 /**
435 Get the controller version information from the specified slot.
436
437 @param[in] PciIo The PCI IO protocol instance.
438 @param[in] Slot The slot number of the SD card to send the command to.
439 @param[out] Version The buffer to store the version information.
440
441 @retval EFI_SUCCESS The operation executes successfully.
442 @retval Others The operation fails.
443
444 **/
445 EFI_STATUS
446 SdMmcHcGetControllerVersion (
447 IN EFI_PCI_IO_PROTOCOL *PciIo,
448 IN UINT8 Slot,
449 OUT UINT16 *Version
450 )
451 {
452 EFI_STATUS Status;
453
454 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CTRL_VER, TRUE, sizeof (UINT16), Version);
455 if (EFI_ERROR (Status)) {
456 return Status;
457 }
458
459 *Version &= 0xFF;
460
461 return EFI_SUCCESS;
462 }
463
464 /**
465 Software reset the specified SD/MMC host controller and enable all interrupts.
466
467 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
468 @param[in] Slot The slot number of the SD card to send the command to.
469
470 @retval EFI_SUCCESS The software reset executes successfully.
471 @retval Others The software reset fails.
472
473 **/
474 EFI_STATUS
475 SdMmcHcReset (
476 IN SD_MMC_HC_PRIVATE_DATA *Private,
477 IN UINT8 Slot
478 )
479 {
480 EFI_STATUS Status;
481 UINT8 SwReset;
482 EFI_PCI_IO_PROTOCOL *PciIo;
483
484 //
485 // Notify the SD/MMC override protocol that we are about to reset
486 // the SD/MMC host controller.
487 //
488 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
489 Status = mOverride->NotifyPhase (
490 Private->ControllerHandle,
491 Slot,
492 EdkiiSdMmcResetPre,
493 NULL);
494 if (EFI_ERROR (Status)) {
495 DEBUG ((DEBUG_WARN,
496 "%a: SD/MMC pre reset notifier callback failed - %r\n",
497 __FUNCTION__, Status));
498 return Status;
499 }
500 }
501
502 PciIo = Private->PciIo;
503 SwReset = BIT0;
504 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_SW_RST, sizeof (SwReset), &SwReset);
505
506 if (EFI_ERROR (Status)) {
507 DEBUG ((DEBUG_ERROR, "SdMmcHcReset: write SW Reset for All fails: %r\n", Status));
508 return Status;
509 }
510
511 Status = SdMmcHcWaitMmioSet (
512 PciIo,
513 Slot,
514 SD_MMC_HC_SW_RST,
515 sizeof (SwReset),
516 BIT0,
517 0x00,
518 SD_MMC_HC_GENERIC_TIMEOUT
519 );
520 if (EFI_ERROR (Status)) {
521 DEBUG ((DEBUG_INFO, "SdMmcHcReset: reset done with %r\n", Status));
522 return Status;
523 }
524
525 //
526 // Enable all interrupt after reset all.
527 //
528 Status = SdMmcHcEnableInterrupt (PciIo, Slot);
529 if (EFI_ERROR (Status)) {
530 DEBUG ((DEBUG_INFO, "SdMmcHcReset: SdMmcHcEnableInterrupt done with %r\n",
531 Status));
532 return Status;
533 }
534
535 //
536 // Notify the SD/MMC override protocol that we have just reset
537 // the SD/MMC host controller.
538 //
539 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
540 Status = mOverride->NotifyPhase (
541 Private->ControllerHandle,
542 Slot,
543 EdkiiSdMmcResetPost,
544 NULL);
545 if (EFI_ERROR (Status)) {
546 DEBUG ((DEBUG_WARN,
547 "%a: SD/MMC post reset notifier callback failed - %r\n",
548 __FUNCTION__, Status));
549 }
550 }
551
552 return Status;
553 }
554
555 /**
556 Set all interrupt status bits in Normal and Error Interrupt Status Enable
557 register.
558
559 @param[in] PciIo The PCI IO protocol instance.
560 @param[in] Slot The slot number of the SD card to send the command to.
561
562 @retval EFI_SUCCESS The operation executes successfully.
563 @retval Others The operation fails.
564
565 **/
566 EFI_STATUS
567 SdMmcHcEnableInterrupt (
568 IN EFI_PCI_IO_PROTOCOL *PciIo,
569 IN UINT8 Slot
570 )
571 {
572 EFI_STATUS Status;
573 UINT16 IntStatus;
574
575 //
576 // Enable all bits in Error Interrupt Status Enable Register
577 //
578 IntStatus = 0xFFFF;
579 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
580 if (EFI_ERROR (Status)) {
581 return Status;
582 }
583 //
584 // Enable all bits in Normal Interrupt Status Enable Register
585 //
586 IntStatus = 0xFFFF;
587 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
588
589 return Status;
590 }
591
592 /**
593 Get the capability data from the specified slot.
594
595 @param[in] PciIo The PCI IO protocol instance.
596 @param[in] Slot The slot number of the SD card to send the command to.
597 @param[out] Capability The buffer to store the capability data.
598
599 @retval EFI_SUCCESS The operation executes successfully.
600 @retval Others The operation fails.
601
602 **/
603 EFI_STATUS
604 SdMmcHcGetCapability (
605 IN EFI_PCI_IO_PROTOCOL *PciIo,
606 IN UINT8 Slot,
607 OUT SD_MMC_HC_SLOT_CAP *Capability
608 )
609 {
610 EFI_STATUS Status;
611 UINT64 Cap;
612
613 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CAP, TRUE, sizeof (Cap), &Cap);
614 if (EFI_ERROR (Status)) {
615 return Status;
616 }
617
618 CopyMem (Capability, &Cap, sizeof (Cap));
619
620 return EFI_SUCCESS;
621 }
622
623 /**
624 Get the maximum current capability data from the specified slot.
625
626 @param[in] PciIo The PCI IO protocol instance.
627 @param[in] Slot The slot number of the SD card to send the command to.
628 @param[out] MaxCurrent The buffer to store the maximum current capability data.
629
630 @retval EFI_SUCCESS The operation executes successfully.
631 @retval Others The operation fails.
632
633 **/
634 EFI_STATUS
635 SdMmcHcGetMaxCurrent (
636 IN EFI_PCI_IO_PROTOCOL *PciIo,
637 IN UINT8 Slot,
638 OUT UINT64 *MaxCurrent
639 )
640 {
641 EFI_STATUS Status;
642
643 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_MAX_CURRENT_CAP, TRUE, sizeof (UINT64), MaxCurrent);
644
645 return Status;
646 }
647
648 /**
649 Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
650 slot.
651
652 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
653
654 @param[in] PciIo The PCI IO protocol instance.
655 @param[in] Slot The slot number of the SD card to send the command to.
656 @param[out] MediaPresent The pointer to the media present boolean value.
657
658 @retval EFI_SUCCESS There is no media change happened.
659 @retval EFI_MEDIA_CHANGED There is media change happened.
660 @retval Others The detection fails.
661
662 **/
663 EFI_STATUS
664 SdMmcHcCardDetect (
665 IN EFI_PCI_IO_PROTOCOL *PciIo,
666 IN UINT8 Slot,
667 OUT BOOLEAN *MediaPresent
668 )
669 {
670 EFI_STATUS Status;
671 UINT16 Data;
672 UINT32 PresentState;
673
674 //
675 // Check Present State Register to see if there is a card presented.
676 //
677 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);
678 if (EFI_ERROR (Status)) {
679 return Status;
680 }
681
682 if ((PresentState & BIT16) != 0) {
683 *MediaPresent = TRUE;
684 } else {
685 *MediaPresent = FALSE;
686 }
687
688 //
689 // Check Normal Interrupt Status Register
690 //
691 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, TRUE, sizeof (Data), &Data);
692 if (EFI_ERROR (Status)) {
693 return Status;
694 }
695
696 if ((Data & (BIT6 | BIT7)) != 0) {
697 //
698 // Clear BIT6 and BIT7 by writing 1 to these two bits if set.
699 //
700 Data &= BIT6 | BIT7;
701 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data), &Data);
702 if (EFI_ERROR (Status)) {
703 return Status;
704 }
705
706 return EFI_MEDIA_CHANGED;
707 }
708
709 return EFI_SUCCESS;
710 }
711
712 /**
713 Stop SD/MMC card clock.
714
715 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
716
717 @param[in] PciIo The PCI IO protocol instance.
718 @param[in] Slot The slot number of the SD card to send the command to.
719
720 @retval EFI_SUCCESS Succeed to stop SD/MMC clock.
721 @retval Others Fail to stop SD/MMC clock.
722
723 **/
724 EFI_STATUS
725 SdMmcHcStopClock (
726 IN EFI_PCI_IO_PROTOCOL *PciIo,
727 IN UINT8 Slot
728 )
729 {
730 EFI_STATUS Status;
731 UINT32 PresentState;
732 UINT16 ClockCtrl;
733
734 //
735 // Ensure no SD transactions are occurring on the SD Bus by
736 // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)
737 // in the Present State register to be 0.
738 //
739 Status = SdMmcHcWaitMmioSet (
740 PciIo,
741 Slot,
742 SD_MMC_HC_PRESENT_STATE,
743 sizeof (PresentState),
744 BIT0 | BIT1,
745 0,
746 SD_MMC_HC_GENERIC_TIMEOUT
747 );
748 if (EFI_ERROR (Status)) {
749 return Status;
750 }
751
752 //
753 // Set SD Clock Enable in the Clock Control register to 0
754 //
755 ClockCtrl = (UINT16)~BIT2;
756 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
757
758 return Status;
759 }
760
761 /**
762 SD/MMC card clock supply.
763
764 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
765
766 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
767 @param[in] Slot The slot number of the SD card to send the command to.
768 @param[in] BusTiming BusTiming at which the frequency change is done.
769 @param[in] FirstTimeSetup Flag to indicate whether the clock is being setup for the first time.
770 @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
771
772 @retval EFI_SUCCESS The clock is supplied successfully.
773 @retval Others The clock isn't supplied successfully.
774
775 **/
776 EFI_STATUS
777 SdMmcHcClockSupply (
778 IN SD_MMC_HC_PRIVATE_DATA *Private,
779 IN UINT8 Slot,
780 IN SD_MMC_BUS_MODE BusTiming,
781 IN BOOLEAN FirstTimeSetup,
782 IN UINT64 ClockFreq
783 )
784 {
785 EFI_STATUS Status;
786 UINT32 SettingFreq;
787 UINT32 Divisor;
788 UINT32 Remainder;
789 UINT16 ClockCtrl;
790 UINT32 BaseClkFreq;
791 UINT16 ControllerVer;
792 EFI_PCI_IO_PROTOCOL *PciIo;
793
794 PciIo = Private->PciIo;
795 BaseClkFreq = Private->BaseClkFreq[Slot];
796 ControllerVer = Private->ControllerVersion[Slot];
797
798 if (BaseClkFreq == 0 || ClockFreq == 0) {
799 return EFI_INVALID_PARAMETER;
800 }
801
802 if (ClockFreq > (BaseClkFreq * 1000)) {
803 ClockFreq = BaseClkFreq * 1000;
804 }
805
806 //
807 // Calculate the divisor of base frequency.
808 //
809 Divisor = 0;
810 SettingFreq = BaseClkFreq * 1000;
811 while (ClockFreq < SettingFreq) {
812 Divisor++;
813
814 SettingFreq = (BaseClkFreq * 1000) / (2 * Divisor);
815 Remainder = (BaseClkFreq * 1000) % (2 * Divisor);
816 if ((ClockFreq == SettingFreq) && (Remainder == 0)) {
817 break;
818 }
819 if ((ClockFreq == SettingFreq) && (Remainder != 0)) {
820 SettingFreq ++;
821 }
822 }
823
824 DEBUG ((DEBUG_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq, Divisor, ClockFreq));
825
826 //
827 // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.
828 //
829 if ((ControllerVer >= SD_MMC_HC_CTRL_VER_300) &&
830 (ControllerVer <= SD_MMC_HC_CTRL_VER_420)) {
831 ASSERT (Divisor <= 0x3FF);
832 ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);
833 } else if ((ControllerVer == SD_MMC_HC_CTRL_VER_100) ||
834 (ControllerVer == SD_MMC_HC_CTRL_VER_200)) {
835 //
836 // Only the most significant bit can be used as divisor.
837 //
838 if (((Divisor - 1) & Divisor) != 0) {
839 Divisor = 1 << (HighBitSet32 (Divisor) + 1);
840 }
841 ASSERT (Divisor <= 0x80);
842 ClockCtrl = (Divisor & 0xFF) << 8;
843 } else {
844 DEBUG ((DEBUG_ERROR, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer));
845 return EFI_UNSUPPORTED;
846 }
847
848 //
849 // Stop bus clock at first
850 //
851 Status = SdMmcHcStopClock (PciIo, Slot);
852 if (EFI_ERROR (Status)) {
853 return Status;
854 }
855
856 //
857 // Supply clock frequency with specified divisor
858 //
859 ClockCtrl |= BIT0;
860 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);
861 if (EFI_ERROR (Status)) {
862 DEBUG ((DEBUG_ERROR, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));
863 return Status;
864 }
865
866 //
867 // Wait Internal Clock Stable in the Clock Control register to be 1
868 //
869 Status = SdMmcHcWaitMmioSet (
870 PciIo,
871 Slot,
872 SD_MMC_HC_CLOCK_CTRL,
873 sizeof (ClockCtrl),
874 BIT1,
875 BIT1,
876 SD_MMC_HC_GENERIC_TIMEOUT
877 );
878 if (EFI_ERROR (Status)) {
879 return Status;
880 }
881
882 //
883 // Set SD Clock Enable in the Clock Control register to 1
884 //
885 ClockCtrl = BIT2;
886 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
887
888 //
889 // We don't notify the platform on first time setup to avoid changing
890 // legacy behavior. During first time setup we also don't know what type
891 // of the card slot it is and which enum value of BusTiming applies.
892 //
893 if (!FirstTimeSetup && mOverride != NULL && mOverride->NotifyPhase != NULL) {
894 Status = mOverride->NotifyPhase (
895 Private->ControllerHandle,
896 Slot,
897 EdkiiSdMmcSwitchClockFreqPost,
898 &BusTiming
899 );
900 if (EFI_ERROR (Status)) {
901 DEBUG ((
902 DEBUG_ERROR,
903 "%a: SD/MMC switch clock freq post notifier callback failed - %r\n",
904 __FUNCTION__,
905 Status
906 ));
907 return Status;
908 }
909 }
910
911 return Status;
912 }
913
914 /**
915 SD/MMC bus power control.
916
917 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
918
919 @param[in] PciIo The PCI IO protocol instance.
920 @param[in] Slot The slot number of the SD card to send the command to.
921 @param[in] PowerCtrl The value setting to the power control register.
922
923 @retval TRUE There is a SD/MMC card attached.
924 @retval FALSE There is no a SD/MMC card attached.
925
926 **/
927 EFI_STATUS
928 SdMmcHcPowerControl (
929 IN EFI_PCI_IO_PROTOCOL *PciIo,
930 IN UINT8 Slot,
931 IN UINT8 PowerCtrl
932 )
933 {
934 EFI_STATUS Status;
935
936 //
937 // Clr SD Bus Power
938 //
939 PowerCtrl &= (UINT8)~BIT0;
940 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
941 if (EFI_ERROR (Status)) {
942 return Status;
943 }
944
945 //
946 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
947 //
948 PowerCtrl |= BIT0;
949 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
950
951 return Status;
952 }
953
954 /**
955 Set the SD/MMC bus width.
956
957 Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
958
959 @param[in] PciIo The PCI IO protocol instance.
960 @param[in] Slot The slot number of the SD card to send the command to.
961 @param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.
962
963 @retval EFI_SUCCESS The bus width is set successfully.
964 @retval Others The bus width isn't set successfully.
965
966 **/
967 EFI_STATUS
968 SdMmcHcSetBusWidth (
969 IN EFI_PCI_IO_PROTOCOL *PciIo,
970 IN UINT8 Slot,
971 IN UINT16 BusWidth
972 )
973 {
974 EFI_STATUS Status;
975 UINT8 HostCtrl1;
976
977 if (BusWidth == 1) {
978 HostCtrl1 = (UINT8)~(BIT5 | BIT1);
979 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
980 } else if (BusWidth == 4) {
981 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
982 if (EFI_ERROR (Status)) {
983 return Status;
984 }
985 HostCtrl1 |= BIT1;
986 HostCtrl1 &= (UINT8)~BIT5;
987 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
988 } else if (BusWidth == 8) {
989 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
990 if (EFI_ERROR (Status)) {
991 return Status;
992 }
993 HostCtrl1 &= (UINT8)~BIT1;
994 HostCtrl1 |= BIT5;
995 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
996 } else {
997 ASSERT (FALSE);
998 return EFI_INVALID_PARAMETER;
999 }
1000
1001 return Status;
1002 }
1003
1004 /**
1005 Configure V4 controller enhancements at initialization.
1006
1007 @param[in] PciIo The PCI IO protocol instance.
1008 @param[in] Slot The slot number of the SD card to send the command to.
1009 @param[in] Capability The capability of the slot.
1010 @param[in] ControllerVer The version of host controller.
1011
1012 @retval EFI_SUCCESS The clock is supplied successfully.
1013
1014 **/
1015 EFI_STATUS
1016 SdMmcHcInitV4Enhancements (
1017 IN EFI_PCI_IO_PROTOCOL *PciIo,
1018 IN UINT8 Slot,
1019 IN SD_MMC_HC_SLOT_CAP Capability,
1020 IN UINT16 ControllerVer
1021 )
1022 {
1023 EFI_STATUS Status;
1024 UINT16 HostCtrl2;
1025
1026 //
1027 // Check if controller version V4 or higher
1028 //
1029 if (ControllerVer >= SD_MMC_HC_CTRL_VER_400) {
1030 HostCtrl2 = SD_MMC_HC_V4_EN;
1031 //
1032 // Check if controller version V4.0
1033 //
1034 if (ControllerVer == SD_MMC_HC_CTRL_VER_400) {
1035 //
1036 // Check if 64bit support is available
1037 //
1038 if (Capability.SysBus64V3 != 0) {
1039 HostCtrl2 |= SD_MMC_HC_64_ADDR_EN;
1040 DEBUG ((DEBUG_INFO, "Enabled V4 64 bit system bus support\n"));
1041 }
1042 }
1043 //
1044 // Check if controller version V4.10 or higher
1045 //
1046 else if (ControllerVer >= SD_MMC_HC_CTRL_VER_410) {
1047 //
1048 // Check if 64bit support is available
1049 //
1050 if (Capability.SysBus64V4 != 0) {
1051 HostCtrl2 |= SD_MMC_HC_64_ADDR_EN;
1052 DEBUG ((DEBUG_INFO, "Enabled V4 64 bit system bus support\n"));
1053 }
1054 HostCtrl2 |= SD_MMC_HC_26_DATA_LEN_ADMA_EN;
1055 DEBUG ((DEBUG_INFO, "Enabled V4 26 bit data length ADMA support\n"));
1056 }
1057 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1058 if (EFI_ERROR (Status)) {
1059 return Status;
1060 }
1061 }
1062
1063 return EFI_SUCCESS;
1064 }
1065
1066 /**
1067 Supply SD/MMC card with maximum voltage at initialization.
1068
1069 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
1070
1071 @param[in] PciIo The PCI IO protocol instance.
1072 @param[in] Slot The slot number of the SD card to send the command to.
1073 @param[in] Capability The capability of the slot.
1074
1075 @retval EFI_SUCCESS The voltage is supplied successfully.
1076 @retval Others The voltage isn't supplied successfully.
1077
1078 **/
1079 EFI_STATUS
1080 SdMmcHcInitPowerVoltage (
1081 IN EFI_PCI_IO_PROTOCOL *PciIo,
1082 IN UINT8 Slot,
1083 IN SD_MMC_HC_SLOT_CAP Capability
1084 )
1085 {
1086 EFI_STATUS Status;
1087 UINT8 MaxVoltage;
1088 UINT8 HostCtrl2;
1089
1090 //
1091 // Calculate supported maximum voltage according to SD Bus Voltage Select
1092 //
1093 if (Capability.Voltage33 != 0) {
1094 //
1095 // Support 3.3V
1096 //
1097 MaxVoltage = 0x0E;
1098 } else if (Capability.Voltage30 != 0) {
1099 //
1100 // Support 3.0V
1101 //
1102 MaxVoltage = 0x0C;
1103 } else if (Capability.Voltage18 != 0) {
1104 //
1105 // Support 1.8V
1106 //
1107 MaxVoltage = 0x0A;
1108 HostCtrl2 = BIT3;
1109 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1110 gBS->Stall (5000);
1111 if (EFI_ERROR (Status)) {
1112 return Status;
1113 }
1114 } else {
1115 ASSERT (FALSE);
1116 return EFI_DEVICE_ERROR;
1117 }
1118
1119 //
1120 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
1121 //
1122 Status = SdMmcHcPowerControl (PciIo, Slot, MaxVoltage);
1123
1124 return Status;
1125 }
1126
1127 /**
1128 Initialize the Timeout Control register with most conservative value at initialization.
1129
1130 Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
1131
1132 @param[in] PciIo The PCI IO protocol instance.
1133 @param[in] Slot The slot number of the SD card to send the command to.
1134
1135 @retval EFI_SUCCESS The timeout control register is configured successfully.
1136 @retval Others The timeout control register isn't configured successfully.
1137
1138 **/
1139 EFI_STATUS
1140 SdMmcHcInitTimeoutCtrl (
1141 IN EFI_PCI_IO_PROTOCOL *PciIo,
1142 IN UINT8 Slot
1143 )
1144 {
1145 EFI_STATUS Status;
1146 UINT8 Timeout;
1147
1148 Timeout = 0x0E;
1149 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_TIMEOUT_CTRL, FALSE, sizeof (Timeout), &Timeout);
1150
1151 return Status;
1152 }
1153
1154 /**
1155 Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value
1156 at initialization.
1157
1158 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1159 @param[in] Slot The slot number of the SD card to send the command to.
1160
1161 @retval EFI_SUCCESS The host controller is initialized successfully.
1162 @retval Others The host controller isn't initialized successfully.
1163
1164 **/
1165 EFI_STATUS
1166 SdMmcHcInitHost (
1167 IN SD_MMC_HC_PRIVATE_DATA *Private,
1168 IN UINT8 Slot
1169 )
1170 {
1171 EFI_STATUS Status;
1172 EFI_PCI_IO_PROTOCOL *PciIo;
1173 SD_MMC_HC_SLOT_CAP Capability;
1174
1175 //
1176 // Notify the SD/MMC override protocol that we are about to initialize
1177 // the SD/MMC host controller.
1178 //
1179 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
1180 Status = mOverride->NotifyPhase (
1181 Private->ControllerHandle,
1182 Slot,
1183 EdkiiSdMmcInitHostPre,
1184 NULL);
1185 if (EFI_ERROR (Status)) {
1186 DEBUG ((DEBUG_WARN,
1187 "%a: SD/MMC pre init notifier callback failed - %r\n",
1188 __FUNCTION__, Status));
1189 return Status;
1190 }
1191 }
1192
1193 PciIo = Private->PciIo;
1194 Capability = Private->Capability[Slot];
1195
1196 Status = SdMmcHcInitV4Enhancements (PciIo, Slot, Capability, Private->ControllerVersion[Slot]);
1197 if (EFI_ERROR (Status)) {
1198 return Status;
1199 }
1200
1201 //
1202 // Perform first time clock setup with 400 KHz frequency.
1203 // We send the 0 as the BusTiming value because at this time
1204 // we still do not know the slot type and which enum value will apply.
1205 // Since it is a first time setup SdMmcHcClockSupply won't notify
1206 // the platofrm driver anyway so it doesn't matter.
1207 //
1208 Status = SdMmcHcClockSupply (Private, Slot, 0, TRUE, 400);
1209 if (EFI_ERROR (Status)) {
1210 return Status;
1211 }
1212
1213 Status = SdMmcHcInitPowerVoltage (PciIo, Slot, Capability);
1214 if (EFI_ERROR (Status)) {
1215 return Status;
1216 }
1217
1218 Status = SdMmcHcInitTimeoutCtrl (PciIo, Slot);
1219 if (EFI_ERROR (Status)) {
1220 return Status;
1221 }
1222
1223 //
1224 // Notify the SD/MMC override protocol that we are have just initialized
1225 // the SD/MMC host controller.
1226 //
1227 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
1228 Status = mOverride->NotifyPhase (
1229 Private->ControllerHandle,
1230 Slot,
1231 EdkiiSdMmcInitHostPost,
1232 NULL);
1233 if (EFI_ERROR (Status)) {
1234 DEBUG ((DEBUG_WARN,
1235 "%a: SD/MMC post init notifier callback failed - %r\n",
1236 __FUNCTION__, Status));
1237 }
1238 }
1239 return Status;
1240 }
1241
1242 /**
1243 Set SD Host Controler control 2 registry according to selected speed.
1244
1245 @param[in] ControllerHandle The handle of the controller.
1246 @param[in] PciIo The PCI IO protocol instance.
1247 @param[in] Slot The slot number of the SD card to send the command to.
1248 @param[in] Timing The timing to select.
1249
1250 @retval EFI_SUCCESS The timing is set successfully.
1251 @retval Others The timing isn't set successfully.
1252 **/
1253 EFI_STATUS
1254 SdMmcHcUhsSignaling (
1255 IN EFI_HANDLE ControllerHandle,
1256 IN EFI_PCI_IO_PROTOCOL *PciIo,
1257 IN UINT8 Slot,
1258 IN SD_MMC_BUS_MODE Timing
1259 )
1260 {
1261 EFI_STATUS Status;
1262 UINT8 HostCtrl2;
1263
1264 HostCtrl2 = (UINT8)~SD_MMC_HC_CTRL_UHS_MASK;
1265 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1266 if (EFI_ERROR (Status)) {
1267 return Status;
1268 }
1269
1270 switch (Timing) {
1271 case SdMmcUhsSdr12:
1272 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR12;
1273 break;
1274 case SdMmcUhsSdr25:
1275 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR25;
1276 break;
1277 case SdMmcUhsSdr50:
1278 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR50;
1279 break;
1280 case SdMmcUhsSdr104:
1281 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR104;
1282 break;
1283 case SdMmcUhsDdr50:
1284 HostCtrl2 = SD_MMC_HC_CTRL_UHS_DDR50;
1285 break;
1286 case SdMmcMmcLegacy:
1287 HostCtrl2 = SD_MMC_HC_CTRL_MMC_LEGACY;
1288 break;
1289 case SdMmcMmcHsSdr:
1290 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_SDR;
1291 break;
1292 case SdMmcMmcHsDdr:
1293 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_DDR;
1294 break;
1295 case SdMmcMmcHs200:
1296 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS200;
1297 break;
1298 case SdMmcMmcHs400:
1299 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS400;
1300 break;
1301 default:
1302 HostCtrl2 = 0;
1303 break;
1304 }
1305 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1306 if (EFI_ERROR (Status)) {
1307 return Status;
1308 }
1309
1310 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
1311 Status = mOverride->NotifyPhase (
1312 ControllerHandle,
1313 Slot,
1314 EdkiiSdMmcUhsSignaling,
1315 &Timing
1316 );
1317 if (EFI_ERROR (Status)) {
1318 DEBUG ((
1319 DEBUG_ERROR,
1320 "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
1321 __FUNCTION__,
1322 Status
1323 ));
1324 return Status;
1325 }
1326 }
1327
1328 return EFI_SUCCESS;
1329 }
1330
1331 /**
1332 Set driver strength in host controller.
1333
1334 @param[in] PciIo The PCI IO protocol instance.
1335 @param[in] SlotIndex The slot index of the card.
1336 @param[in] DriverStrength DriverStrength to set in the controller.
1337
1338 @retval EFI_SUCCESS Driver strength programmed successfully.
1339 @retval Others Failed to set driver strength.
1340 **/
1341 EFI_STATUS
1342 SdMmcSetDriverStrength (
1343 IN EFI_PCI_IO_PROTOCOL *PciIo,
1344 IN UINT8 SlotIndex,
1345 IN SD_DRIVER_STRENGTH_TYPE DriverStrength
1346 )
1347 {
1348 EFI_STATUS Status;
1349 UINT16 HostCtrl2;
1350
1351 if (DriverStrength == SdDriverStrengthIgnore) {
1352 return EFI_SUCCESS;
1353 }
1354
1355 HostCtrl2 = (UINT16)~SD_MMC_HC_CTRL_DRIVER_STRENGTH_MASK;
1356 Status = SdMmcHcAndMmio (PciIo, SlotIndex, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1357 if (EFI_ERROR (Status)) {
1358 return Status;
1359 }
1360
1361 HostCtrl2 = (DriverStrength << 4) & SD_MMC_HC_CTRL_DRIVER_STRENGTH_MASK;
1362 return SdMmcHcOrMmio (PciIo, SlotIndex, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1363 }
1364
1365 /**
1366 Turn on/off LED.
1367
1368 @param[in] PciIo The PCI IO protocol instance.
1369 @param[in] Slot The slot number of the SD card to send the command to.
1370 @param[in] On The boolean to turn on/off LED.
1371
1372 @retval EFI_SUCCESS The LED is turned on/off successfully.
1373 @retval Others The LED isn't turned on/off successfully.
1374
1375 **/
1376 EFI_STATUS
1377 SdMmcHcLedOnOff (
1378 IN EFI_PCI_IO_PROTOCOL *PciIo,
1379 IN UINT8 Slot,
1380 IN BOOLEAN On
1381 )
1382 {
1383 EFI_STATUS Status;
1384 UINT8 HostCtrl1;
1385
1386 if (On) {
1387 HostCtrl1 = BIT0;
1388 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1389 } else {
1390 HostCtrl1 = (UINT8)~BIT0;
1391 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1392 }
1393
1394 return Status;
1395 }
1396
1397 /**
1398 Build ADMA descriptor table for transfer.
1399
1400 Refer to SD Host Controller Simplified spec 4.2 Section 1.13 for details.
1401
1402 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1403 @param[in] ControllerVer The version of host controller.
1404
1405 @retval EFI_SUCCESS The ADMA descriptor table is created successfully.
1406 @retval Others The ADMA descriptor table isn't created successfully.
1407
1408 **/
1409 EFI_STATUS
1410 BuildAdmaDescTable (
1411 IN SD_MMC_HC_TRB *Trb,
1412 IN UINT16 ControllerVer
1413 )
1414 {
1415 EFI_PHYSICAL_ADDRESS Data;
1416 UINT64 DataLen;
1417 UINT64 Entries;
1418 UINT32 Index;
1419 UINT64 Remaining;
1420 UINT64 Address;
1421 UINTN TableSize;
1422 EFI_PCI_IO_PROTOCOL *PciIo;
1423 EFI_STATUS Status;
1424 UINTN Bytes;
1425 UINT32 AdmaMaxDataPerLine;
1426 UINT32 DescSize;
1427 VOID *AdmaDesc;
1428
1429 AdmaMaxDataPerLine = ADMA_MAX_DATA_PER_LINE_16B;
1430 DescSize = sizeof (SD_MMC_HC_ADMA_32_DESC_LINE);
1431 AdmaDesc = NULL;
1432
1433 Data = Trb->DataPhy;
1434 DataLen = Trb->DataLen;
1435 PciIo = Trb->Private->PciIo;
1436
1437 //
1438 // Check for valid ranges in 32bit ADMA Descriptor Table
1439 //
1440 if ((Trb->Mode == SdMmcAdma32bMode) &&
1441 ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul))) {
1442 return EFI_INVALID_PARAMETER;
1443 }
1444 //
1445 // Check address field alignment
1446 //
1447 if (Trb->Mode != SdMmcAdma32bMode) {
1448 //
1449 // Address field shall be set on 64-bit boundary (Lower 3-bit is always set to 0)
1450 //
1451 if ((Data & (BIT0 | BIT1 | BIT2)) != 0) {
1452 DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 8 bytes boundary!\n", Data));
1453 }
1454 } else {
1455 //
1456 // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)
1457 //
1458 if ((Data & (BIT0 | BIT1)) != 0) {
1459 DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data));
1460 }
1461 }
1462
1463 //
1464 // Configure 64b ADMA.
1465 //
1466 if (Trb->Mode == SdMmcAdma64bV3Mode) {
1467 DescSize = sizeof (SD_MMC_HC_ADMA_64_V3_DESC_LINE);
1468 }else if (Trb->Mode == SdMmcAdma64bV4Mode) {
1469 DescSize = sizeof (SD_MMC_HC_ADMA_64_V4_DESC_LINE);
1470 }
1471 //
1472 // Configure 26b data length.
1473 //
1474 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1475 AdmaMaxDataPerLine = ADMA_MAX_DATA_PER_LINE_26B;
1476 }
1477
1478 Entries = DivU64x32 ((DataLen + AdmaMaxDataPerLine - 1), AdmaMaxDataPerLine);
1479 TableSize = (UINTN)MultU64x32 (Entries, DescSize);
1480 Trb->AdmaPages = (UINT32)EFI_SIZE_TO_PAGES (TableSize);
1481 Status = PciIo->AllocateBuffer (
1482 PciIo,
1483 AllocateAnyPages,
1484 EfiBootServicesData,
1485 EFI_SIZE_TO_PAGES (TableSize),
1486 (VOID **)&AdmaDesc,
1487 0
1488 );
1489 if (EFI_ERROR (Status)) {
1490 return EFI_OUT_OF_RESOURCES;
1491 }
1492 ZeroMem (AdmaDesc, TableSize);
1493 Bytes = TableSize;
1494 Status = PciIo->Map (
1495 PciIo,
1496 EfiPciIoOperationBusMasterCommonBuffer,
1497 AdmaDesc,
1498 &Bytes,
1499 &Trb->AdmaDescPhy,
1500 &Trb->AdmaMap
1501 );
1502
1503 if (EFI_ERROR (Status) || (Bytes != TableSize)) {
1504 //
1505 // Map error or unable to map the whole RFis buffer into a contiguous region.
1506 //
1507 PciIo->FreeBuffer (
1508 PciIo,
1509 EFI_SIZE_TO_PAGES (TableSize),
1510 AdmaDesc
1511 );
1512 return EFI_OUT_OF_RESOURCES;
1513 }
1514
1515 if ((Trb->Mode == SdMmcAdma32bMode) &&
1516 (UINT64)(UINTN)Trb->AdmaDescPhy > 0x100000000ul) {
1517 //
1518 // The ADMA doesn't support 64bit addressing.
1519 //
1520 PciIo->Unmap (
1521 PciIo,
1522 Trb->AdmaMap
1523 );
1524 PciIo->FreeBuffer (
1525 PciIo,
1526 EFI_SIZE_TO_PAGES (TableSize),
1527 AdmaDesc
1528 );
1529 return EFI_DEVICE_ERROR;
1530 }
1531
1532 Remaining = DataLen;
1533 Address = Data;
1534 if (Trb->Mode == SdMmcAdma32bMode) {
1535 Trb->Adma32Desc = AdmaDesc;
1536 } else if (Trb->Mode == SdMmcAdma64bV3Mode) {
1537 Trb->Adma64V3Desc = AdmaDesc;
1538 } else {
1539 Trb->Adma64V4Desc = AdmaDesc;
1540 }
1541
1542 for (Index = 0; Index < Entries; Index++) {
1543 if (Trb->Mode == SdMmcAdma32bMode) {
1544 if (Remaining <= AdmaMaxDataPerLine) {
1545 Trb->Adma32Desc[Index].Valid = 1;
1546 Trb->Adma32Desc[Index].Act = 2;
1547 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1548 Trb->Adma32Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);
1549 }
1550 Trb->Adma32Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);
1551 Trb->Adma32Desc[Index].Address = (UINT32)Address;
1552 break;
1553 } else {
1554 Trb->Adma32Desc[Index].Valid = 1;
1555 Trb->Adma32Desc[Index].Act = 2;
1556 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1557 Trb->Adma32Desc[Index].UpperLength = 0;
1558 }
1559 Trb->Adma32Desc[Index].LowerLength = 0;
1560 Trb->Adma32Desc[Index].Address = (UINT32)Address;
1561 }
1562 } else if (Trb->Mode == SdMmcAdma64bV3Mode) {
1563 if (Remaining <= AdmaMaxDataPerLine) {
1564 Trb->Adma64V3Desc[Index].Valid = 1;
1565 Trb->Adma64V3Desc[Index].Act = 2;
1566 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1567 Trb->Adma64V3Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);
1568 }
1569 Trb->Adma64V3Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);
1570 Trb->Adma64V3Desc[Index].LowerAddress = (UINT32)Address;
1571 Trb->Adma64V3Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);
1572 break;
1573 } else {
1574 Trb->Adma64V3Desc[Index].Valid = 1;
1575 Trb->Adma64V3Desc[Index].Act = 2;
1576 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1577 Trb->Adma64V3Desc[Index].UpperLength = 0;
1578 }
1579 Trb->Adma64V3Desc[Index].LowerLength = 0;
1580 Trb->Adma64V3Desc[Index].LowerAddress = (UINT32)Address;
1581 Trb->Adma64V3Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);
1582 }
1583 } else {
1584 if (Remaining <= AdmaMaxDataPerLine) {
1585 Trb->Adma64V4Desc[Index].Valid = 1;
1586 Trb->Adma64V4Desc[Index].Act = 2;
1587 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1588 Trb->Adma64V4Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);
1589 }
1590 Trb->Adma64V4Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);
1591 Trb->Adma64V4Desc[Index].LowerAddress = (UINT32)Address;
1592 Trb->Adma64V4Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);
1593 break;
1594 } else {
1595 Trb->Adma64V4Desc[Index].Valid = 1;
1596 Trb->Adma64V4Desc[Index].Act = 2;
1597 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1598 Trb->Adma64V4Desc[Index].UpperLength = 0;
1599 }
1600 Trb->Adma64V4Desc[Index].LowerLength = 0;
1601 Trb->Adma64V4Desc[Index].LowerAddress = (UINT32)Address;
1602 Trb->Adma64V4Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);
1603 }
1604 }
1605
1606 Remaining -= AdmaMaxDataPerLine;
1607 Address += AdmaMaxDataPerLine;
1608 }
1609
1610 //
1611 // Set the last descriptor line as end of descriptor table
1612 //
1613 if (Trb->Mode == SdMmcAdma32bMode) {
1614 Trb->Adma32Desc[Index].End = 1;
1615 } else if (Trb->Mode == SdMmcAdma64bV3Mode) {
1616 Trb->Adma64V3Desc[Index].End = 1;
1617 } else {
1618 Trb->Adma64V4Desc[Index].End = 1;
1619 }
1620 return EFI_SUCCESS;
1621 }
1622
1623 /**
1624 Create a new TRB for the SD/MMC cmd request.
1625
1626 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1627 @param[in] Slot The slot number of the SD card to send the command to.
1628 @param[in] Packet A pointer to the SD command data structure.
1629 @param[in] Event If Event is NULL, blocking I/O is performed. If Event is
1630 not NULL, then nonblocking I/O is performed, and Event
1631 will be signaled when the Packet completes.
1632
1633 @return Created Trb or NULL.
1634
1635 **/
1636 SD_MMC_HC_TRB *
1637 SdMmcCreateTrb (
1638 IN SD_MMC_HC_PRIVATE_DATA *Private,
1639 IN UINT8 Slot,
1640 IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
1641 IN EFI_EVENT Event
1642 )
1643 {
1644 SD_MMC_HC_TRB *Trb;
1645 EFI_STATUS Status;
1646 EFI_TPL OldTpl;
1647 EFI_PCI_IO_PROTOCOL_OPERATION Flag;
1648 EFI_PCI_IO_PROTOCOL *PciIo;
1649 UINTN MapLength;
1650
1651 Trb = AllocateZeroPool (sizeof (SD_MMC_HC_TRB));
1652 if (Trb == NULL) {
1653 return NULL;
1654 }
1655
1656 Trb->Signature = SD_MMC_HC_TRB_SIG;
1657 Trb->Slot = Slot;
1658 Trb->BlockSize = 0x200;
1659 Trb->Packet = Packet;
1660 Trb->Event = Event;
1661 Trb->Started = FALSE;
1662 Trb->Timeout = Packet->Timeout;
1663 Trb->Private = Private;
1664
1665 if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {
1666 Trb->Data = Packet->InDataBuffer;
1667 Trb->DataLen = Packet->InTransferLength;
1668 Trb->Read = TRUE;
1669 } else if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {
1670 Trb->Data = Packet->OutDataBuffer;
1671 Trb->DataLen = Packet->OutTransferLength;
1672 Trb->Read = FALSE;
1673 } else if ((Packet->InTransferLength == 0) && (Packet->OutTransferLength == 0)) {
1674 Trb->Data = NULL;
1675 Trb->DataLen = 0;
1676 } else {
1677 goto Error;
1678 }
1679
1680 if ((Trb->DataLen != 0) && (Trb->DataLen < Trb->BlockSize)) {
1681 Trb->BlockSize = (UINT16)Trb->DataLen;
1682 }
1683
1684 if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
1685 (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
1686 ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
1687 (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
1688 Trb->Mode = SdMmcPioMode;
1689 } else {
1690 if (Trb->Read) {
1691 Flag = EfiPciIoOperationBusMasterWrite;
1692 } else {
1693 Flag = EfiPciIoOperationBusMasterRead;
1694 }
1695
1696 PciIo = Private->PciIo;
1697 if (Trb->DataLen != 0) {
1698 MapLength = Trb->DataLen;
1699 Status = PciIo->Map (
1700 PciIo,
1701 Flag,
1702 Trb->Data,
1703 &MapLength,
1704 &Trb->DataPhy,
1705 &Trb->DataMap
1706 );
1707 if (EFI_ERROR (Status) || (Trb->DataLen != MapLength)) {
1708 Status = EFI_BAD_BUFFER_SIZE;
1709 goto Error;
1710 }
1711 }
1712
1713 if (Trb->DataLen == 0) {
1714 Trb->Mode = SdMmcNoData;
1715 } else if (Private->Capability[Slot].Adma2 != 0) {
1716 Trb->Mode = SdMmcAdma32bMode;
1717 Trb->AdmaLengthMode = SdMmcAdmaLen16b;
1718 if ((Private->ControllerVersion[Slot] == SD_MMC_HC_CTRL_VER_300) &&
1719 (Private->Capability[Slot].SysBus64V3 == 1)) {
1720 Trb->Mode = SdMmcAdma64bV3Mode;
1721 } else if (((Private->ControllerVersion[Slot] == SD_MMC_HC_CTRL_VER_400) &&
1722 (Private->Capability[Slot].SysBus64V3 == 1)) ||
1723 ((Private->ControllerVersion[Slot] >= SD_MMC_HC_CTRL_VER_410) &&
1724 (Private->Capability[Slot].SysBus64V4 == 1))) {
1725 Trb->Mode = SdMmcAdma64bV4Mode;
1726 }
1727 if (Private->ControllerVersion[Slot] >= SD_MMC_HC_CTRL_VER_410) {
1728 Trb->AdmaLengthMode = SdMmcAdmaLen26b;
1729 }
1730 Status = BuildAdmaDescTable (Trb, Private->ControllerVersion[Slot]);
1731 if (EFI_ERROR (Status)) {
1732 PciIo->Unmap (PciIo, Trb->DataMap);
1733 goto Error;
1734 }
1735 } else if (Private->Capability[Slot].Sdma != 0) {
1736 Trb->Mode = SdMmcSdmaMode;
1737 } else {
1738 Trb->Mode = SdMmcPioMode;
1739 }
1740 }
1741
1742 if (Event != NULL) {
1743 OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
1744 InsertTailList (&Private->Queue, &Trb->TrbList);
1745 gBS->RestoreTPL (OldTpl);
1746 }
1747
1748 return Trb;
1749
1750 Error:
1751 SdMmcFreeTrb (Trb);
1752 return NULL;
1753 }
1754
1755 /**
1756 Free the resource used by the TRB.
1757
1758 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1759
1760 **/
1761 VOID
1762 SdMmcFreeTrb (
1763 IN SD_MMC_HC_TRB *Trb
1764 )
1765 {
1766 EFI_PCI_IO_PROTOCOL *PciIo;
1767
1768 PciIo = Trb->Private->PciIo;
1769
1770 if (Trb->AdmaMap != NULL) {
1771 PciIo->Unmap (
1772 PciIo,
1773 Trb->AdmaMap
1774 );
1775 }
1776 if (Trb->Adma32Desc != NULL) {
1777 PciIo->FreeBuffer (
1778 PciIo,
1779 Trb->AdmaPages,
1780 Trb->Adma32Desc
1781 );
1782 }
1783 if (Trb->Adma64V3Desc != NULL) {
1784 PciIo->FreeBuffer (
1785 PciIo,
1786 Trb->AdmaPages,
1787 Trb->Adma64V3Desc
1788 );
1789 }
1790 if (Trb->Adma64V4Desc != NULL) {
1791 PciIo->FreeBuffer (
1792 PciIo,
1793 Trb->AdmaPages,
1794 Trb->Adma64V4Desc
1795 );
1796 }
1797 if (Trb->DataMap != NULL) {
1798 PciIo->Unmap (
1799 PciIo,
1800 Trb->DataMap
1801 );
1802 }
1803 FreePool (Trb);
1804 return;
1805 }
1806
1807 /**
1808 Check if the env is ready for execute specified TRB.
1809
1810 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1811 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1812
1813 @retval EFI_SUCCESS The env is ready for TRB execution.
1814 @retval EFI_NOT_READY The env is not ready for TRB execution.
1815 @retval Others Some erros happen.
1816
1817 **/
1818 EFI_STATUS
1819 SdMmcCheckTrbEnv (
1820 IN SD_MMC_HC_PRIVATE_DATA *Private,
1821 IN SD_MMC_HC_TRB *Trb
1822 )
1823 {
1824 EFI_STATUS Status;
1825 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1826 EFI_PCI_IO_PROTOCOL *PciIo;
1827 UINT32 PresentState;
1828
1829 Packet = Trb->Packet;
1830
1831 if ((Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) ||
1832 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b) ||
1833 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b)) {
1834 //
1835 // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in
1836 // the Present State register to be 0
1837 //
1838 PresentState = BIT0 | BIT1;
1839 } else {
1840 //
1841 // Wait Command Inhibit (CMD) in the Present State register
1842 // to be 0
1843 //
1844 PresentState = BIT0;
1845 }
1846
1847 PciIo = Private->PciIo;
1848 Status = SdMmcHcCheckMmioSet (
1849 PciIo,
1850 Trb->Slot,
1851 SD_MMC_HC_PRESENT_STATE,
1852 sizeof (PresentState),
1853 PresentState,
1854 0
1855 );
1856
1857 return Status;
1858 }
1859
1860 /**
1861 Wait for the env to be ready for execute specified TRB.
1862
1863 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1864 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1865
1866 @retval EFI_SUCCESS The env is ready for TRB execution.
1867 @retval EFI_TIMEOUT The env is not ready for TRB execution in time.
1868 @retval Others Some erros happen.
1869
1870 **/
1871 EFI_STATUS
1872 SdMmcWaitTrbEnv (
1873 IN SD_MMC_HC_PRIVATE_DATA *Private,
1874 IN SD_MMC_HC_TRB *Trb
1875 )
1876 {
1877 EFI_STATUS Status;
1878 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1879 UINT64 Timeout;
1880 BOOLEAN InfiniteWait;
1881
1882 //
1883 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1884 //
1885 Packet = Trb->Packet;
1886 Timeout = Packet->Timeout;
1887 if (Timeout == 0) {
1888 InfiniteWait = TRUE;
1889 } else {
1890 InfiniteWait = FALSE;
1891 }
1892
1893 while (InfiniteWait || (Timeout > 0)) {
1894 //
1895 // Check Trb execution result by reading Normal Interrupt Status register.
1896 //
1897 Status = SdMmcCheckTrbEnv (Private, Trb);
1898 if (Status != EFI_NOT_READY) {
1899 return Status;
1900 }
1901 //
1902 // Stall for 1 microsecond.
1903 //
1904 gBS->Stall (1);
1905
1906 Timeout--;
1907 }
1908
1909 return EFI_TIMEOUT;
1910 }
1911
1912 /**
1913 Execute the specified TRB.
1914
1915 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1916 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1917
1918 @retval EFI_SUCCESS The TRB is sent to host controller successfully.
1919 @retval Others Some erros happen when sending this request to the host controller.
1920
1921 **/
1922 EFI_STATUS
1923 SdMmcExecTrb (
1924 IN SD_MMC_HC_PRIVATE_DATA *Private,
1925 IN SD_MMC_HC_TRB *Trb
1926 )
1927 {
1928 EFI_STATUS Status;
1929 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1930 EFI_PCI_IO_PROTOCOL *PciIo;
1931 UINT16 Cmd;
1932 UINT16 IntStatus;
1933 UINT32 Argument;
1934 UINT32 BlkCount;
1935 UINT16 BlkSize;
1936 UINT16 TransMode;
1937 UINT8 HostCtrl1;
1938 UINT64 SdmaAddr;
1939 UINT64 AdmaAddr;
1940 BOOLEAN AddressingMode64;
1941
1942 AddressingMode64 = FALSE;
1943
1944 Packet = Trb->Packet;
1945 PciIo = Trb->Private->PciIo;
1946 //
1947 // Clear all bits in Error Interrupt Status Register
1948 //
1949 IntStatus = 0xFFFF;
1950 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ERR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1951 if (EFI_ERROR (Status)) {
1952 return Status;
1953 }
1954 //
1955 // Clear all bits in Normal Interrupt Status Register excepts for Card Removal & Card Insertion bits.
1956 //
1957 IntStatus = 0xFF3F;
1958 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1959 if (EFI_ERROR (Status)) {
1960 return Status;
1961 }
1962
1963 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {
1964 Status = SdMmcHcCheckMmioSet(PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL2, sizeof(UINT16),
1965 SD_MMC_HC_64_ADDR_EN, SD_MMC_HC_64_ADDR_EN);
1966 if (!EFI_ERROR (Status)) {
1967 AddressingMode64 = TRUE;
1968 }
1969 }
1970
1971 //
1972 // Set Host Control 1 register DMA Select field
1973 //
1974 if ((Trb->Mode == SdMmcAdma32bMode) ||
1975 (Trb->Mode == SdMmcAdma64bV4Mode)) {
1976 HostCtrl1 = BIT4;
1977 Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1978 if (EFI_ERROR (Status)) {
1979 return Status;
1980 }
1981 } else if (Trb->Mode == SdMmcAdma64bV3Mode) {
1982 HostCtrl1 = BIT4|BIT3;
1983 Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1984 if (EFI_ERROR (Status)) {
1985 return Status;
1986 }
1987 }
1988
1989 SdMmcHcLedOnOff (PciIo, Trb->Slot, TRUE);
1990
1991 if (Trb->Mode == SdMmcSdmaMode) {
1992 if ((!AddressingMode64) &&
1993 ((UINT64)(UINTN)Trb->DataPhy >= 0x100000000ul)) {
1994 return EFI_INVALID_PARAMETER;
1995 }
1996
1997 SdmaAddr = (UINT64)(UINTN)Trb->DataPhy;
1998
1999 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {
2000 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (UINT64), &SdmaAddr);
2001 } else {
2002 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (UINT32), &SdmaAddr);
2003 }
2004
2005 if (EFI_ERROR (Status)) {
2006 return Status;
2007 }
2008 } else if ((Trb->Mode == SdMmcAdma32bMode) ||
2009 (Trb->Mode == SdMmcAdma64bV3Mode) ||
2010 (Trb->Mode == SdMmcAdma64bV4Mode)) {
2011 AdmaAddr = (UINT64)(UINTN)Trb->AdmaDescPhy;
2012 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (AdmaAddr), &AdmaAddr);
2013 if (EFI_ERROR (Status)) {
2014 return Status;
2015 }
2016 }
2017
2018 BlkSize = Trb->BlockSize;
2019 if (Trb->Mode == SdMmcSdmaMode) {
2020 //
2021 // Set SDMA boundary to be 512K bytes.
2022 //
2023 BlkSize |= 0x7000;
2024 }
2025
2026 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_SIZE, FALSE, sizeof (BlkSize), &BlkSize);
2027 if (EFI_ERROR (Status)) {
2028 return Status;
2029 }
2030
2031 BlkCount = 0;
2032 if (Trb->Mode != SdMmcNoData) {
2033 //
2034 // Calcuate Block Count.
2035 //
2036 BlkCount = (Trb->DataLen / Trb->BlockSize);
2037 }
2038 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_410) {
2039 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (UINT32), &BlkCount);
2040 } else {
2041 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_COUNT, FALSE, sizeof (UINT16), &BlkCount);
2042 }
2043 if (EFI_ERROR (Status)) {
2044 return Status;
2045 }
2046
2047 Argument = Packet->SdMmcCmdBlk->CommandArgument;
2048 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ARG1, FALSE, sizeof (Argument), &Argument);
2049 if (EFI_ERROR (Status)) {
2050 return Status;
2051 }
2052
2053 TransMode = 0;
2054 if (Trb->Mode != SdMmcNoData) {
2055 if (Trb->Mode != SdMmcPioMode) {
2056 TransMode |= BIT0;
2057 }
2058 if (Trb->Read) {
2059 TransMode |= BIT4;
2060 }
2061 if (BlkCount > 1) {
2062 TransMode |= BIT5 | BIT1;
2063 }
2064 //
2065 // Only SD memory card needs to use AUTO CMD12 feature.
2066 //
2067 if (Private->Slot[Trb->Slot].CardType == SdCardType) {
2068 if (BlkCount > 1) {
2069 TransMode |= BIT2;
2070 }
2071 }
2072 }
2073
2074 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_TRANS_MOD, FALSE, sizeof (TransMode), &TransMode);
2075 if (EFI_ERROR (Status)) {
2076 return Status;
2077 }
2078
2079 Cmd = (UINT16)LShiftU64(Packet->SdMmcCmdBlk->CommandIndex, 8);
2080 if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) {
2081 Cmd |= BIT5;
2082 }
2083 //
2084 // Convert ResponseType to value
2085 //
2086 if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
2087 switch (Packet->SdMmcCmdBlk->ResponseType) {
2088 case SdMmcResponseTypeR1:
2089 case SdMmcResponseTypeR5:
2090 case SdMmcResponseTypeR6:
2091 case SdMmcResponseTypeR7:
2092 Cmd |= (BIT1 | BIT3 | BIT4);
2093 break;
2094 case SdMmcResponseTypeR2:
2095 Cmd |= (BIT0 | BIT3);
2096 break;
2097 case SdMmcResponseTypeR3:
2098 case SdMmcResponseTypeR4:
2099 Cmd |= BIT1;
2100 break;
2101 case SdMmcResponseTypeR1b:
2102 case SdMmcResponseTypeR5b:
2103 Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);
2104 break;
2105 default:
2106 ASSERT (FALSE);
2107 break;
2108 }
2109 }
2110 //
2111 // Execute cmd
2112 //
2113 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_COMMAND, FALSE, sizeof (Cmd), &Cmd);
2114 return Status;
2115 }
2116
2117 /**
2118 Check the TRB execution result.
2119
2120 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2121 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2122
2123 @retval EFI_SUCCESS The TRB is executed successfully.
2124 @retval EFI_NOT_READY The TRB is not completed for execution.
2125 @retval Others Some erros happen when executing this request.
2126
2127 **/
2128 EFI_STATUS
2129 SdMmcCheckTrbResult (
2130 IN SD_MMC_HC_PRIVATE_DATA *Private,
2131 IN SD_MMC_HC_TRB *Trb
2132 )
2133 {
2134 EFI_STATUS Status;
2135 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
2136 UINT16 IntStatus;
2137 UINT32 Response[4];
2138 UINT64 SdmaAddr;
2139 UINT8 Index;
2140 UINT8 SwReset;
2141 UINT32 PioLength;
2142
2143 SwReset = 0;
2144 Packet = Trb->Packet;
2145 //
2146 // Check Trb execution result by reading Normal Interrupt Status register.
2147 //
2148 Status = SdMmcHcRwMmio (
2149 Private->PciIo,
2150 Trb->Slot,
2151 SD_MMC_HC_NOR_INT_STS,
2152 TRUE,
2153 sizeof (IntStatus),
2154 &IntStatus
2155 );
2156 if (EFI_ERROR (Status)) {
2157 goto Done;
2158 }
2159 //
2160 // Check Transfer Complete bit is set or not.
2161 //
2162 if ((IntStatus & BIT1) == BIT1) {
2163 if ((IntStatus & BIT15) == BIT15) {
2164 //
2165 // Read Error Interrupt Status register to check if the error is
2166 // Data Timeout Error.
2167 // If yes, treat it as success as Transfer Complete has higher
2168 // priority than Data Timeout Error.
2169 //
2170 Status = SdMmcHcRwMmio (
2171 Private->PciIo,
2172 Trb->Slot,
2173 SD_MMC_HC_ERR_INT_STS,
2174 TRUE,
2175 sizeof (IntStatus),
2176 &IntStatus
2177 );
2178 if (!EFI_ERROR (Status)) {
2179 if ((IntStatus & BIT4) == BIT4) {
2180 Status = EFI_SUCCESS;
2181 } else {
2182 Status = EFI_DEVICE_ERROR;
2183 }
2184 }
2185 }
2186
2187 goto Done;
2188 }
2189 //
2190 // Check if there is a error happened during cmd execution.
2191 // If yes, then do error recovery procedure to follow SD Host Controller
2192 // Simplified Spec 3.0 section 3.10.1.
2193 //
2194 if ((IntStatus & BIT15) == BIT15) {
2195 Status = SdMmcHcRwMmio (
2196 Private->PciIo,
2197 Trb->Slot,
2198 SD_MMC_HC_ERR_INT_STS,
2199 TRUE,
2200 sizeof (IntStatus),
2201 &IntStatus
2202 );
2203 if (EFI_ERROR (Status)) {
2204 goto Done;
2205 }
2206 if ((IntStatus & 0x0F) != 0) {
2207 SwReset |= BIT1;
2208 }
2209 if ((IntStatus & 0xF0) != 0) {
2210 SwReset |= BIT2;
2211 }
2212
2213 Status = SdMmcHcRwMmio (
2214 Private->PciIo,
2215 Trb->Slot,
2216 SD_MMC_HC_SW_RST,
2217 FALSE,
2218 sizeof (SwReset),
2219 &SwReset
2220 );
2221 if (EFI_ERROR (Status)) {
2222 goto Done;
2223 }
2224 Status = SdMmcHcWaitMmioSet (
2225 Private->PciIo,
2226 Trb->Slot,
2227 SD_MMC_HC_SW_RST,
2228 sizeof (SwReset),
2229 0xFF,
2230 0,
2231 SD_MMC_HC_GENERIC_TIMEOUT
2232 );
2233 if (EFI_ERROR (Status)) {
2234 goto Done;
2235 }
2236
2237 Status = EFI_DEVICE_ERROR;
2238 goto Done;
2239 }
2240 //
2241 // Check if DMA interrupt is signalled for the SDMA transfer.
2242 //
2243 if ((Trb->Mode == SdMmcSdmaMode) && ((IntStatus & BIT3) == BIT3)) {
2244 //
2245 // Clear DMA interrupt bit.
2246 //
2247 IntStatus = BIT3;
2248 Status = SdMmcHcRwMmio (
2249 Private->PciIo,
2250 Trb->Slot,
2251 SD_MMC_HC_NOR_INT_STS,
2252 FALSE,
2253 sizeof (IntStatus),
2254 &IntStatus
2255 );
2256 if (EFI_ERROR (Status)) {
2257 goto Done;
2258 }
2259 //
2260 // Update SDMA Address register.
2261 //
2262 SdmaAddr = SD_MMC_SDMA_ROUND_UP ((UINTN)Trb->DataPhy, SD_MMC_SDMA_BOUNDARY);
2263
2264 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {
2265 Status = SdMmcHcRwMmio (
2266 Private->PciIo,
2267 Trb->Slot,
2268 SD_MMC_HC_ADMA_SYS_ADDR,
2269 FALSE,
2270 sizeof (UINT64),
2271 &SdmaAddr
2272 );
2273 } else {
2274 Status = SdMmcHcRwMmio (
2275 Private->PciIo,
2276 Trb->Slot,
2277 SD_MMC_HC_SDMA_ADDR,
2278 FALSE,
2279 sizeof (UINT32),
2280 &SdmaAddr
2281 );
2282 }
2283
2284 if (EFI_ERROR (Status)) {
2285 goto Done;
2286 }
2287 Trb->DataPhy = (UINT64)(UINTN)SdmaAddr;
2288 }
2289
2290 if ((Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeAdtc) &&
2291 (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR1b) &&
2292 (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR5b)) {
2293 if ((IntStatus & BIT0) == BIT0) {
2294 Status = EFI_SUCCESS;
2295 goto Done;
2296 }
2297 }
2298
2299 if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
2300 (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
2301 ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
2302 (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
2303 //
2304 // When performing tuning procedure (Execute Tuning is set to 1) through PIO mode,
2305 // wait Buffer Read Ready bit of Normal Interrupt Status Register to be 1.
2306 // Refer to SD Host Controller Simplified Specification 3.0 figure 2-29 for details.
2307 //
2308 if ((IntStatus & BIT5) == BIT5) {
2309 //
2310 // Clear Buffer Read Ready interrupt at first.
2311 //
2312 IntStatus = BIT5;
2313 SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
2314 //
2315 // Read data out from Buffer Port register
2316 //
2317 for (PioLength = 0; PioLength < Trb->DataLen; PioLength += 4) {
2318 SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_BUF_DAT_PORT, TRUE, 4, (UINT8*)Trb->Data + PioLength);
2319 }
2320 Status = EFI_SUCCESS;
2321 goto Done;
2322 }
2323 }
2324
2325 Status = EFI_NOT_READY;
2326 Done:
2327 //
2328 // Get response data when the cmd is executed successfully.
2329 //
2330 if (!EFI_ERROR (Status)) {
2331 if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
2332 for (Index = 0; Index < 4; Index++) {
2333 Status = SdMmcHcRwMmio (
2334 Private->PciIo,
2335 Trb->Slot,
2336 SD_MMC_HC_RESPONSE + Index * 4,
2337 TRUE,
2338 sizeof (UINT32),
2339 &Response[Index]
2340 );
2341 if (EFI_ERROR (Status)) {
2342 SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);
2343 return Status;
2344 }
2345 }
2346 CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response));
2347 }
2348 }
2349
2350 if (Status != EFI_NOT_READY) {
2351 SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);
2352 }
2353
2354 return Status;
2355 }
2356
2357 /**
2358 Wait for the TRB execution result.
2359
2360 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2361 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2362
2363 @retval EFI_SUCCESS The TRB is executed successfully.
2364 @retval Others Some erros happen when executing this request.
2365
2366 **/
2367 EFI_STATUS
2368 SdMmcWaitTrbResult (
2369 IN SD_MMC_HC_PRIVATE_DATA *Private,
2370 IN SD_MMC_HC_TRB *Trb
2371 )
2372 {
2373 EFI_STATUS Status;
2374 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
2375 UINT64 Timeout;
2376 BOOLEAN InfiniteWait;
2377
2378 Packet = Trb->Packet;
2379 //
2380 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
2381 //
2382 Timeout = Packet->Timeout;
2383 if (Timeout == 0) {
2384 InfiniteWait = TRUE;
2385 } else {
2386 InfiniteWait = FALSE;
2387 }
2388
2389 while (InfiniteWait || (Timeout > 0)) {
2390 //
2391 // Check Trb execution result by reading Normal Interrupt Status register.
2392 //
2393 Status = SdMmcCheckTrbResult (Private, Trb);
2394 if (Status != EFI_NOT_READY) {
2395 return Status;
2396 }
2397 //
2398 // Stall for 1 microsecond.
2399 //
2400 gBS->Stall (1);
2401
2402 Timeout--;
2403 }
2404
2405 return EFI_TIMEOUT;
2406 }
2407
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