3 The definition for UHCI register operation routines.
5 Copyright (c) 2007, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #ifndef _EFI_UHCI_QUEUE_H_
17 #define _EFI_UHCI_QUEUE_H_
20 // Macroes used to set various links in UHCI's driver.
21 // In this UHCI driver, QH's horizontal link always pointers to other QH,
22 // and its vertical link always pointers to TD. TD's next pointer always
23 // pointers to other sibling TD. Frame link always pointers to QH because
24 // ISO transfer isn't supported.
26 // We should use UINT32 to access these pointers to void race conditions
29 #define QH_HLINK(Pointer, Terminate) \
30 (((UINT32) ((UINTN) (Pointer)) & 0xFFFFFFF0) | 0x02 | ((Terminate) ? 0x01 : 0))
32 #define QH_VLINK(Pointer, Terminate) \
33 (((UINT32) ((UINTN) (Pointer)) & 0xFFFFFFF0) | ((Terminate) ? 0x01 : 0))
35 #define TD_LINK(Pointer, VertFirst, Terminate) \
36 (((UINT32) ((UINTN) (Pointer)) & 0xFFFFFFF0) | \
37 ((VertFirst) ? 0x04 : 0) | ((Terminate) ? 0x01 : 0))
39 #define LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
41 #define UHCI_ADDR(QhOrTd) ((VOID *) (UINTN) ((QhOrTd) & 0xFFFFFFF0))
45 // Both links in QH has this internal structure:
46 // Next pointer: 28, Reserved: 2, NextIsQh: 1, Terminate: 1
47 // This is the same as frame list entry.
55 // Next link in TD has this internal structure:
56 // Next pointer: 28, Reserved: 1, Vertical First: 1, NextIsQh: 1, Terminate: 1
60 UINT32 ActualLen
: 11;
66 UINT32 ErrorCount
: 2;
67 UINT32 ShortPacket
: 1;
70 UINT32 DeviceAddr
: 7;
72 UINT32 DataToggle
: 1;
74 UINT32 MaxPacketLen
: 11;
79 typedef struct _UHCI_TD_SW UHCI_TD_SW
;
80 typedef struct _UHCI_QH_SW UHCI_QH_SW
;
100 @param Uhc The UHCI device.
101 @param Qh The queue head for the TD to link to.
102 @param Td The TD to link.
114 Unlink TD from the QH.
116 @param Qh The queue head to unlink from.
117 @param Td The TD to unlink.
130 Map address of request structure buffer.
132 @param Uhc The UHCI device.
133 @param Request The user request buffer.
134 @param MappedAddr Mapped address of request.
135 @param Map Identificaion of this mapping to return.
137 @return EFI_SUCCESS Success.
138 @return EFI_DEVICE_ERROR Fail to map the user request.
144 IN OUT VOID
*Request
,
145 OUT UINT8
**MappedAddr
,
151 Map address of user data buffer.
153 @param Uhc The UHCI device.
154 @param Direction Direction of the data transfer.
155 @param Data The user data buffer.
156 @param Len Length of the user data.
157 @param PktId Packet identificaion.
158 @param MappedAddr Mapped address to return.
159 @param Map Identificaion of this mapping to return.
161 @return EFI_SUCCESS Success.
162 @return EFI_DEVICE_ERROR Fail to map the user data.
168 IN EFI_USB_DATA_DIRECTION Direction
,
172 OUT UINT8
**MappedAddr
,
178 Delete a list of TDs.
180 @param Uhc The UHCI device.
181 @param FirstTd TD link list head.
189 IN UHCI_TD_SW
*FirstTd
194 Create an initialize a new queue head.
196 @param Uhc The UHCI device.
197 @param Interval The polling interval for the queue.
199 @return The newly created queue header.
210 Create Tds list for Control Transfer.
212 @param Uhc The UHCI device.
213 @param DeviceAddr The device address.
214 @param DataPktId Packet Identification of Data Tds.
215 @param Request A pointer to cpu memory address of request structure buffer to transfer.
216 @param RequestPhy A pointer to pci memory address of request structure buffer to transfer.
217 @param Data A pointer to cpu memory address of user data buffer to transfer.
218 @param DataPhy A pointer to pci memory address of user data buffer to transfer.
219 @param DataLen Length of user data to transfer.
220 @param MaxPacket Maximum packet size for control transfer.
221 @param IsLow Full speed or low speed.
223 @return The Td list head for the control transfer.
232 IN UINT8
*RequestPhy
,
242 Create Tds list for Bulk/Interrupt Transfer.
244 @param Uhc USB_HC_DEV.
245 @param DevAddr Address of Device.
246 @param EndPoint Endpoint Number.
247 @param PktId Packet Identification of Data Tds.
248 @param Data A pointer to cpu memory address of user data buffer to transfer.
249 @param DataPhy A pointer to pci memory address of user data buffer to transfer.
250 @param DataLen Length of user data to transfer.
251 @param DataToggle Data Toggle Pointer.
252 @param MaxPacket Maximum packet size for Bulk/Interrupt transfer.
253 @param IsLow Is Low Speed Device.
255 @return The Tds list head for the bulk transfer.
259 UhciCreateBulkOrIntTds (
267 IN OUT UINT8
*DataToggle
,