MdeModulePkg/Bus/Pci/UhciDxe/UhciQueue.h

   1 /** @file
   2
   3   The definition for UHCI register operation routines.
   4
   5 Copyright (c) 2007, Intel Corporation. All rights reserved.<BR>
   6 SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9
  10 #ifndef _EFI_UHCI_QUEUE_H_
  11 #define _EFI_UHCI_QUEUE_H_
  12
  13 //
  14 // Macroes used to set various links in UHCI's driver.
  15 // In this UHCI driver, QH's horizontal link always pointers to other QH,
  16 // and its vertical link always pointers to TD. TD's next pointer always
  17 // pointers to other sibling TD. Frame link always pointers to QH because
  18 // ISO transfer isn't supported.
  19 //
  20 // We should use UINT32 to access these pointers to void race conditions
  21 // with hardware.
  22 //
  23 #define QH_HLINK(Pointer, Terminate)  \
  24         (((UINT32) ((UINTN) (Pointer)) & 0xFFFFFFF0) | 0x02 | ((Terminate) ? 0x01 : 0))
  25
  26 #define QH_VLINK(Pointer, Terminate)  \
  27         (((UINT32) ((UINTN) (Pointer)) & 0xFFFFFFF0) | ((Terminate) ? 0x01 : 0))
  28
  29 #define TD_LINK(Pointer, VertFirst, Terminate) \
  30         (((UINT32) ((UINTN) (Pointer)) & 0xFFFFFFF0) | \
  31          ((VertFirst) ? 0x04 : 0) | ((Terminate) ? 0x01 : 0))
  32
  33 #define LINK_TERMINATED(Link)  (((Link) & 0x01) != 0)
  34
  35 #define UHCI_ADDR(QhOrTd)  ((VOID *) (UINTN) ((QhOrTd) & 0xFFFFFFF0))
  36
  37 #pragma pack(1)
  38 //
  39 // Both links in QH has this internal structure:
  40 //   Next pointer: 28, Reserved: 2, NextIsQh: 1, Terminate: 1
  41 // This is the same as frame list entry.
  42 //
  43 typedef struct {
  44   UINT32    HorizonLink;
  45   UINT32    VerticalLink;
  46 } UHCI_QH_HW;
  47
  48 //
  49 // Next link in TD has this internal structure:
  50 //   Next pointer: 28, Reserved: 1, Vertical First: 1, NextIsQh: 1, Terminate: 1
  51 //
  52 typedef struct {
  53   UINT32    NextLink;
  54   UINT32    ActualLen    : 11;
  55   UINT32    Reserved1    : 5;
  56   UINT32    Status       : 8;
  57   UINT32    IntOnCpl     : 1;
  58   UINT32    IsIsoch      : 1;
  59   UINT32    LowSpeed     : 1;
  60   UINT32    ErrorCount   : 2;
  61   UINT32    ShortPacket  : 1;
  62   UINT32    Reserved2    : 2;
  63   UINT32    PidCode      : 8;
  64   UINT32    DeviceAddr   : 7;
  65   UINT32    EndPoint     : 4;
  66   UINT32    DataToggle   : 1;
  67   UINT32    Reserved3    : 1;
  68   UINT32    MaxPacketLen : 11;
  69   UINT32    DataBuffer;
  70 } UHCI_TD_HW;
  71 #pragma pack()
  72
  73 typedef struct _UHCI_TD_SW  UHCI_TD_SW;
  74 typedef struct _UHCI_QH_SW  UHCI_QH_SW;
  75
  76 struct _UHCI_QH_SW {
  77   UHCI_QH_HW    QhHw;
  78   UHCI_QH_SW    *NextQh;
  79   UHCI_TD_SW    *TDs;
  80   UINTN         Interval;
  81 };
  82
  83 struct _UHCI_TD_SW {
  84   UHCI_TD_HW    TdHw;
  85   UHCI_TD_SW    *NextTd;
  86   UINT8         *Data;
  87   UINT16        DataLen;
  88 };
  89
  90 /**
  91   Link the TD To QH.
  92
  93   @param  Uhc         The UHCI device.
  94   @param  Qh          The queue head for the TD to link to.
  95   @param  Td          The TD to link.
  96
  97 **/
  98 VOID
  99 UhciLinkTdToQh (
 100   IN USB_HC_DEV  *Uhc,
 101   IN UHCI_QH_SW  *Qh,
 102   IN UHCI_TD_SW  *Td
 103   );
 104
 105 /**
 106   Unlink TD from the QH.
 107
 108   @param  Qh          The queue head to unlink from.
 109   @param  Td          The TD to unlink.
 110
 111   @return None.
 112
 113 **/
 114 VOID
 115 UhciUnlinkTdFromQh (
 116   IN UHCI_QH_SW  *Qh,
 117   IN UHCI_TD_SW  *Td
 118   );
 119
 120 /**
 121   Map address of request structure buffer.
 122
 123   @param  Uhc                The UHCI device.
 124   @param  Request            The user request buffer.
 125   @param  MappedAddr         Mapped address of request.
 126   @param  Map                Identificaion of this mapping to return.
 127
 128   @return EFI_SUCCESS        Success.
 129   @return EFI_DEVICE_ERROR   Fail to map the user request.
 130
 131 **/
 132 EFI_STATUS
 133 UhciMapUserRequest (
 134   IN  USB_HC_DEV  *Uhc,
 135   IN  OUT VOID    *Request,
 136   OUT UINT8       **MappedAddr,
 137   OUT VOID        **Map
 138   );
 139
 140 /**
 141   Map address of user data buffer.
 142
 143   @param  Uhc                The UHCI device.
 144   @param  Direction          Direction of the data transfer.
 145   @param  Data               The user data buffer.
 146   @param  Len                Length of the user data.
 147   @param  PktId              Packet identificaion.
 148   @param  MappedAddr         Mapped address to return.
 149   @param  Map                Identificaion of this mapping to return.
 150
 151   @return EFI_SUCCESS        Success.
 152   @return EFI_DEVICE_ERROR   Fail to map the user data.
 153
 154 **/
 155 EFI_STATUS
 156 UhciMapUserData (
 157   IN  USB_HC_DEV              *Uhc,
 158   IN  EFI_USB_DATA_DIRECTION  Direction,
 159   IN  VOID                    *Data,
 160   IN  OUT UINTN               *Len,
 161   OUT UINT8                   *PktId,
 162   OUT UINT8                   **MappedAddr,
 163   OUT VOID                    **Map
 164   );
 165
 166 /**
 167   Delete a list of TDs.
 168
 169   @param  Uhc         The UHCI device.
 170   @param  FirstTd     TD link list head.
 171
 172   @return None.
 173
 174 **/
 175 VOID
 176 UhciDestoryTds (
 177   IN USB_HC_DEV  *Uhc,
 178   IN UHCI_TD_SW  *FirstTd
 179   );
 180
 181 /**
 182   Create an initialize a new queue head.
 183
 184   @param  Uhc         The UHCI device.
 185   @param  Interval    The polling interval for the queue.
 186
 187   @return The newly created queue header.
 188
 189 **/
 190 UHCI_QH_SW *
 191 UhciCreateQh (
 192   IN  USB_HC_DEV  *Uhc,
 193   IN  UINTN       Interval
 194   );
 195
 196 /**
 197   Create Tds list for Control Transfer.
 198
 199   @param  Uhc         The UHCI device.
 200   @param  DeviceAddr  The device address.
 201   @param  DataPktId   Packet Identification of Data Tds.
 202   @param  Request     A pointer to cpu memory address of request structure buffer to transfer.
 203   @param  RequestPhy  A pointer to pci memory address of request structure buffer to transfer.
 204   @param  Data        A pointer to cpu memory address of user data buffer to transfer.
 205   @param  DataPhy     A pointer to pci memory address of user data buffer to transfer.
 206   @param  DataLen     Length of user data to transfer.
 207   @param  MaxPacket   Maximum packet size for control transfer.
 208   @param  IsLow       Full speed or low speed.
 209
 210   @return The Td list head for the control transfer.
 211
 212 **/
 213 UHCI_TD_SW *
 214 UhciCreateCtrlTds (
 215   IN USB_HC_DEV  *Uhc,
 216   IN UINT8       DeviceAddr,
 217   IN UINT8       DataPktId,
 218   IN UINT8       *Request,
 219   IN UINT8       *RequestPhy,
 220   IN UINT8       *Data,
 221   IN UINT8       *DataPhy,
 222   IN UINTN       DataLen,
 223   IN UINT8       MaxPacket,
 224   IN BOOLEAN     IsLow
 225   );
 226
 227 /**
 228   Create Tds list for Bulk/Interrupt Transfer.
 229
 230   @param  Uhc         USB_HC_DEV.
 231   @param  DevAddr     Address of Device.
 232   @param  EndPoint    Endpoint Number.
 233   @param  PktId       Packet Identification of Data Tds.
 234   @param  Data        A pointer to cpu memory address of user data buffer to transfer.
 235   @param  DataPhy     A pointer to pci memory address of user data buffer to transfer.
 236   @param  DataLen     Length of user data to transfer.
 237   @param  DataToggle  Data Toggle Pointer.
 238   @param  MaxPacket   Maximum packet size for Bulk/Interrupt transfer.
 239   @param  IsLow       Is Low Speed Device.
 240
 241   @return The Tds list head for the bulk transfer.
 242
 243 **/
 244 UHCI_TD_SW *
 245 UhciCreateBulkOrIntTds (
 246   IN USB_HC_DEV  *Uhc,
 247   IN UINT8       DevAddr,
 248   IN UINT8       EndPoint,
 249   IN UINT8       PktId,
 250   IN UINT8       *Data,
 251   IN UINT8       *DataPhy,
 252   IN UINTN       DataLen,
 253   IN OUT UINT8   *DataToggle,
 254   IN UINT8       MaxPacket,
 255   IN BOOLEAN     IsLow
 256   );
 257
 258 #endif