]>
git.proxmox.com Git - mirror_edk2.git/blob - MdeModulePkg/Bus/Pci/UhciDxe/UhciReg.c
3 The UHCI register operation routines.
5 Copyright (c) 2007, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
22 @param PciIo The EFI_PCI_IO_PROTOCOL to use.
23 @param Offset Register offset to USB_BAR_INDEX.
25 @return Content of register.
30 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
37 Status
= PciIo
->Io
.Read (
46 if (EFI_ERROR (Status
)) {
47 DEBUG ((EFI_D_ERROR
, "UhciReadReg: PciIo Io.Read error: %r at offset %d\n", Status
, Offset
));
57 Write data to UHCI register.
59 @param PciIo The EFI_PCI_IO_PROTOCOL to use.
60 @param Offset Register offset to USB_BAR_INDEX.
61 @param Data Data to write.
66 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
73 Status
= PciIo
->Io
.Write (
82 if (EFI_ERROR (Status
)) {
83 DEBUG ((EFI_D_ERROR
, "UhciWriteReg: PciIo Io.Write error: %r at offset %d\n", Status
, Offset
));
89 Set a bit of the UHCI Register.
91 @param PciIo The EFI_PCI_IO_PROTOCOL to use.
92 @param Offset Register offset to USB_BAR_INDEX.
93 @param Bit The bit to set.
98 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
105 Data
= UhciReadReg (PciIo
, Offset
);
106 Data
= (UINT16
) (Data
|Bit
);
107 UhciWriteReg (PciIo
, Offset
, Data
);
112 Clear a bit of the UHCI Register.
114 @param PciIo The PCI_IO protocol to access the PCI.
115 @param Offset Register offset to USB_BAR_INDEX.
116 @param Bit The bit to clear.
121 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
128 Data
= UhciReadReg (PciIo
, Offset
);
129 Data
= (UINT16
) (Data
& ~Bit
);
130 UhciWriteReg (PciIo
, Offset
, Data
);
135 Clear all the interrutp status bits, these bits
138 @param Uhc The UHCI device.
142 UhciAckAllInterrupt (
146 UhciWriteReg (Uhc
->PciIo
, USBSTS_OFFSET
, 0x3F);
149 // If current HC is halted, re-enable it. Host Controller Process Error
150 // is a temporary error status.
152 if (!UhciIsHcWorking (Uhc
->PciIo
)) {
153 DEBUG ((EFI_D_ERROR
, "UhciAckAllInterrupt: re-enable the UHCI from system error\n"));
154 Uhc
->Usb2Hc
.SetState (&Uhc
->Usb2Hc
, EfiUsbHcStateOperational
);
160 Stop the host controller.
162 @param Uhc The UHCI device.
163 @param Timeout Max time allowed.
165 @retval EFI_SUCCESS The host controller is stopped.
166 @retval EFI_TIMEOUT Failed to stop the host controller.
178 UhciClearRegBit (Uhc
->PciIo
, USBCMD_OFFSET
, USBCMD_RS
);
181 // ensure the HC is in halt status after send the stop command
182 // Timeout is in us unit.
184 for (Index
= 0; Index
< (Timeout
/ 50) + 1; Index
++) {
185 UsbSts
= UhciReadReg (Uhc
->PciIo
, USBSTS_OFFSET
);
187 if ((UsbSts
& USBSTS_HCH
) == USBSTS_HCH
) {
199 Check whether the host controller operates well.
201 @param PciIo The PCI_IO protocol to use.
203 @retval TRUE Host controller is working.
204 @retval FALSE Host controller is halted or system error.
209 IN EFI_PCI_IO_PROTOCOL
*PciIo
214 UsbSts
= UhciReadReg (PciIo
, USBSTS_OFFSET
);
216 if ((UsbSts
& (USBSTS_HCPE
| USBSTS_HSE
| USBSTS_HCH
)) != 0) {
217 DEBUG ((EFI_D_ERROR
, "UhciIsHcWorking: current USB state is %x\n", UsbSts
));
226 Set the UHCI frame list base address. It can't use
227 UhciWriteReg which access memory in UINT16.
229 @param PciIo The EFI_PCI_IO_PROTOCOL to use.
230 @param Addr Address to set.
234 UhciSetFrameListBaseAddr (
235 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
242 Data
= (UINT32
) ((UINTN
) Addr
& 0xFFFFF000);
244 Status
= PciIo
->Io
.Write (
248 (UINT64
) USB_FRAME_BASE_OFFSET
,
253 if (EFI_ERROR (Status
)) {
254 DEBUG ((EFI_D_ERROR
, "UhciSetFrameListBaseAddr: PciIo Io.Write error: %r\n", Status
));
260 Disable USB Emulation.
262 @param PciIo The EFI_PCI_IO_PROTOCOL protocol to use.
266 UhciTurnOffUsbEmulation (
267 IN EFI_PCI_IO_PROTOCOL
*PciIo
277 USB_EMULATION_OFFSET
,