3 This file contains the register definition of XHCI host controller.
5 Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #ifndef _EFI_XHCI_REG_H_
17 #define _EFI_XHCI_REG_H_
19 #define PCI_IF_XHCI 0x30
22 // PCI Configuration Registers
24 #define XHC_BAR_INDEX 0x00
26 #define XHC_PCI_BAR_OFFSET 0x10 // Memory Bar Register Offset
27 #define XHC_PCI_BAR_MASK 0xFFFF // Memory Base Address Mask
29 #define XHC_PCI_SBRN_OFFSET 0x60 // Serial Bus Release Number Register Offset
31 #define USB_HUB_CLASS_CODE 0x09
32 #define USB_HUB_SUBCLASS_CODE 0x00
34 #define XHC_CAP_USB_LEGACY 0x01
35 #define XHC_CAP_USB_DEBUG 0x0A
37 //============================================//
38 // XHCI register offset //
39 //============================================//
42 // Capability registers offset
44 #define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset
45 #define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h
46 #define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1
47 #define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2
48 #define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3
49 #define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters
50 #define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset
51 #define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset
54 // Operational registers offset
56 #define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset
57 #define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset
58 #define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset
59 #define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset
60 #define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset
61 #define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset
62 #define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset
63 #define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset
66 // Runtime registers offset
68 #define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset
69 #define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset
70 #define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset
71 #define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset
72 #define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset
73 #define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset
76 // Debug registers offset
78 #define XHC_DC_DCCTRL 0x20
80 #define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore
81 #define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore
85 UINT8 MaxSlots
; // Number of Device Slots
86 UINT16 MaxIntrs
:11; // Number of Interrupters
88 UINT8 MaxPorts
; // Number of Ports
92 // Structural Parameters 1 Register Bitmap Definition
100 UINT32 Ist
:4; // Isochronous Scheduling Threshold
101 UINT32 Erst
:4; // Event Ring Segment Table Max
103 UINT32 ScratchBufHi
:5; // Max Scratchpad Buffers Hi
104 UINT32 Spr
:1; // Scratchpad Restore
105 UINT32 ScratchBufLo
:5; // Max Scratchpad Buffers Lo
109 // Structural Parameters 2 Register Bitmap Definition
117 UINT16 Ac64
:1; // 64-bit Addressing Capability
118 UINT16 Bnc
:1; // BW Negotiation Capability
119 UINT16 Csz
:1; // Context Size
120 UINT16 Ppc
:1; // Port Power Control
121 UINT16 Pind
:1; // Port Indicators
122 UINT16 Lhrc
:1; // Light HC Reset Capability
123 UINT16 Ltc
:1; // Latency Tolerance Messaging Capability
124 UINT16 Nss
:1; // No Secondary SID Support
125 UINT16 Pae
:1; // Parse All Event Data
127 UINT16 MaxPsaSize
:4; // Maximum Primary Stream Array Size
128 UINT16 ExtCapReg
; // xHCI Extended Capabilities Pointer
132 // Capability Parameters Register Bitmap Definition
142 // Register Bit Definition
144 #define XHC_USBCMD_RUN BIT0 // Run/Stop
145 #define XHC_USBCMD_RESET BIT1 // Host Controller Reset
146 #define XHC_USBCMD_INTE BIT2 // Interrupter Enable
147 #define XHC_USBCMD_HSEE BIT3 // Host System Error Enable
149 #define XHC_USBSTS_HALT BIT0 // Host Controller Halted
150 #define XHC_USBSTS_HSE BIT2 // Host System Error
151 #define XHC_USBSTS_EINT BIT3 // Event Interrupt
152 #define XHC_USBSTS_PCD BIT4 // Port Change Detect
153 #define XHC_USBSTS_SSS BIT8 // Save State Status
154 #define XHC_USBSTS_RSS BIT9 // Restore State Status
155 #define XHC_USBSTS_SRE BIT10 // Save/Restore Error
156 #define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready
157 #define XHC_USBSTS_HCE BIT12 // Host Controller Error
159 #define XHC_PAGESIZE_MASK 0xFFFF // Page Size
161 #define XHC_CRCR_RCS BIT0 // Ring Cycle State
162 #define XHC_CRCR_CS BIT1 // Command Stop
163 #define XHC_CRCR_CA BIT2 // Command Abort
164 #define XHC_CRCR_CRR BIT3 // Command Ring Running
166 #define XHC_CONFIG_MASK 0xFF // Command Ring Running
168 #define XHC_PORTSC_CCS BIT0 // Current Connect Status
169 #define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled
170 #define XHC_PORTSC_OCA BIT3 // Over-current Active
171 #define XHC_PORTSC_RESET BIT4 // Port Reset
172 #define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State
173 #define XHC_PORTSC_PP BIT9 // Port Power
174 #define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // Port Speed
175 #define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe
176 #define XHC_PORTSC_CSC BIT17 // Connect Status Change
177 #define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change
178 #define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change
179 #define XHC_PORTSC_OCC BIT20 // Over-Current Change
180 #define XHC_PORTSC_PRC BIT21 // Port Reset Change
181 #define XHC_PORTSC_PLC BIT22 // Port Link State Change
182 #define XHC_PORTSC_CEC BIT23 // Port Config Error Change
183 #define XHC_PORTSC_CAS BIT24 // Cold Attach Status
185 #define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status
186 #define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled
187 #define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active
188 #define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset
189 #define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power
190 #define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change
191 #define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change
192 #define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change
193 #define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change
194 #define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change
195 #define XHC_IMAN_IP BIT0 // Interrupt Pending
196 #define XHC_IMAN_IE BIT1 // Interrupt Enable
198 #define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval
199 #define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter
202 // Hub Class Feature Selector for Clear Port Feature Request
203 // It's the extension of hub class feature selector of USB 2.0 in USB 3.0 Spec.
204 // For more details, Please refer to USB 3.0 Spec Table 10-7.
207 Usb3PortBHPortReset
= 28,
208 Usb3PortBHPortResetChange
= 29
212 // Structure to map the hardware port states to the
213 // UEFI's port states.
218 } USB_PORT_STATE_MAP
;
221 // Structure to map the hardware port states to feature selector for clear port feature request.
226 } USB_CLEAR_PORT_MAP
;
229 Read 1-byte width XHCI capability register.
231 @param Xhc The XHCI Instance.
232 @param Offset The offset of the 1-byte width capability register.
234 @return The register content read.
235 @retval If err, return 0xFFFF.
240 IN USB_XHCI_INSTANCE
*Xhc
,
245 Read 4-bytes width XHCI capability register.
247 @param Xhc The XHCI Instance.
248 @param Offset The offset of the 4-bytes width capability register.
250 @return The register content read.
251 @retval If err, return 0xFFFFFFFF.
256 IN USB_XHCI_INSTANCE
*Xhc
,
261 Read 4-bytes width XHCI Operational register.
263 @param Xhc The XHCI Instance.
264 @param Offset The offset of the 4-bytes width operational register.
266 @return The register content read.
267 @retval If err, return 0xFFFFFFFF.
272 IN USB_XHCI_INSTANCE
*Xhc
,
277 Write the data to the 4-bytes width XHCI operational register.
279 @param Xhc The XHCI Instance.
280 @param Offset The offset of the 4-bytes width operational register.
281 @param Data The data to write.
286 IN USB_XHCI_INSTANCE
*Xhc
,
293 Read XHCI runtime register.
295 @param Xhc The XHCI Instance.
296 @param Offset The offset of the runtime register.
298 @return The register content read
303 IN USB_XHCI_INSTANCE
*Xhc
,
308 Write the data to the XHCI runtime register.
310 @param Xhc The XHCI Instance.
311 @param Offset The offset of the runtime register.
312 @param Data The data to write.
317 IN USB_XHCI_INSTANCE
*Xhc
,
324 Write the data to the XHCI door bell register.
326 @param Xhc The XHCI Instance.
327 @param Offset The offset of the door bell register.
328 @param Data The data to write.
332 XhcWriteDoorBellReg (
333 IN USB_XHCI_INSTANCE
*Xhc
,
339 Set one bit of the operational register while keeping other bits.
341 @param Xhc The XHCI Instance.
342 @param Offset The offset of the operational register.
343 @param Bit The bit mask of the register to set.
348 IN USB_XHCI_INSTANCE
*Xhc
,
354 Clear one bit of the operational register while keeping other bits.
356 @param Xhc The XHCI Instance.
357 @param Offset The offset of the operational register.
358 @param Bit The bit mask of the register to clear.
363 IN USB_XHCI_INSTANCE
*Xhc
,
369 Wait the operation register's bit as specified by Bit
370 to be set (or clear).
372 @param Xhc The XHCI Instance.
373 @param Offset The offset of the operational register.
374 @param Bit The bit of the register to wait for.
375 @param WaitToSet Wait the bit to set or clear.
376 @param Timeout The time to wait before abort (in millisecond, ms).
378 @retval EFI_SUCCESS The bit successfully changed by host controller.
379 @retval EFI_TIMEOUT The time out occurred.
384 IN USB_XHCI_INSTANCE
*Xhc
,
387 IN BOOLEAN WaitToSet
,
392 Read XHCI runtime register.
394 @param Xhc The XHCI Instance.
395 @param Offset The offset of the runtime register.
397 @return The register content read
402 IN USB_XHCI_INSTANCE
*Xhc
,
407 Write the data to the XHCI runtime register.
409 @param Xhc The XHCI Instance.
410 @param Offset The offset of the runtime register.
411 @param Data The data to write.
416 IN USB_XHCI_INSTANCE
*Xhc
,
422 Set one bit of the runtime register while keeping other bits.
424 @param Xhc The XHCI Instance.
425 @param Offset The offset of the runtime register.
426 @param Bit The bit mask of the register to set.
430 XhcSetRuntimeRegBit (
431 IN USB_XHCI_INSTANCE
*Xhc
,
437 Clear one bit of the runtime register while keeping other bits.
439 @param Xhc The XHCI Instance.
440 @param Offset The offset of the runtime register.
441 @param Bit The bit mask of the register to set.
445 XhcClearRuntimeRegBit (
446 IN USB_XHCI_INSTANCE
*Xhc
,
452 Read XHCI extended capability register.
454 @param Xhc The XHCI Instance.
455 @param Offset The offset of the extended capability register.
457 @return The register content read
462 IN USB_XHCI_INSTANCE
*Xhc
,
467 Whether the XHCI host controller is halted.
469 @param Xhc The XHCI Instance.
471 @retval TRUE The controller is halted.
472 @retval FALSE It isn't halted.
477 IN USB_XHCI_INSTANCE
*Xhc
481 Whether system error occurred.
483 @param Xhc The XHCI Instance.
485 @retval TRUE System error happened.
486 @retval FALSE No system error.
491 IN USB_XHCI_INSTANCE
*Xhc
495 Reset the XHCI host controller.
497 @param Xhc The XHCI Instance.
498 @param Timeout Time to wait before abort (in millisecond, ms).
500 @retval EFI_SUCCESS The XHCI host controller is reset.
501 @return Others Failed to reset the XHCI before Timeout.
506 IN USB_XHCI_INSTANCE
*Xhc
,
511 Halt the XHCI host controller.
513 @param Xhc The XHCI Instance.
514 @param Timeout Time to wait before abort (in millisecond, ms).
516 @return EFI_SUCCESS The XHCI host controller is halt.
517 @return EFI_TIMEOUT Failed to halt the XHCI before Timeout.
522 IN USB_XHCI_INSTANCE
*Xhc
,
527 Set the XHCI host controller to run.
529 @param Xhc The XHCI Instance.
530 @param Timeout Time to wait before abort (in millisecond, ms).
532 @return EFI_SUCCESS The XHCI host controller is running.
533 @return EFI_TIMEOUT Failed to set the XHCI to run before Timeout.
538 IN USB_XHCI_INSTANCE
*Xhc
,
543 Calculate the offset of the XHCI capability.
545 @param Xhc The XHCI Instance.
546 @param CapId The XHCI Capability ID.
548 @return The offset of XHCI legacy support capability register.
552 XhcGetCapabilityAddr (
553 IN USB_XHCI_INSTANCE
*Xhc
,