3 This file contains the register definition of XHCI host controller.
5 Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
10 #ifndef _EFI_XHCI_REG_H_
11 #define _EFI_XHCI_REG_H_
13 #define PCI_IF_XHCI 0x30
16 // PCI Configuration Registers
18 #define XHC_BAR_INDEX 0x00
20 #define XHC_PCI_BAR_OFFSET 0x10 // Memory Bar Register Offset
21 #define XHC_PCI_BAR_MASK 0xFFFF // Memory Base Address Mask
23 #define XHC_PCI_SBRN_OFFSET 0x60 // Serial Bus Release Number Register Offset
25 #define USB_HUB_CLASS_CODE 0x09
26 #define USB_HUB_SUBCLASS_CODE 0x00
28 #define XHC_CAP_USB_LEGACY 0x01
29 #define XHC_CAP_USB_DEBUG 0x0A
30 #define XHC_CAP_USB_SUPPORTED_PROTOCOL 0x02
32 // ============================================//
33 // XHCI register offset //
34 // ============================================//
37 // Capability registers offset
39 #define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset
40 #define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h
41 #define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1
42 #define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2
43 #define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3
44 #define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters
45 #define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset
46 #define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset
49 // Operational registers offset
51 #define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset
52 #define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset
53 #define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset
54 #define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset
55 #define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset
56 #define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset
57 #define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset
58 #define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset
61 // Runtime registers offset
63 #define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset
64 #define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset
65 #define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset
66 #define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset
67 #define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset
68 #define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset
71 // Debug registers offset
73 #define XHC_DC_DCCTRL 0x20
75 #define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore
76 #define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore
79 // xHCI Supported Protocol Capability
81 #define XHC_SUPPORTED_PROTOCOL_DW0_MAJOR_REVISION_USB2 0x02
82 #define XHC_SUPPORTED_PROTOCOL_DW0_MAJOR_REVISION_USB3 0x03
83 #define XHC_SUPPORTED_PROTOCOL_NAME_STRING_OFFSET 0x04
84 #define XHC_SUPPORTED_PROTOCOL_NAME_STRING_VALUE 0x20425355
85 #define XHC_SUPPORTED_PROTOCOL_DW2_OFFSET 0x08
86 #define XHC_SUPPORTED_PROTOCOL_PSI_OFFSET 0x10
87 #define XHC_SUPPORTED_PROTOCOL_USB2_HIGH_SPEED_PSIM 480
88 #define XHC_SUPPORTED_PROTOCOL_USB2_LOW_SPEED_PSIM 1500
92 UINT8 MaxSlots
; // Number of Device Slots
93 UINT16 MaxIntrs
: 11; // Number of Interrupters
95 UINT8 MaxPorts
; // Number of Ports
99 // Structural Parameters 1 Register Bitmap Definition
107 UINT32 Ist
: 4; // Isochronous Scheduling Threshold
108 UINT32 Erst
: 4; // Event Ring Segment Table Max
110 UINT32 ScratchBufHi
: 5; // Max Scratchpad Buffers Hi
111 UINT32 Spr
: 1; // Scratchpad Restore
112 UINT32 ScratchBufLo
: 5; // Max Scratchpad Buffers Lo
116 // Structural Parameters 2 Register Bitmap Definition
124 UINT16 Ac64
: 1; // 64-bit Addressing Capability
125 UINT16 Bnc
: 1; // BW Negotiation Capability
126 UINT16 Csz
: 1; // Context Size
127 UINT16 Ppc
: 1; // Port Power Control
128 UINT16 Pind
: 1; // Port Indicators
129 UINT16 Lhrc
: 1; // Light HC Reset Capability
130 UINT16 Ltc
: 1; // Latency Tolerance Messaging Capability
131 UINT16 Nss
: 1; // No Secondary SID Support
132 UINT16 Pae
: 1; // Parse All Event Data
134 UINT16 MaxPsaSize
: 4; // Maximum Primary Stream Array Size
135 UINT16 ExtCapReg
; // xHCI Extended Capabilities Pointer
139 // Capability Parameters Register Bitmap Definition
147 // xHCI Supported Protocol Cabability
154 } SUPPORTED_PROTOCOL_DW0
;
158 SUPPORTED_PROTOCOL_DW0 Data
;
159 } XHC_SUPPORTED_PROTOCOL_DW0
;
163 } XHC_SUPPORTED_PROTOCOL_DW1
;
166 UINT8 CompPortOffset
;
168 UINT16 ProtocolDef
: 12;
170 } SUPPORTED_PROTOCOL_DW2
;
174 SUPPORTED_PROTOCOL_DW2 Data
;
175 } XHC_SUPPORTED_PROTOCOL_DW2
;
185 } SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID
;
189 SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID Data
;
190 } XHC_SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID
;
195 // Register Bit Definition
197 #define XHC_USBCMD_RUN BIT0 // Run/Stop
198 #define XHC_USBCMD_RESET BIT1 // Host Controller Reset
199 #define XHC_USBCMD_INTE BIT2 // Interrupter Enable
200 #define XHC_USBCMD_HSEE BIT3 // Host System Error Enable
202 #define XHC_USBSTS_HALT BIT0 // Host Controller Halted
203 #define XHC_USBSTS_HSE BIT2 // Host System Error
204 #define XHC_USBSTS_EINT BIT3 // Event Interrupt
205 #define XHC_USBSTS_PCD BIT4 // Port Change Detect
206 #define XHC_USBSTS_SSS BIT8 // Save State Status
207 #define XHC_USBSTS_RSS BIT9 // Restore State Status
208 #define XHC_USBSTS_SRE BIT10 // Save/Restore Error
209 #define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready
210 #define XHC_USBSTS_HCE BIT12 // Host Controller Error
212 #define XHC_PAGESIZE_MASK 0xFFFF // Page Size
214 #define XHC_CRCR_RCS BIT0 // Ring Cycle State
215 #define XHC_CRCR_CS BIT1 // Command Stop
216 #define XHC_CRCR_CA BIT2 // Command Abort
217 #define XHC_CRCR_CRR BIT3 // Command Ring Running
219 #define XHC_CONFIG_MASK 0xFF // Command Ring Running
221 #define XHC_PORTSC_CCS BIT0 // Current Connect Status
222 #define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled
223 #define XHC_PORTSC_OCA BIT3 // Over-current Active
224 #define XHC_PORTSC_RESET BIT4 // Port Reset
225 #define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State
226 #define XHC_PORTSC_PP BIT9 // Port Power
227 #define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // Port Speed
228 #define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe
229 #define XHC_PORTSC_CSC BIT17 // Connect Status Change
230 #define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change
231 #define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change
232 #define XHC_PORTSC_OCC BIT20 // Over-Current Change
233 #define XHC_PORTSC_PRC BIT21 // Port Reset Change
234 #define XHC_PORTSC_PLC BIT22 // Port Link State Change
235 #define XHC_PORTSC_CEC BIT23 // Port Config Error Change
236 #define XHC_PORTSC_CAS BIT24 // Cold Attach Status
238 #define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status
239 #define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled
240 #define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active
241 #define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset
242 #define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power
243 #define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change
244 #define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change
245 #define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change
246 #define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change
247 #define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change
248 #define XHC_IMAN_IP BIT0 // Interrupt Pending
249 #define XHC_IMAN_IE BIT1 // Interrupt Enable
251 #define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval
252 #define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter
255 // Hub Class Feature Selector for Clear Port Feature Request
256 // It's the extension of hub class feature selector of USB 2.0 in USB 3.0 Spec.
257 // For more details, Please refer to USB 3.0 Spec Table 10-7.
260 Usb3PortBHPortReset
= 28,
261 Usb3PortBHPortResetChange
= 29
265 // Structure to map the hardware port states to the
266 // UEFI's port states.
271 } USB_PORT_STATE_MAP
;
274 // Structure to map the hardware port states to feature selector for clear port feature request.
279 } USB_CLEAR_PORT_MAP
;
282 Read 1-byte width XHCI capability register.
284 @param Xhc The XHCI Instance.
285 @param Offset The offset of the 1-byte width capability register.
287 @return The register content read.
288 @retval If err, return 0xFFFF.
293 IN USB_XHCI_INSTANCE
*Xhc
,
298 Read 4-bytes width XHCI capability register.
300 @param Xhc The XHCI Instance.
301 @param Offset The offset of the 4-bytes width capability register.
303 @return The register content read.
304 @retval If err, return 0xFFFFFFFF.
309 IN USB_XHCI_INSTANCE
*Xhc
,
314 Read 4-bytes width XHCI Operational register.
316 @param Xhc The XHCI Instance.
317 @param Offset The offset of the 4-bytes width operational register.
319 @return The register content read.
320 @retval If err, return 0xFFFFFFFF.
325 IN USB_XHCI_INSTANCE
*Xhc
,
330 Write the data to the 4-bytes width XHCI operational register.
332 @param Xhc The XHCI Instance.
333 @param Offset The offset of the 4-bytes width operational register.
334 @param Data The data to write.
339 IN USB_XHCI_INSTANCE
*Xhc
,
345 Read XHCI runtime register.
347 @param Xhc The XHCI Instance.
348 @param Offset The offset of the runtime register.
350 @return The register content read
355 IN USB_XHCI_INSTANCE
*Xhc
,
360 Write the data to the XHCI runtime register.
362 @param Xhc The XHCI Instance.
363 @param Offset The offset of the runtime register.
364 @param Data The data to write.
369 IN USB_XHCI_INSTANCE
*Xhc
,
375 Write the data to the XHCI door bell register.
377 @param Xhc The XHCI Instance.
378 @param Offset The offset of the door bell register.
379 @param Data The data to write.
383 XhcWriteDoorBellReg (
384 IN USB_XHCI_INSTANCE
*Xhc
,
390 Set one bit of the operational register while keeping other bits.
392 @param Xhc The XHCI Instance.
393 @param Offset The offset of the operational register.
394 @param Bit The bit mask of the register to set.
399 IN USB_XHCI_INSTANCE
*Xhc
,
405 Clear one bit of the operational register while keeping other bits.
407 @param Xhc The XHCI Instance.
408 @param Offset The offset of the operational register.
409 @param Bit The bit mask of the register to clear.
414 IN USB_XHCI_INSTANCE
*Xhc
,
420 Wait the operation register's bit as specified by Bit
421 to be set (or clear).
423 @param Xhc The XHCI Instance.
424 @param Offset The offset of the operational register.
425 @param Bit The bit of the register to wait for.
426 @param WaitToSet Wait the bit to set or clear.
427 @param Timeout The time to wait before abort (in millisecond, ms).
429 @retval EFI_SUCCESS The bit successfully changed by host controller.
430 @retval EFI_TIMEOUT The time out occurred.
435 IN USB_XHCI_INSTANCE
*Xhc
,
438 IN BOOLEAN WaitToSet
,
443 Read XHCI runtime register.
445 @param Xhc The XHCI Instance.
446 @param Offset The offset of the runtime register.
448 @return The register content read
453 IN USB_XHCI_INSTANCE
*Xhc
,
458 Write the data to the XHCI runtime register.
460 @param Xhc The XHCI Instance.
461 @param Offset The offset of the runtime register.
462 @param Data The data to write.
467 IN USB_XHCI_INSTANCE
*Xhc
,
473 Set one bit of the runtime register while keeping other bits.
475 @param Xhc The XHCI Instance.
476 @param Offset The offset of the runtime register.
477 @param Bit The bit mask of the register to set.
481 XhcSetRuntimeRegBit (
482 IN USB_XHCI_INSTANCE
*Xhc
,
488 Clear one bit of the runtime register while keeping other bits.
490 @param Xhc The XHCI Instance.
491 @param Offset The offset of the runtime register.
492 @param Bit The bit mask of the register to set.
496 XhcClearRuntimeRegBit (
497 IN USB_XHCI_INSTANCE
*Xhc
,
503 Read XHCI extended capability register.
505 @param Xhc The XHCI Instance.
506 @param Offset The offset of the extended capability register.
508 @return The register content read
513 IN USB_XHCI_INSTANCE
*Xhc
,
518 Whether the XHCI host controller is halted.
520 @param Xhc The XHCI Instance.
522 @retval TRUE The controller is halted.
523 @retval FALSE It isn't halted.
528 IN USB_XHCI_INSTANCE
*Xhc
532 Whether system error occurred.
534 @param Xhc The XHCI Instance.
536 @retval TRUE System error happened.
537 @retval FALSE No system error.
542 IN USB_XHCI_INSTANCE
*Xhc
546 Reset the XHCI host controller.
548 @param Xhc The XHCI Instance.
549 @param Timeout Time to wait before abort (in millisecond, ms).
551 @retval EFI_SUCCESS The XHCI host controller is reset.
552 @return Others Failed to reset the XHCI before Timeout.
557 IN USB_XHCI_INSTANCE
*Xhc
,
562 Halt the XHCI host controller.
564 @param Xhc The XHCI Instance.
565 @param Timeout Time to wait before abort (in millisecond, ms).
567 @return EFI_SUCCESS The XHCI host controller is halt.
568 @return EFI_TIMEOUT Failed to halt the XHCI before Timeout.
573 IN USB_XHCI_INSTANCE
*Xhc
,
578 Set the XHCI host controller to run.
580 @param Xhc The XHCI Instance.
581 @param Timeout Time to wait before abort (in millisecond, ms).
583 @return EFI_SUCCESS The XHCI host controller is running.
584 @return EFI_TIMEOUT Failed to set the XHCI to run before Timeout.
589 IN USB_XHCI_INSTANCE
*Xhc
,
594 Calculate the offset of the XHCI capability.
596 @param Xhc The XHCI Instance.
597 @param CapId The XHCI Capability ID.
599 @return The offset of XHCI legacy support capability register.
603 XhcGetCapabilityAddr (
604 IN USB_XHCI_INSTANCE
*Xhc
,
609 Calculate the offset of the xHCI Supported Protocol Capability.
611 @param Xhc The XHCI Instance.
612 @param MajorVersion The USB Major Version in xHCI Support Protocol Capability Field
614 @return The offset of xHCI Supported Protocol capability register.
618 XhcGetSupportedProtocolCapabilityAddr (
619 IN USB_XHCI_INSTANCE
*Xhc
,
620 IN UINT8 MajorVersion
624 Find PortSpeed value match case in XHCI Supported Protocol Capability
626 @param Xhc The XHCI Instance.
627 @param PortSpeed The Port Speed Field in USB PortSc register
628 @param PortNumber The Port Number (0-indexed)
630 @return The USB Port Speed.
634 XhcCheckUsbPortSpeedUsedPsic (
635 IN USB_XHCI_INSTANCE
*Xhc
,