3 This file contains the register definition of XHCI host controller.
5 Copyright (c) 2011 - 2013, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #ifndef _EFI_XHCI_REG_H_
17 #define _EFI_XHCI_REG_H_
19 #define PCI_IF_XHCI 0x30
22 // PCI Configuration Registers
24 #define XHC_BAR_INDEX 0x00
26 #define XHC_PCI_BAR_OFFSET 0x10 // Memory Bar Register Offset
27 #define XHC_PCI_BAR_MASK 0xFFFF // Memory Base Address Mask
29 #define USB_HUB_CLASS_CODE 0x09
30 #define USB_HUB_SUBCLASS_CODE 0x00
32 #define XHC_CAP_USB_LEGACY 0x01
33 #define XHC_CAP_USB_DEBUG 0x0A
35 //============================================//
36 // XHCI register offset //
37 //============================================//
40 // Capability registers offset
42 #define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset
43 #define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h
44 #define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1
45 #define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2
46 #define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3
47 #define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters
48 #define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset
49 #define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset
52 // Operational registers offset
54 #define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset
55 #define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset
56 #define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset
57 #define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset
58 #define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset
59 #define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset
60 #define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset
61 #define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset
64 // Runtime registers offset
66 #define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset
67 #define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset
68 #define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset
69 #define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset
70 #define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset
71 #define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset
74 // Debug registers offset
76 #define XHC_DC_DCCTRL 0x20
78 #define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore
79 #define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore
83 UINT8 MaxSlots
; // Number of Device Slots
84 UINT16 MaxIntrs
:11; // Number of Interrupters
86 UINT8 MaxPorts
; // Number of Ports
90 // Structural Parameters 1 Register Bitmap Definition
98 UINT32 Ist
:4; // Isochronous Scheduling Threshold
99 UINT32 Erst
:4; // Event Ring Segment Table Max
101 UINT32 ScratchBufHi
:5; // Max Scratchpad Buffers Hi
102 UINT32 Spr
:1; // Scratchpad Restore
103 UINT32 ScratchBufLo
:5; // Max Scratchpad Buffers Lo
107 // Structural Parameters 2 Register Bitmap Definition
115 UINT16 Ac64
:1; // 64-bit Addressing Capability
116 UINT16 Bnc
:1; // BW Negotiation Capability
117 UINT16 Csz
:1; // Context Size
118 UINT16 Ppc
:1; // Port Power Control
119 UINT16 Pind
:1; // Port Indicators
120 UINT16 Lhrc
:1; // Light HC Reset Capability
121 UINT16 Ltc
:1; // Latency Tolerance Messaging Capability
122 UINT16 Nss
:1; // No Secondary SID Support
123 UINT16 Pae
:1; // Parse All Event Data
125 UINT16 MaxPsaSize
:4; // Maximum Primary Stream Array Size
126 UINT16 ExtCapReg
; // xHCI Extended Capabilities Pointer
130 // Capability Parameters Register Bitmap Definition
140 // Register Bit Definition
142 #define XHC_USBCMD_RUN BIT0 // Run/Stop
143 #define XHC_USBCMD_RESET BIT1 // Host Controller Reset
144 #define XHC_USBCMD_INTE BIT2 // Interrupter Enable
145 #define XHC_USBCMD_HSEE BIT3 // Host System Error Enable
147 #define XHC_USBSTS_HALT BIT0 // Host Controller Halted
148 #define XHC_USBSTS_HSE BIT2 // Host System Error
149 #define XHC_USBSTS_EINT BIT3 // Event Interrupt
150 #define XHC_USBSTS_PCD BIT4 // Port Change Detect
151 #define XHC_USBSTS_SSS BIT8 // Save State Status
152 #define XHC_USBSTS_RSS BIT9 // Restore State Status
153 #define XHC_USBSTS_SRE BIT10 // Save/Restore Error
154 #define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready
155 #define XHC_USBSTS_HCE BIT12 // Host Controller Error
157 #define XHC_PAGESIZE_MASK 0xFFFF // Page Size
159 #define XHC_CRCR_RCS BIT0 // Ring Cycle State
160 #define XHC_CRCR_CS BIT1 // Command Stop
161 #define XHC_CRCR_CA BIT2 // Command Abort
162 #define XHC_CRCR_CRR BIT3 // Command Ring Running
164 #define XHC_CONFIG_MASK 0xFF // Command Ring Running
166 #define XHC_PORTSC_CCS BIT0 // Current Connect Status
167 #define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled
168 #define XHC_PORTSC_OCA BIT3 // Over-current Active
169 #define XHC_PORTSC_RESET BIT4 // Port Reset
170 #define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State
171 #define XHC_PORTSC_PP BIT9 // Port Power
172 #define XHC_PORTSC_PS (BIT10|BIT11|BIT12) // Port Speed
173 #define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe
174 #define XHC_PORTSC_CSC BIT17 // Connect Status Change
175 #define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change
176 #define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change
177 #define XHC_PORTSC_OCC BIT20 // Over-Current Change
178 #define XHC_PORTSC_PRC BIT21 // Port Reset Change
179 #define XHC_PORTSC_PLC BIT22 // Port Link State Change
180 #define XHC_PORTSC_CEC BIT23 // Port Config Error Change
181 #define XHC_PORTSC_CAS BIT24 // Cold Attach Status
183 #define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status
184 #define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled
185 #define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active
186 #define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset
187 #define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power
188 #define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change
189 #define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change
190 #define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change
191 #define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change
192 #define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change
193 #define XHC_IMAN_IP BIT0 // Interrupt Pending
194 #define XHC_IMAN_IE BIT1 // Interrupt Enable
196 #define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval
197 #define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter
200 // Hub Class Feature Selector for Clear Port Feature Request
201 // It's the extension of hub class feature selector of USB 2.0 in USB 3.0 Spec.
202 // For more details, Please refer to USB 3.0 Spec Table 10-7.
205 Usb3PortBHPortReset
= 28,
206 Usb3PortBHPortResetChange
= 29
210 // Structure to map the hardware port states to the
211 // UEFI's port states.
216 } USB_PORT_STATE_MAP
;
219 // Structure to map the hardware port states to feature selector for clear port feature request.
224 } USB_CLEAR_PORT_MAP
;
227 Read 1-byte width XHCI capability register.
229 @param Xhc The XHCI Instance.
230 @param Offset The offset of the 1-byte width capability register.
232 @return The register content read.
233 @retval If err, return 0xFFFF.
238 IN USB_XHCI_INSTANCE
*Xhc
,
243 Read 4-bytes width XHCI capability register.
245 @param Xhc The XHCI Instance.
246 @param Offset The offset of the 4-bytes width capability register.
248 @return The register content read.
249 @retval If err, return 0xFFFFFFFF.
254 IN USB_XHCI_INSTANCE
*Xhc
,
259 Read 4-bytes width XHCI Operational register.
261 @param Xhc The XHCI Instance.
262 @param Offset The offset of the 4-bytes width operational register.
264 @return The register content read.
265 @retval If err, return 0xFFFFFFFF.
270 IN USB_XHCI_INSTANCE
*Xhc
,
275 Write the data to the 4-bytes width XHCI operational register.
277 @param Xhc The XHCI Instance.
278 @param Offset The offset of the 4-bytes width operational register.
279 @param Data The data to write.
284 IN USB_XHCI_INSTANCE
*Xhc
,
290 Write the data to the 2-bytes width XHCI operational register.
292 @param Xhc The XHCI Instance.
293 @param Offset The offset of the 2-bytes width operational register.
294 @param Data The data to write.
299 IN USB_XHCI_INSTANCE
*Xhc
,
305 Read XHCI runtime register.
307 @param Xhc The XHCI Instance.
308 @param Offset The offset of the runtime register.
310 @return The register content read
315 IN USB_XHCI_INSTANCE
*Xhc
,
320 Write the data to the XHCI runtime register.
322 @param Xhc The XHCI Instance.
323 @param Offset The offset of the runtime register.
324 @param Data The data to write.
329 IN USB_XHCI_INSTANCE
*Xhc
,
335 Read XHCI door bell register.
337 @param Xhc The XHCI Instance.
338 @param Offset The offset of the door bell register.
340 @return The register content read
345 IN USB_XHCI_INSTANCE
*Xhc
,
350 Write the data to the XHCI door bell register.
352 @param Xhc The XHCI Instance.
353 @param Offset The offset of the door bell register.
354 @param Data The data to write.
358 XhcWriteDoorBellReg (
359 IN USB_XHCI_INSTANCE
*Xhc
,
365 Set one bit of the operational register while keeping other bits.
367 @param Xhc The XHCI Instance.
368 @param Offset The offset of the operational register.
369 @param Bit The bit mask of the register to set.
374 IN USB_XHCI_INSTANCE
*Xhc
,
380 Clear one bit of the operational register while keeping other bits.
382 @param Xhc The XHCI Instance.
383 @param Offset The offset of the operational register.
384 @param Bit The bit mask of the register to clear.
389 IN USB_XHCI_INSTANCE
*Xhc
,
395 Wait the operation register's bit as specified by Bit
396 to be set (or clear).
398 @param Xhc The XHCI Instance.
399 @param Offset The offset of the operational register.
400 @param Bit The bit of the register to wait for.
401 @param WaitToSet Wait the bit to set or clear.
402 @param Timeout The time to wait before abort (in microsecond, us).
404 @retval EFI_SUCCESS The bit successfully changed by host controller.
405 @retval EFI_TIMEOUT The time out occurred.
410 IN USB_XHCI_INSTANCE
*Xhc
,
413 IN BOOLEAN WaitToSet
,
418 Read XHCI runtime register.
420 @param Xhc The XHCI Instance.
421 @param Offset The offset of the runtime register.
423 @return The register content read
428 IN USB_XHCI_INSTANCE
*Xhc
,
433 Write the data to the XHCI runtime register.
435 @param Xhc The XHCI Instance.
436 @param Offset The offset of the runtime register.
437 @param Data The data to write.
442 IN USB_XHCI_INSTANCE
*Xhc
,
448 Set one bit of the runtime register while keeping other bits.
450 @param Xhc The XHCI Instance.
451 @param Offset The offset of the runtime register.
452 @param Bit The bit mask of the register to set.
456 XhcSetRuntimeRegBit (
457 IN USB_XHCI_INSTANCE
*Xhc
,
463 Clear one bit of the runtime register while keeping other bits.
465 @param Xhc The XHCI Instance.
466 @param Offset The offset of the runtime register.
467 @param Bit The bit mask of the register to set.
471 XhcClearRuntimeRegBit (
472 IN USB_XHCI_INSTANCE
*Xhc
,
478 Read XHCI extended capability register.
480 @param Xhc The XHCI Instance.
481 @param Offset The offset of the extended capability register.
483 @return The register content read
488 IN USB_XHCI_INSTANCE
*Xhc
,
493 Whether the XHCI host controller is halted.
495 @param Xhc The XHCI Instance.
497 @retval TRUE The controller is halted.
498 @retval FALSE It isn't halted.
503 IN USB_XHCI_INSTANCE
*Xhc
507 Whether system error occurred.
509 @param Xhc The XHCI Instance.
511 @retval TRUE System error happened.
512 @retval FALSE No system error.
517 IN USB_XHCI_INSTANCE
*Xhc
521 Reset the XHCI host controller.
523 @param Xhc The XHCI Instance.
524 @param Timeout Time to wait before abort (in microsecond, us).
526 @retval EFI_SUCCESS The XHCI host controller is reset.
527 @return Others Failed to reset the XHCI before Timeout.
532 IN USB_XHCI_INSTANCE
*Xhc
,
537 Halt the XHCI host controller.
539 @param Xhc The XHCI Instance.
540 @param Timeout Time to wait before abort (in microsecond, us).
542 @return EFI_SUCCESS The XHCI host controller is halt.
543 @return EFI_TIMEOUT Failed to halt the XHCI before Timeout.
548 IN USB_XHCI_INSTANCE
*Xhc
,
553 Set the XHCI host controller to run.
555 @param Xhc The XHCI Instance.
556 @param Timeout Time to wait before abort (in microsecond, us).
558 @return EFI_SUCCESS The XHCI host controller is running.
559 @return EFI_TIMEOUT Failed to set the XHCI to run before Timeout.
564 IN USB_XHCI_INSTANCE
*Xhc
,
569 Calculate the offset of the XHCI capability.
571 @param Xhc The XHCI Instance.
572 @param CapId The XHCI Capability ID.
574 @return The offset of XHCI legacy support capability register.
578 XhcGetCapabilityAddr (
579 IN USB_XHCI_INSTANCE
*Xhc
,