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git.proxmox.com Git - mirror_edk2.git/blob - MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
3 This file contains the register definition of XHCI host controller.
5 Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #ifndef _EFI_XHCI_REG_H_
17 #define _EFI_XHCI_REG_H_
19 #define PCI_IF_XHCI 0x30
22 // PCI Configuration Registers
24 #define XHC_BAR_INDEX 0x00
26 #define XHC_PCI_BAR_OFFSET 0x10 // Memory Bar Register Offset
27 #define XHC_PCI_BAR_MASK 0xFFFF // Memory Base Address Mask
29 #define USB_HUB_CLASS_CODE 0x09
30 #define USB_HUB_SUBCLASS_CODE 0x00
32 //============================================//
33 // XHCI register offset //
34 //============================================//
37 // Capability registers offset
39 #define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset
40 #define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h
41 #define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1
42 #define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2
43 #define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3
44 #define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters
45 #define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset
46 #define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset
49 // Operational registers offset
51 #define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset
52 #define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset
53 #define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset
54 #define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset
55 #define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset
56 #define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset
57 #define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset
58 #define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset
61 // Runtime registers offset
63 #define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset
64 #define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset
65 #define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset
66 #define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset
67 #define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset
68 #define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset
70 #define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore
71 #define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore
75 // Structural Parameters 1 Register Bitmap Definition
77 typedef union _XHC_HCSPARAMS1
{
80 UINT8 MaxSlots
; // Number of Device Slots
81 UINT16 MaxIntrs
:11; // Number of Interrupters
83 UINT8 MaxPorts
; // Number of Ports
88 // Structural Parameters 2 Register Bitmap Definition
90 typedef union _XHC_HCSPARAMS2
{
93 UINT32 Ist
:4; // Isochronous Scheduling Threshold
94 UINT32 Erst
:4; // Event Ring Segment Table Max
96 UINT32 ScratchBufHi
:5; // Max Scratchpad Buffers Hi
97 UINT32 Spr
:1; // Scratchpad Restore
98 UINT32 ScratchBufLo
:5; // Max Scratchpad Buffers Lo
103 // Capability Parameters Register Bitmap Definition
105 typedef union _XHC_HCCPARAMS
{
108 UINT16 Ac64
:1; // 64-bit Addressing Capability
109 UINT16 Bnc
:1; // BW Negotiation Capability
110 UINT16 Csz
:1; // Context Size
111 UINT16 Ppc
:1; // Port Power Control
112 UINT16 Pind
:1; // Port Indicators
113 UINT16 Lhrc
:1; // Light HC Reset Capability
114 UINT16 Ltc
:1; // Latency Tolerance Messaging Capability
115 UINT16 Nss
:1; // No Secondary SID Support
116 UINT16 Pae
:1; // Parse All Event Data
118 UINT16 MaxPsaSize
:4; // Maximum Primary Stream Array Size
119 UINT16 ExtCapReg
; // xHCI Extended Capabilities Pointer
126 // Register Bit Definition
128 #define XHC_USBCMD_RUN BIT0 // Run/Stop
129 #define XHC_USBCMD_RESET BIT1 // Host Controller Reset
130 #define XHC_USBCMD_INTE BIT2 // Interrupter Enable
131 #define XHC_USBCMD_HSEE BIT3 // Host System Error Enable
133 #define XHC_USBSTS_HALT BIT0 // Host Controller Halted
134 #define XHC_USBSTS_HSE BIT2 // Host System Error
135 #define XHC_USBSTS_EINT BIT3 // Event Interrupt
136 #define XHC_USBSTS_PCD BIT4 // Port Change Detect
137 #define XHC_USBSTS_SSS BIT8 // Save State Status
138 #define XHC_USBSTS_RSS BIT9 // Restore State Status
139 #define XHC_USBSTS_SRE BIT10 // Save/Restore Error
140 #define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready
141 #define XHC_USBSTS_HCE BIT12 // Host Controller Error
143 #define XHC_PAGESIZE_MASK 0xFFFF // Page Size
145 #define XHC_CRCR_RCS BIT0 // Ring Cycle State
146 #define XHC_CRCR_CS BIT1 // Command Stop
147 #define XHC_CRCR_CA BIT2 // Command Abort
148 #define XHC_CRCR_CRR BIT3 // Command Ring Running
150 #define XHC_CONFIG_MASK 0xFF // Command Ring Running
152 #define XHC_PORTSC_CCS BIT0 // Current Connect Status
153 #define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled
154 #define XHC_PORTSC_OCA BIT3 // Over-current Active
155 #define XHC_PORTSC_RESET BIT4 // Port Reset
156 #define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State
157 #define XHC_PORTSC_PP BIT9 // Port Power
158 #define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // Port Speed
159 #define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe
160 #define XHC_PORTSC_CSC BIT17 // Connect Status Change
161 #define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change
162 #define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change
163 #define XHC_PORTSC_OCC BIT20 // Over-Current Change
164 #define XHC_PORTSC_PRC BIT21 // Port Reset Change
165 #define XHC_PORTSC_PLC BIT22 // Port Link State Change
166 #define XHC_PORTSC_CEC BIT23 // Port Config Error Change
167 #define XHC_PORTSC_CAS BIT24 // Cold Attach Status
169 #define XHC_IMAN_IP BIT0 // Interrupt Pending
170 #define XHC_IMAN_IE BIT1 // Interrupt Enable
172 #define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval
173 #define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter
176 // Structure to map the hardware port states to the
177 // UEFI's port states.
182 } USB_PORT_STATE_MAP
;
185 Read 1-byte width XHCI capability register.
187 @param Xhc The XHCI device.
188 @param Offset The offset of the 1-byte width capability register.
190 @return The register content read.
191 @retval If err, return 0xFFFF.
196 IN USB_XHCI_DEV
*Xhc
,
201 Read 4-bytes width XHCI capability register.
203 @param Xhc The XHCI device.
204 @param Offset The offset of the 4-bytes width capability register.
206 @return The register content read.
207 @retval If err, return 0xFFFFFFFF.
212 IN USB_XHCI_DEV
*Xhc
,
217 Read 4-bytes width XHCI Operational register.
219 @param Xhc The XHCI device.
220 @param Offset The offset of the 4-bytes width operational register.
222 @return The register content read.
223 @retval If err, return 0xFFFFFFFF.
228 IN USB_XHCI_DEV
*Xhc
,
233 Write the data to the 4-bytes width XHCI operational register.
235 @param Xhc The XHCI device.
236 @param Offset The offset of the 4-bytes width operational register.
237 @param Data The data to write.
242 IN USB_XHCI_DEV
*Xhc
,
248 Write the data to the 2-bytes width XHCI operational register.
250 @param Xhc The XHCI device.
251 @param Offset The offset of the 2-bytes width operational register.
252 @param Data The data to write.
257 IN USB_XHCI_DEV
*Xhc
,
263 Write the data to the 8-bytes width XHCI operational register.
265 @param Xhc The XHCI device.
266 @param Offset The offset of the 8-bytes width operational register.
267 @param Data The data to write.
272 IN USB_XHCI_DEV
*Xhc
,
278 Read XHCI runtime register.
280 @param Xhc The XHCI device.
281 @param Offset The offset of the runtime register.
283 @return The register content read
288 IN USB_XHCI_DEV
*Xhc
,
293 Read 8-bytes width XHCI runtime register.
295 @param Xhc The XHCI device.
296 @param Offset The offset of the 8-bytes width runtime register.
298 @return The register content read
302 XhcReadRuntimeReg64 (
303 IN USB_XHCI_DEV
*Xhc
,
308 Write the data to the XHCI runtime register.
310 @param Xhc The XHCI device.
311 @param Offset The offset of the runtime register.
312 @param Data The data to write.
317 IN USB_XHCI_DEV
*Xhc
,
323 Write the data to the 8-bytes width XHCI runtime register.
325 @param Xhc The XHCI device.
326 @param Offset The offset of the 8-bytes width runtime register.
327 @param Data The data to write.
331 XhcWriteRuntimeReg64 (
332 IN USB_XHCI_DEV
*Xhc
,
338 Read XHCI door bell register.
340 @param Xhc The XHCI device.
341 @param Offset The offset of the door bell register.
343 @return The register content read
348 IN USB_XHCI_DEV
*Xhc
,
353 Write the data to the XHCI door bell register.
355 @param Xhc The XHCI device.
356 @param Offset The offset of the door bell register.
357 @param Data The data to write.
361 XhcWriteDoorBellReg (
362 IN USB_XHCI_DEV
*Xhc
,
368 Set one bit of the operational register while keeping other bits.
370 @param Xhc The XHCI device.
371 @param Offset The offset of the operational register.
372 @param Bit The bit mask of the register to set.
377 IN USB_XHCI_DEV
*Xhc
,
383 Clear one bit of the operational register while keeping other bits.
385 @param Xhc The XHCI device.
386 @param Offset The offset of the operational register.
387 @param Bit The bit mask of the register to clear.
392 IN USB_XHCI_DEV
*Xhc
,
398 Wait the operation register's bit as specified by Bit
399 to be set (or clear).
401 @param Xhc The XHCI device.
402 @param Offset The offset of the operational register.
403 @param Bit The bit of the register to wait for.
404 @param WaitToSet Wait the bit to set or clear.
405 @param Timeout The time to wait before abort (in millisecond, ms).
407 @retval EFI_SUCCESS The bit successfully changed by host controller.
408 @retval EFI_TIMEOUT The time out occurred.
413 IN USB_XHCI_DEV
*Xhc
,
416 IN BOOLEAN WaitToSet
,
421 Read XHCI runtime register.
423 @param Xhc The XHCI device.
424 @param Offset The offset of the runtime register.
426 @return The register content read
431 IN USB_XHCI_DEV
*Xhc
,
436 Write the data to the XHCI runtime register.
438 @param Xhc The XHCI device.
439 @param Offset The offset of the runtime register.
440 @param Data The data to write.
445 IN USB_XHCI_DEV
*Xhc
,
451 Set one bit of the runtime register while keeping other bits.
453 @param Xhc The XHCI device.
454 @param Offset The offset of the runtime register.
455 @param Bit The bit mask of the register to set.
459 XhcSetRuntimeRegBit (
460 IN USB_XHCI_DEV
*Xhc
,
466 Clear one bit of the runtime register while keeping other bits.
468 @param Xhc The XHCI device.
469 @param Offset The offset of the runtime register.
470 @param Bit The bit mask of the register to set.
474 XhcClearRuntimeRegBit (
475 IN USB_XHCI_DEV
*Xhc
,
481 Whether the XHCI host controller is halted.
483 @param Xhc The XHCI device.
485 @retval TRUE The controller is halted.
486 @retval FALSE It isn't halted.
495 Whether system error occurred.
497 @param Xhc The XHCI device.
499 @retval TRUE System error happened.
500 @retval FALSE No system error.
509 Reset the XHCI host controller.
511 @param Xhc The XHCI device.
512 @param Timeout Time to wait before abort (in millisecond, ms).
514 @retval EFI_SUCCESS The XHCI host controller is reset.
515 @return Others Failed to reset the XHCI before Timeout.
520 IN USB_XHCI_DEV
*Xhc
,
525 Halt the XHCI host controller.
527 @param Xhc The XHCI device.
528 @param Timeout Time to wait before abort (in millisecond, ms).
530 @return EFI_SUCCESS The XHCI host controller is halt.
531 @return EFI_TIMEOUT Failed to halt the XHCI before Timeout.
536 IN USB_XHCI_DEV
*Xhc
,
541 Set the XHCI host controller to run.
543 @param Xhc The XHCI device.
544 @param Timeout Time to wait before abort (in millisecond, ms).
546 @return EFI_SUCCESS The XHCI host controller is running.
547 @return EFI_TIMEOUT Failed to set the XHCI to run before Timeout.
552 IN USB_XHCI_DEV
*Xhc
,
557 Calculate the XHCI legacy support capability register offset.
559 @param Xhc The XHCI device.
561 @return The offset of XHCI legacy support capability register.
565 XhcGetLegSupCapAddr (