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1 /** @file
2
3 This file contains the definition for XHCI host controller schedule routines.
4
5 Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
7
8 **/
9
10 #ifndef _EFI_XHCI_SCHED_H_
11 #define _EFI_XHCI_SCHED_H_
12
13 #define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
14 #define XHC_INIT_DEVICE_SLOT_RETRIES 1
15
16 //
17 // Transfer types, used in URB to identify the transfer type
18 //
19 #define XHC_CTRL_TRANSFER 0x01
20 #define XHC_BULK_TRANSFER 0x02
21 #define XHC_INT_TRANSFER_SYNC 0x04
22 #define XHC_INT_TRANSFER_ASYNC 0x08
23 #define XHC_INT_ONLY_TRANSFER_ASYNC 0x10
24
25 //
26 // 6.4.6 TRB Types
27 //
28 #define TRB_TYPE_NORMAL 1
29 #define TRB_TYPE_SETUP_STAGE 2
30 #define TRB_TYPE_DATA_STAGE 3
31 #define TRB_TYPE_STATUS_STAGE 4
32 #define TRB_TYPE_ISOCH 5
33 #define TRB_TYPE_LINK 6
34 #define TRB_TYPE_EVENT_DATA 7
35 #define TRB_TYPE_NO_OP 8
36 #define TRB_TYPE_EN_SLOT 9
37 #define TRB_TYPE_DIS_SLOT 10
38 #define TRB_TYPE_ADDRESS_DEV 11
39 #define TRB_TYPE_CON_ENDPOINT 12
40 #define TRB_TYPE_EVALU_CONTXT 13
41 #define TRB_TYPE_RESET_ENDPOINT 14
42 #define TRB_TYPE_STOP_ENDPOINT 15
43 #define TRB_TYPE_SET_TR_DEQUE 16
44 #define TRB_TYPE_RESET_DEV 17
45 #define TRB_TYPE_GET_PORT_BANW 21
46 #define TRB_TYPE_FORCE_HEADER 22
47 #define TRB_TYPE_NO_OP_COMMAND 23
48 #define TRB_TYPE_TRANS_EVENT 32
49 #define TRB_TYPE_COMMAND_COMPLT_EVENT 33
50 #define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34
51 #define TRB_TYPE_HOST_CONTROLLER_EVENT 37
52 #define TRB_TYPE_DEVICE_NOTIFI_EVENT 38
53 #define TRB_TYPE_MFINDEX_WRAP_EVENT 39
54
55 //
56 // Endpoint Type (EP Type).
57 //
58 #define ED_NOT_VALID 0
59 #define ED_ISOCH_OUT 1
60 #define ED_BULK_OUT 2
61 #define ED_INTERRUPT_OUT 3
62 #define ED_CONTROL_BIDIR 4
63 #define ED_ISOCH_IN 5
64 #define ED_BULK_IN 6
65 #define ED_INTERRUPT_IN 7
66
67 //
68 // 6.4.5 TRB Completion Codes
69 //
70 #define TRB_COMPLETION_INVALID 0
71 #define TRB_COMPLETION_SUCCESS 1
72 #define TRB_COMPLETION_DATA_BUFFER_ERROR 2
73 #define TRB_COMPLETION_BABBLE_ERROR 3
74 #define TRB_COMPLETION_USB_TRANSACTION_ERROR 4
75 #define TRB_COMPLETION_TRB_ERROR 5
76 #define TRB_COMPLETION_STALL_ERROR 6
77 #define TRB_COMPLETION_SHORT_PACKET 13
78 #define TRB_COMPLETION_STOPPED 26
79 #define TRB_COMPLETION_STOPPED_LENGTH_INVALID 27
80
81 //
82 // The topology string used to present usb device location
83 //
84 typedef struct _USB_DEV_TOPOLOGY {
85 //
86 // The tier concatenation of down stream port.
87 //
88 UINT32 RouteString:20;
89 //
90 // The root port number of the chain.
91 //
92 UINT32 RootPortNum:8;
93 //
94 // The Tier the device reside.
95 //
96 UINT32 TierNum:4;
97 } USB_DEV_TOPOLOGY;
98
99 //
100 // USB Device's RouteChart
101 //
102 typedef union _USB_DEV_ROUTE {
103 UINT32 Dword;
104 USB_DEV_TOPOLOGY Route;
105 } USB_DEV_ROUTE;
106
107 //
108 // Endpoint address and its capabilities
109 //
110 typedef struct _USB_ENDPOINT {
111 //
112 // Store logical device address assigned by UsbBus
113 // It's because some XHCI host controllers may assign the same physcial device
114 // address for those devices inserted at different root port.
115 //
116 UINT8 BusAddr;
117 UINT8 DevAddr;
118 UINT8 EpAddr;
119 EFI_USB_DATA_DIRECTION Direction;
120 UINT8 DevSpeed;
121 UINTN MaxPacket;
122 UINTN Type;
123 } USB_ENDPOINT;
124
125 //
126 // TRB Template
127 //
128 typedef struct _TRB_TEMPLATE {
129 UINT32 Parameter1;
130
131 UINT32 Parameter2;
132
133 UINT32 Status;
134
135 UINT32 CycleBit:1;
136 UINT32 RsvdZ1:9;
137 UINT32 Type:6;
138 UINT32 Control:16;
139 } TRB_TEMPLATE;
140
141 typedef struct _TRANSFER_RING {
142 VOID *RingSeg0;
143 UINTN TrbNumber;
144 TRB_TEMPLATE *RingEnqueue;
145 TRB_TEMPLATE *RingDequeue;
146 UINT32 RingPCS;
147 } TRANSFER_RING;
148
149 typedef struct _EVENT_RING {
150 VOID *ERSTBase;
151 VOID *EventRingSeg0;
152 UINTN TrbNumber;
153 TRB_TEMPLATE *EventRingEnqueue;
154 TRB_TEMPLATE *EventRingDequeue;
155 UINT32 EventRingCCS;
156 } EVENT_RING;
157
158 //
159 // URB (Usb Request Block) contains information for all kinds of
160 // usb requests.
161 //
162 typedef struct _URB {
163 UINT32 Signature;
164 LIST_ENTRY UrbList;
165 //
166 // Usb Device URB related information
167 //
168 USB_ENDPOINT Ep;
169 EFI_USB_DEVICE_REQUEST *Request;
170 VOID *Data;
171 UINTN DataLen;
172 VOID *DataPhy;
173 VOID *DataMap;
174 EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
175 VOID *Context;
176 //
177 // Execute result
178 //
179 UINT32 Result;
180 //
181 // completed data length
182 //
183 UINTN Completed;
184 //
185 // Command/Tranfer Ring info
186 //
187 TRANSFER_RING *Ring;
188 TRB_TEMPLATE *TrbStart;
189 TRB_TEMPLATE *TrbEnd;
190 UINTN TrbNum;
191 BOOLEAN StartDone;
192 BOOLEAN EndDone;
193 BOOLEAN Finished;
194
195 TRB_TEMPLATE *EvtTrb;
196 } URB;
197
198 //
199 // 6.5 Event Ring Segment Table
200 // The Event Ring Segment Table is used to define multi-segment Event Rings and to enable runtime
201 // expansion and shrinking of the Event Ring. The location of the Event Ring Segment Table is defined by the
202 // Event Ring Segment Table Base Address Register (5.5.2.3.2). The size of the Event Ring Segment Table
203 // is defined by the Event Ring Segment Table Base Size Register (5.5.2.3.1).
204 //
205 typedef struct _EVENT_RING_SEG_TABLE_ENTRY {
206 UINT32 PtrLo;
207 UINT32 PtrHi;
208 UINT32 RingTrbSize:16;
209 UINT32 RsvdZ1:16;
210 UINT32 RsvdZ2;
211 } EVENT_RING_SEG_TABLE_ENTRY;
212
213 //
214 // 6.4.1.1 Normal TRB
215 // A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and
216 // Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer
217 // Rings, and to define the Data stage information for Control Transfer Rings.
218 //
219 typedef struct _TRANSFER_TRB_NORMAL {
220 UINT32 TRBPtrLo;
221
222 UINT32 TRBPtrHi;
223
224 UINT32 Length:17;
225 UINT32 TDSize:5;
226 UINT32 IntTarget:10;
227
228 UINT32 CycleBit:1;
229 UINT32 ENT:1;
230 UINT32 ISP:1;
231 UINT32 NS:1;
232 UINT32 CH:1;
233 UINT32 IOC:1;
234 UINT32 IDT:1;
235 UINT32 RsvdZ1:2;
236 UINT32 BEI:1;
237 UINT32 Type:6;
238 UINT32 RsvdZ2:16;
239 } TRANSFER_TRB_NORMAL;
240
241 //
242 // 6.4.1.2.1 Setup Stage TRB
243 // A Setup Stage TRB is created by system software to initiate a USB Setup packet on a control endpoint.
244 //
245 typedef struct _TRANSFER_TRB_CONTROL_SETUP {
246 UINT32 bmRequestType:8;
247 UINT32 bRequest:8;
248 UINT32 wValue:16;
249
250 UINT32 wIndex:16;
251 UINT32 wLength:16;
252
253 UINT32 Length:17;
254 UINT32 RsvdZ1:5;
255 UINT32 IntTarget:10;
256
257 UINT32 CycleBit:1;
258 UINT32 RsvdZ2:4;
259 UINT32 IOC:1;
260 UINT32 IDT:1;
261 UINT32 RsvdZ3:3;
262 UINT32 Type:6;
263 UINT32 TRT:2;
264 UINT32 RsvdZ4:14;
265 } TRANSFER_TRB_CONTROL_SETUP;
266
267 //
268 // 6.4.1.2.2 Data Stage TRB
269 // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.
270 //
271 typedef struct _TRANSFER_TRB_CONTROL_DATA {
272 UINT32 TRBPtrLo;
273
274 UINT32 TRBPtrHi;
275
276 UINT32 Length:17;
277 UINT32 TDSize:5;
278 UINT32 IntTarget:10;
279
280 UINT32 CycleBit:1;
281 UINT32 ENT:1;
282 UINT32 ISP:1;
283 UINT32 NS:1;
284 UINT32 CH:1;
285 UINT32 IOC:1;
286 UINT32 IDT:1;
287 UINT32 RsvdZ1:3;
288 UINT32 Type:6;
289 UINT32 DIR:1;
290 UINT32 RsvdZ2:15;
291 } TRANSFER_TRB_CONTROL_DATA;
292
293 //
294 // 6.4.1.2.2 Data Stage TRB
295 // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.
296 //
297 typedef struct _TRANSFER_TRB_CONTROL_STATUS {
298 UINT32 RsvdZ1;
299 UINT32 RsvdZ2;
300
301 UINT32 RsvdZ3:22;
302 UINT32 IntTarget:10;
303
304 UINT32 CycleBit:1;
305 UINT32 ENT:1;
306 UINT32 RsvdZ4:2;
307 UINT32 CH:1;
308 UINT32 IOC:1;
309 UINT32 RsvdZ5:4;
310 UINT32 Type:6;
311 UINT32 DIR:1;
312 UINT32 RsvdZ6:15;
313 } TRANSFER_TRB_CONTROL_STATUS;
314
315 //
316 // 6.4.2.1 Transfer Event TRB
317 // A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1
318 // for more information on the use and operation of Transfer Events.
319 //
320 typedef struct _EVT_TRB_TRANSFER {
321 UINT32 TRBPtrLo;
322
323 UINT32 TRBPtrHi;
324
325 UINT32 Length:24;
326 UINT32 Completecode:8;
327
328 UINT32 CycleBit:1;
329 UINT32 RsvdZ1:1;
330 UINT32 ED:1;
331 UINT32 RsvdZ2:7;
332 UINT32 Type:6;
333 UINT32 EndpointId:5;
334 UINT32 RsvdZ3:3;
335 UINT32 SlotId:8;
336 } EVT_TRB_TRANSFER;
337
338 //
339 // 6.4.2.2 Command Completion Event TRB
340 // A Command Completion Event TRB shall be generated by the xHC when a command completes on the
341 // Command Ring. Refer to section 4.11.4 for more information on the use of Command Completion Events.
342 //
343 typedef struct _EVT_TRB_COMMAND_COMPLETION {
344 UINT32 TRBPtrLo;
345
346 UINT32 TRBPtrHi;
347
348 UINT32 RsvdZ2:24;
349 UINT32 Completecode:8;
350
351 UINT32 CycleBit:1;
352 UINT32 RsvdZ3:9;
353 UINT32 Type:6;
354 UINT32 VFID:8;
355 UINT32 SlotId:8;
356 } EVT_TRB_COMMAND_COMPLETION;
357
358 typedef union _TRB {
359 TRB_TEMPLATE TrbTemplate;
360 TRANSFER_TRB_NORMAL TrbNormal;
361 TRANSFER_TRB_CONTROL_SETUP TrbCtrSetup;
362 TRANSFER_TRB_CONTROL_DATA TrbCtrData;
363 TRANSFER_TRB_CONTROL_STATUS TrbCtrStatus;
364 } TRB;
365
366 //
367 // 6.4.3.1 No Op Command TRB
368 // The No Op Command TRB provides a simple means for verifying the operation of the Command Ring
369 // mechanisms offered by the xHCI.
370 //
371 typedef struct _CMD_TRB_NO_OP {
372 UINT32 RsvdZ0;
373 UINT32 RsvdZ1;
374 UINT32 RsvdZ2;
375
376 UINT32 CycleBit:1;
377 UINT32 RsvdZ3:9;
378 UINT32 Type:6;
379 UINT32 RsvdZ4:16;
380 } CMD_TRB_NO_OP;
381
382 //
383 // 6.4.3.2 Enable Slot Command TRB
384 // The Enable Slot Command TRB causes the xHC to select an available Device Slot and return the ID of the
385 // selected slot to the host in a Command Completion Event.
386 //
387 typedef struct _CMD_TRB_ENABLE_SLOT {
388 UINT32 RsvdZ0;
389 UINT32 RsvdZ1;
390 UINT32 RsvdZ2;
391
392 UINT32 CycleBit:1;
393 UINT32 RsvdZ3:9;
394 UINT32 Type:6;
395 UINT32 RsvdZ4:16;
396 } CMD_TRB_ENABLE_SLOT;
397
398 //
399 // 6.4.3.3 Disable Slot Command TRB
400 // The Disable Slot Command TRB releases any bandwidth assigned to the disabled slot and frees any
401 // internal xHC resources assigned to the slot.
402 //
403 typedef struct _CMD_TRB_DISABLE_SLOT {
404 UINT32 RsvdZ0;
405 UINT32 RsvdZ1;
406 UINT32 RsvdZ2;
407
408 UINT32 CycleBit:1;
409 UINT32 RsvdZ3:9;
410 UINT32 Type:6;
411 UINT32 RsvdZ4:8;
412 UINT32 SlotId:8;
413 } CMD_TRB_DISABLE_SLOT;
414
415 //
416 // 6.4.3.4 Address Device Command TRB
417 // The Address Device Command TRB transitions the selected Device Context from the Default to the
418 // Addressed state and causes the xHC to select an address for the USB device in the Default State and
419 // issue a SET_ADDRESS request to the USB device.
420 //
421 typedef struct _CMD_TRB_ADDRESS_DEVICE {
422 UINT32 PtrLo;
423
424 UINT32 PtrHi;
425
426 UINT32 RsvdZ1;
427
428 UINT32 CycleBit:1;
429 UINT32 RsvdZ2:8;
430 UINT32 BSR:1;
431 UINT32 Type:6;
432 UINT32 RsvdZ3:8;
433 UINT32 SlotId:8;
434 } CMD_TRB_ADDRESS_DEVICE;
435
436 //
437 // 6.4.3.5 Configure Endpoint Command TRB
438 // The Configure Endpoint Command TRB evaluates the bandwidth and resource requirements of the
439 // endpoints selected by the command.
440 //
441 typedef struct _CMD_TRB_CONFIG_ENDPOINT {
442 UINT32 PtrLo;
443
444 UINT32 PtrHi;
445
446 UINT32 RsvdZ1;
447
448 UINT32 CycleBit:1;
449 UINT32 RsvdZ2:8;
450 UINT32 DC:1;
451 UINT32 Type:6;
452 UINT32 RsvdZ3:8;
453 UINT32 SlotId:8;
454 } CMD_TRB_CONFIG_ENDPOINT;
455
456 //
457 // 6.4.3.6 Evaluate Context Command TRB
458 // The Evaluate Context Command TRB is used by system software to inform the xHC that the selected
459 // Context data structures in the Device Context have been modified by system software and that the xHC
460 // shall evaluate any changes
461 //
462 typedef struct _CMD_TRB_EVALUATE_CONTEXT {
463 UINT32 PtrLo;
464
465 UINT32 PtrHi;
466
467 UINT32 RsvdZ1;
468
469 UINT32 CycleBit:1;
470 UINT32 RsvdZ2:9;
471 UINT32 Type:6;
472 UINT32 RsvdZ3:8;
473 UINT32 SlotId:8;
474 } CMD_TRB_EVALUATE_CONTEXT;
475
476 //
477 // 6.4.3.7 Reset Endpoint Command TRB
478 // The Reset Endpoint Command TRB is used by system software to reset a specified Transfer Ring
479 //
480 typedef struct _CMD_TRB_RESET_ENDPOINT {
481 UINT32 RsvdZ0;
482 UINT32 RsvdZ1;
483 UINT32 RsvdZ2;
484
485 UINT32 CycleBit:1;
486 UINT32 RsvdZ3:8;
487 UINT32 TSP:1;
488 UINT32 Type:6;
489 UINT32 EDID:5;
490 UINT32 RsvdZ4:3;
491 UINT32 SlotId:8;
492 } CMD_TRB_RESET_ENDPOINT;
493
494 //
495 // 6.4.3.8 Stop Endpoint Command TRB
496 // The Stop Endpoint Command TRB command allows software to stop the xHC execution of the TDs on a
497 // Transfer Ring and temporarily take ownership of TDs that had previously been passed to the xHC.
498 //
499 typedef struct _CMD_TRB_STOP_ENDPOINT {
500 UINT32 RsvdZ0;
501 UINT32 RsvdZ1;
502 UINT32 RsvdZ2;
503
504 UINT32 CycleBit:1;
505 UINT32 RsvdZ3:9;
506 UINT32 Type:6;
507 UINT32 EDID:5;
508 UINT32 RsvdZ4:2;
509 UINT32 SP:1;
510 UINT32 SlotId:8;
511 } CMD_TRB_STOP_ENDPOINT;
512
513 //
514 // 6.4.3.9 Set TR Dequeue Pointer Command TRB
515 // The Set TR Dequeue Pointer Command TRB is used by system software to modify the TR Dequeue
516 // Pointer and DCS fields of an Endpoint or Stream Context.
517 //
518 typedef struct _CMD_SET_TR_DEQ_POINTER {
519 UINT32 PtrLo;
520
521 UINT32 PtrHi;
522
523 UINT32 RsvdZ1:16;
524 UINT32 StreamID:16;
525
526 UINT32 CycleBit:1;
527 UINT32 RsvdZ2:9;
528 UINT32 Type:6;
529 UINT32 Endpoint:5;
530 UINT32 RsvdZ3:3;
531 UINT32 SlotId:8;
532 } CMD_SET_TR_DEQ_POINTER;
533
534 //
535 // 6.4.4.1 Link TRB
536 // A Link TRB provides support for non-contiguous TRB Rings.
537 //
538 typedef struct _LINK_TRB {
539 UINT32 PtrLo;
540
541 UINT32 PtrHi;
542
543 UINT32 RsvdZ1:22;
544 UINT32 InterTarget:10;
545
546 UINT32 CycleBit:1;
547 UINT32 TC:1;
548 UINT32 RsvdZ2:2;
549 UINT32 CH:1;
550 UINT32 IOC:1;
551 UINT32 RsvdZ3:4;
552 UINT32 Type:6;
553 UINT32 RsvdZ4:16;
554 } LINK_TRB;
555
556 //
557 // 6.2.2 Slot Context
558 //
559 typedef struct _SLOT_CONTEXT {
560 UINT32 RouteString:20;
561 UINT32 Speed:4;
562 UINT32 RsvdZ1:1;
563 UINT32 MTT:1;
564 UINT32 Hub:1;
565 UINT32 ContextEntries:5;
566
567 UINT32 MaxExitLatency:16;
568 UINT32 RootHubPortNum:8;
569 UINT32 PortNum:8;
570
571 UINT32 TTHubSlotId:8;
572 UINT32 TTPortNum:8;
573 UINT32 TTT:2;
574 UINT32 RsvdZ2:4;
575 UINT32 InterTarget:10;
576
577 UINT32 DeviceAddress:8;
578 UINT32 RsvdZ3:19;
579 UINT32 SlotState:5;
580
581 UINT32 RsvdZ4;
582 UINT32 RsvdZ5;
583 UINT32 RsvdZ6;
584 UINT32 RsvdZ7;
585 } SLOT_CONTEXT;
586
587 typedef struct _SLOT_CONTEXT_64 {
588 UINT32 RouteString:20;
589 UINT32 Speed:4;
590 UINT32 RsvdZ1:1;
591 UINT32 MTT:1;
592 UINT32 Hub:1;
593 UINT32 ContextEntries:5;
594
595 UINT32 MaxExitLatency:16;
596 UINT32 RootHubPortNum:8;
597 UINT32 PortNum:8;
598
599 UINT32 TTHubSlotId:8;
600 UINT32 TTPortNum:8;
601 UINT32 TTT:2;
602 UINT32 RsvdZ2:4;
603 UINT32 InterTarget:10;
604
605 UINT32 DeviceAddress:8;
606 UINT32 RsvdZ3:19;
607 UINT32 SlotState:5;
608
609 UINT32 RsvdZ4;
610 UINT32 RsvdZ5;
611 UINT32 RsvdZ6;
612 UINT32 RsvdZ7;
613
614 UINT32 RsvdZ8;
615 UINT32 RsvdZ9;
616 UINT32 RsvdZ10;
617 UINT32 RsvdZ11;
618
619 UINT32 RsvdZ12;
620 UINT32 RsvdZ13;
621 UINT32 RsvdZ14;
622 UINT32 RsvdZ15;
623
624 } SLOT_CONTEXT_64;
625
626
627 //
628 // 6.2.3 Endpoint Context
629 //
630 typedef struct _ENDPOINT_CONTEXT {
631 UINT32 EPState:3;
632 UINT32 RsvdZ1:5;
633 UINT32 Mult:2;
634 UINT32 MaxPStreams:5;
635 UINT32 LSA:1;
636 UINT32 Interval:8;
637 UINT32 RsvdZ2:8;
638
639 UINT32 RsvdZ3:1;
640 UINT32 CErr:2;
641 UINT32 EPType:3;
642 UINT32 RsvdZ4:1;
643 UINT32 HID:1;
644 UINT32 MaxBurstSize:8;
645 UINT32 MaxPacketSize:16;
646
647 UINT32 PtrLo;
648
649 UINT32 PtrHi;
650
651 UINT32 AverageTRBLength:16;
652 UINT32 MaxESITPayload:16;
653
654 UINT32 RsvdZ5;
655 UINT32 RsvdZ6;
656 UINT32 RsvdZ7;
657 } ENDPOINT_CONTEXT;
658
659 typedef struct _ENDPOINT_CONTEXT_64 {
660 UINT32 EPState:3;
661 UINT32 RsvdZ1:5;
662 UINT32 Mult:2;
663 UINT32 MaxPStreams:5;
664 UINT32 LSA:1;
665 UINT32 Interval:8;
666 UINT32 RsvdZ2:8;
667
668 UINT32 RsvdZ3:1;
669 UINT32 CErr:2;
670 UINT32 EPType:3;
671 UINT32 RsvdZ4:1;
672 UINT32 HID:1;
673 UINT32 MaxBurstSize:8;
674 UINT32 MaxPacketSize:16;
675
676 UINT32 PtrLo;
677
678 UINT32 PtrHi;
679
680 UINT32 AverageTRBLength:16;
681 UINT32 MaxESITPayload:16;
682
683 UINT32 RsvdZ5;
684 UINT32 RsvdZ6;
685 UINT32 RsvdZ7;
686
687 UINT32 RsvdZ8;
688 UINT32 RsvdZ9;
689 UINT32 RsvdZ10;
690 UINT32 RsvdZ11;
691
692 UINT32 RsvdZ12;
693 UINT32 RsvdZ13;
694 UINT32 RsvdZ14;
695 UINT32 RsvdZ15;
696
697 } ENDPOINT_CONTEXT_64;
698
699
700 //
701 // 6.2.5.1 Input Control Context
702 //
703 typedef struct _INPUT_CONTRL_CONTEXT {
704 UINT32 Dword1;
705 UINT32 Dword2;
706 UINT32 RsvdZ1;
707 UINT32 RsvdZ2;
708 UINT32 RsvdZ3;
709 UINT32 RsvdZ4;
710 UINT32 RsvdZ5;
711 UINT32 RsvdZ6;
712 } INPUT_CONTRL_CONTEXT;
713
714 typedef struct _INPUT_CONTRL_CONTEXT_64 {
715 UINT32 Dword1;
716 UINT32 Dword2;
717 UINT32 RsvdZ1;
718 UINT32 RsvdZ2;
719 UINT32 RsvdZ3;
720 UINT32 RsvdZ4;
721 UINT32 RsvdZ5;
722 UINT32 RsvdZ6;
723 UINT32 RsvdZ7;
724 UINT32 RsvdZ8;
725 UINT32 RsvdZ9;
726 UINT32 RsvdZ10;
727 UINT32 RsvdZ11;
728 UINT32 RsvdZ12;
729 UINT32 RsvdZ13;
730 UINT32 RsvdZ14;
731 } INPUT_CONTRL_CONTEXT_64;
732
733 //
734 // 6.2.1 Device Context
735 //
736 typedef struct _DEVICE_CONTEXT {
737 SLOT_CONTEXT Slot;
738 ENDPOINT_CONTEXT EP[31];
739 } DEVICE_CONTEXT;
740
741 typedef struct _DEVICE_CONTEXT_64 {
742 SLOT_CONTEXT_64 Slot;
743 ENDPOINT_CONTEXT_64 EP[31];
744 } DEVICE_CONTEXT_64;
745
746 //
747 // 6.2.5 Input Context
748 //
749 typedef struct _INPUT_CONTEXT {
750 INPUT_CONTRL_CONTEXT InputControlContext;
751 SLOT_CONTEXT Slot;
752 ENDPOINT_CONTEXT EP[31];
753 } INPUT_CONTEXT;
754
755 typedef struct _INPUT_CONTEXT_64 {
756 INPUT_CONTRL_CONTEXT_64 InputControlContext;
757 SLOT_CONTEXT_64 Slot;
758 ENDPOINT_CONTEXT_64 EP[31];
759 } INPUT_CONTEXT_64;
760
761
762 /**
763 Initialize the XHCI host controller for schedule.
764
765 @param Xhc The XHCI Instance to be initialized.
766
767 **/
768 VOID
769 XhcInitSched (
770 IN USB_XHCI_INSTANCE *Xhc
771 );
772
773 /**
774 Free the resouce allocated at initializing schedule.
775
776 @param Xhc The XHCI Instance.
777
778 **/
779 VOID
780 XhcFreeSched (
781 IN USB_XHCI_INSTANCE *Xhc
782 );
783
784 /**
785 Ring the door bell to notify XHCI there is a transaction to be executed through URB.
786
787 @param Xhc The XHCI Instance.
788 @param Urb The URB to be rung.
789
790 @retval EFI_SUCCESS Successfully ring the door bell.
791
792 **/
793 EFI_STATUS
794 RingIntTransferDoorBell (
795 IN USB_XHCI_INSTANCE *Xhc,
796 IN URB *Urb
797 );
798
799 /**
800 Execute the transfer by polling the URB. This is a synchronous operation.
801
802 @param Xhc The XHCI Instance.
803 @param CmdTransfer The executed URB is for cmd transfer or not.
804 @param Urb The URB to execute.
805 @param Timeout The time to wait before abort, in millisecond.
806
807 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.
808 @return EFI_TIMEOUT The transfer failed due to time out.
809 @return EFI_SUCCESS The transfer finished OK.
810
811 **/
812 EFI_STATUS
813 XhcExecTransfer (
814 IN USB_XHCI_INSTANCE *Xhc,
815 IN BOOLEAN CmdTransfer,
816 IN URB *Urb,
817 IN UINTN Timeout
818 );
819
820 /**
821 Delete a single asynchronous interrupt transfer for
822 the device and endpoint.
823
824 @param Xhc The XHCI Instance.
825 @param BusAddr The logical device address assigned by UsbBus driver.
826 @param EpNum The endpoint of the target.
827
828 @retval EFI_SUCCESS An asynchronous transfer is removed.
829 @retval EFI_NOT_FOUND No transfer for the device is found.
830
831 **/
832 EFI_STATUS
833 XhciDelAsyncIntTransfer (
834 IN USB_XHCI_INSTANCE *Xhc,
835 IN UINT8 BusAddr,
836 IN UINT8 EpNum
837 );
838
839 /**
840 Remove all the asynchronous interrupt transfers.
841
842 @param Xhc The XHCI Instance.
843
844 **/
845 VOID
846 XhciDelAllAsyncIntTransfers (
847 IN USB_XHCI_INSTANCE *Xhc
848 );
849
850 /**
851 Insert a single asynchronous interrupt transfer for
852 the device and endpoint.
853
854 @param Xhc The XHCI Instance
855 @param BusAddr The logical device address assigned by UsbBus driver
856 @param EpAddr Endpoint addrress
857 @param DevSpeed The device speed
858 @param MaxPacket The max packet length of the endpoint
859 @param DataLen The length of data buffer
860 @param Callback The function to call when data is transferred
861 @param Context The context to the callback
862
863 @return Created URB or NULL
864
865 **/
866 URB *
867 XhciInsertAsyncIntTransfer (
868 IN USB_XHCI_INSTANCE *Xhc,
869 IN UINT8 BusAddr,
870 IN UINT8 EpAddr,
871 IN UINT8 DevSpeed,
872 IN UINTN MaxPacket,
873 IN UINTN DataLen,
874 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
875 IN VOID *Context
876 );
877
878 /**
879 Set Bios Ownership
880
881 @param Xhc The XHCI Instance.
882
883 **/
884 VOID
885 XhcSetBiosOwnership (
886 IN USB_XHCI_INSTANCE *Xhc
887 );
888
889 /**
890 Clear Bios Ownership
891
892 @param Xhc The XHCI Instance.
893
894 **/
895 VOID
896 XhcClearBiosOwnership (
897 IN USB_XHCI_INSTANCE *Xhc
898 );
899
900 /**
901 Find out the slot id according to the device's route string.
902
903 @param Xhc The XHCI Instance.
904 @param RouteString The route string described the device location.
905
906 @return The slot id used by the device.
907
908 **/
909 UINT8
910 EFIAPI
911 XhcRouteStringToSlotId (
912 IN USB_XHCI_INSTANCE *Xhc,
913 IN USB_DEV_ROUTE RouteString
914 );
915
916 /**
917 Calculate the device context index by endpoint address and direction.
918
919 @param EpAddr The target endpoint number.
920 @param Direction The direction of the target endpoint.
921
922 @return The device context index of endpoint.
923
924 **/
925 UINT8
926 XhcEndpointToDci (
927 IN UINT8 EpAddr,
928 IN UINT8 Direction
929 );
930
931 /**
932 Ring the door bell to notify XHCI there is a transaction to be executed.
933
934 @param Xhc The XHCI Instance.
935 @param SlotId The slot id of the target device.
936 @param Dci The device context index of the target slot or endpoint.
937
938 @retval EFI_SUCCESS Successfully ring the door bell.
939
940 **/
941 EFI_STATUS
942 EFIAPI
943 XhcRingDoorBell (
944 IN USB_XHCI_INSTANCE *Xhc,
945 IN UINT8 SlotId,
946 IN UINT8 Dci
947 );
948
949 /**
950 Interrupt transfer periodic check handler.
951
952 @param Event Interrupt event.
953 @param Context Pointer to USB_XHCI_INSTANCE.
954
955 **/
956 VOID
957 EFIAPI
958 XhcMonitorAsyncRequests (
959 IN EFI_EVENT Event,
960 IN VOID *Context
961 );
962
963 /**
964 Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.
965
966 @param Xhc The XHCI Instance.
967 @param ParentRouteChart The route string pointed to the parent device if it exists.
968 @param Port The port to be polled.
969 @param PortState The port state.
970
971 @retval EFI_SUCCESS Successfully enable/disable device slot according to port state.
972 @retval Others Should not appear.
973
974 **/
975 EFI_STATUS
976 EFIAPI
977 XhcPollPortStatusChange (
978 IN USB_XHCI_INSTANCE *Xhc,
979 IN USB_DEV_ROUTE ParentRouteChart,
980 IN UINT8 Port,
981 IN EFI_USB_PORT_STATUS *PortState
982 );
983
984 /**
985 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
986
987 @param Xhc The XHCI Instance.
988 @param SlotId The slot id to be configured.
989 @param PortNum The total number of downstream port supported by the hub.
990 @param TTT The TT think time of the hub device.
991 @param MTT The multi-TT of the hub device.
992
993 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
994
995 **/
996 EFI_STATUS
997 XhcConfigHubContext (
998 IN USB_XHCI_INSTANCE *Xhc,
999 IN UINT8 SlotId,
1000 IN UINT8 PortNum,
1001 IN UINT8 TTT,
1002 IN UINT8 MTT
1003 );
1004
1005
1006 /**
1007 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
1008
1009 @param Xhc The XHCI Instance.
1010 @param SlotId The slot id to be configured.
1011 @param PortNum The total number of downstream port supported by the hub.
1012 @param TTT The TT think time of the hub device.
1013 @param MTT The multi-TT of the hub device.
1014
1015 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
1016
1017 **/
1018 EFI_STATUS
1019 XhcConfigHubContext64 (
1020 IN USB_XHCI_INSTANCE *Xhc,
1021 IN UINT8 SlotId,
1022 IN UINT8 PortNum,
1023 IN UINT8 TTT,
1024 IN UINT8 MTT
1025 );
1026
1027
1028 /**
1029 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
1030
1031 @param Xhc The XHCI Instance.
1032 @param SlotId The slot id to be configured.
1033 @param DeviceSpeed The device's speed.
1034 @param ConfigDesc The pointer to the usb device configuration descriptor.
1035
1036 @retval EFI_SUCCESS Successfully configure all the device endpoints.
1037
1038 **/
1039 EFI_STATUS
1040 EFIAPI
1041 XhcSetConfigCmd (
1042 IN USB_XHCI_INSTANCE *Xhc,
1043 IN UINT8 SlotId,
1044 IN UINT8 DeviceSpeed,
1045 IN USB_CONFIG_DESCRIPTOR *ConfigDesc
1046 );
1047
1048
1049 /**
1050 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
1051
1052 @param Xhc The XHCI Instance.
1053 @param SlotId The slot id to be configured.
1054 @param DeviceSpeed The device's speed.
1055 @param ConfigDesc The pointer to the usb device configuration descriptor.
1056
1057 @retval EFI_SUCCESS Successfully configure all the device endpoints.
1058
1059 **/
1060 EFI_STATUS
1061 EFIAPI
1062 XhcSetConfigCmd64 (
1063 IN USB_XHCI_INSTANCE *Xhc,
1064 IN UINT8 SlotId,
1065 IN UINT8 DeviceSpeed,
1066 IN USB_CONFIG_DESCRIPTOR *ConfigDesc
1067 );
1068
1069 /**
1070 Set interface through XHCI's Configure_Endpoint cmd.
1071
1072 @param Xhc The XHCI Instance.
1073 @param SlotId The slot id to be configured.
1074 @param DeviceSpeed The device's speed.
1075 @param ConfigDesc The pointer to the usb device configuration descriptor.
1076 @param Request USB device request to send.
1077
1078 @retval EFI_SUCCESS Successfully set interface.
1079
1080 **/
1081 EFI_STATUS
1082 EFIAPI
1083 XhcSetInterface (
1084 IN USB_XHCI_INSTANCE *Xhc,
1085 IN UINT8 SlotId,
1086 IN UINT8 DeviceSpeed,
1087 IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
1088 IN EFI_USB_DEVICE_REQUEST *Request
1089 );
1090
1091 /**
1092 Set interface through XHCI's Configure_Endpoint cmd.
1093
1094 @param Xhc The XHCI Instance.
1095 @param SlotId The slot id to be configured.
1096 @param DeviceSpeed The device's speed.
1097 @param ConfigDesc The pointer to the usb device configuration descriptor.
1098 @param Request USB device request to send.
1099
1100 @retval EFI_SUCCESS Successfully set interface.
1101
1102 **/
1103 EFI_STATUS
1104 EFIAPI
1105 XhcSetInterface64 (
1106 IN USB_XHCI_INSTANCE *Xhc,
1107 IN UINT8 SlotId,
1108 IN UINT8 DeviceSpeed,
1109 IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
1110 IN EFI_USB_DEVICE_REQUEST *Request
1111 );
1112
1113 /**
1114 Find out the actual device address according to the requested device address from UsbBus.
1115
1116 @param Xhc The XHCI Instance.
1117 @param BusDevAddr The requested device address by UsbBus upper driver.
1118
1119 @return The actual device address assigned to the device.
1120
1121 **/
1122 UINT8
1123 EFIAPI
1124 XhcBusDevAddrToSlotId (
1125 IN USB_XHCI_INSTANCE *Xhc,
1126 IN UINT8 BusDevAddr
1127 );
1128
1129 /**
1130 Assign and initialize the device slot for a new device.
1131
1132 @param Xhc The XHCI Instance.
1133 @param ParentRouteChart The route string pointed to the parent device.
1134 @param ParentPort The port at which the device is located.
1135 @param RouteChart The route string pointed to the device.
1136 @param DeviceSpeed The device speed.
1137
1138 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
1139
1140 **/
1141 EFI_STATUS
1142 EFIAPI
1143 XhcInitializeDeviceSlot (
1144 IN USB_XHCI_INSTANCE *Xhc,
1145 IN USB_DEV_ROUTE ParentRouteChart,
1146 IN UINT16 ParentPort,
1147 IN USB_DEV_ROUTE RouteChart,
1148 IN UINT8 DeviceSpeed
1149 );
1150
1151 /**
1152 Assign and initialize the device slot for a new device.
1153
1154 @param Xhc The XHCI Instance.
1155 @param ParentRouteChart The route string pointed to the parent device.
1156 @param ParentPort The port at which the device is located.
1157 @param RouteChart The route string pointed to the device.
1158 @param DeviceSpeed The device speed.
1159
1160 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
1161
1162 **/
1163 EFI_STATUS
1164 EFIAPI
1165 XhcInitializeDeviceSlot64 (
1166 IN USB_XHCI_INSTANCE *Xhc,
1167 IN USB_DEV_ROUTE ParentRouteChart,
1168 IN UINT16 ParentPort,
1169 IN USB_DEV_ROUTE RouteChart,
1170 IN UINT8 DeviceSpeed
1171 );
1172
1173 /**
1174 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
1175
1176 @param Xhc The XHCI Instance.
1177 @param SlotId The slot id to be evaluated.
1178 @param MaxPacketSize The max packet size supported by the device control transfer.
1179
1180 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
1181
1182 **/
1183 EFI_STATUS
1184 EFIAPI
1185 XhcEvaluateContext (
1186 IN USB_XHCI_INSTANCE *Xhc,
1187 IN UINT8 SlotId,
1188 IN UINT32 MaxPacketSize
1189 );
1190
1191
1192 /**
1193 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
1194
1195 @param Xhc The XHCI Instance.
1196 @param SlotId The slot id to be evaluated.
1197 @param MaxPacketSize The max packet size supported by the device control transfer.
1198
1199 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
1200
1201 **/
1202 EFI_STATUS
1203 EFIAPI
1204 XhcEvaluateContext64 (
1205 IN USB_XHCI_INSTANCE *Xhc,
1206 IN UINT8 SlotId,
1207 IN UINT32 MaxPacketSize
1208 );
1209
1210
1211 /**
1212 Disable the specified device slot.
1213
1214 @param Xhc The XHCI Instance.
1215 @param SlotId The slot id to be disabled.
1216
1217 @retval EFI_SUCCESS Successfully disable the device slot.
1218
1219 **/
1220 EFI_STATUS
1221 EFIAPI
1222 XhcDisableSlotCmd (
1223 IN USB_XHCI_INSTANCE *Xhc,
1224 IN UINT8 SlotId
1225 );
1226
1227
1228 /**
1229 Disable the specified device slot.
1230
1231 @param Xhc The XHCI Instance.
1232 @param SlotId The slot id to be disabled.
1233
1234 @retval EFI_SUCCESS Successfully disable the device slot.
1235
1236 **/
1237 EFI_STATUS
1238 EFIAPI
1239 XhcDisableSlotCmd64 (
1240 IN USB_XHCI_INSTANCE *Xhc,
1241 IN UINT8 SlotId
1242 );
1243
1244
1245 /**
1246 Synchronize the specified transfer ring to update the enqueue and dequeue pointer.
1247
1248 @param Xhc The XHCI Instance.
1249 @param TrsRing The transfer ring to sync.
1250
1251 @retval EFI_SUCCESS The transfer ring is synchronized successfully.
1252
1253 **/
1254 EFI_STATUS
1255 EFIAPI
1256 XhcSyncTrsRing (
1257 IN USB_XHCI_INSTANCE *Xhc,
1258 TRANSFER_RING *TrsRing
1259 );
1260
1261 /**
1262 Synchronize the specified event ring to update the enqueue and dequeue pointer.
1263
1264 @param Xhc The XHCI Instance.
1265 @param EvtRing The event ring to sync.
1266
1267 @retval EFI_SUCCESS The event ring is synchronized successfully.
1268
1269 **/
1270 EFI_STATUS
1271 EFIAPI
1272 XhcSyncEventRing (
1273 IN USB_XHCI_INSTANCE *Xhc,
1274 EVENT_RING *EvtRing
1275 );
1276
1277 /**
1278 Check if there is a new generated event.
1279
1280 @param Xhc The XHCI Instance.
1281 @param EvtRing The event ring to check.
1282 @param NewEvtTrb The new event TRB found.
1283
1284 @retval EFI_SUCCESS Found a new event TRB at the event ring.
1285 @retval EFI_NOT_READY The event ring has no new event.
1286
1287 **/
1288 EFI_STATUS
1289 EFIAPI
1290 XhcCheckNewEvent (
1291 IN USB_XHCI_INSTANCE *Xhc,
1292 IN EVENT_RING *EvtRing,
1293 OUT TRB_TEMPLATE **NewEvtTrb
1294 );
1295
1296 /**
1297 Create XHCI transfer ring.
1298
1299 @param Xhc The XHCI Instance.
1300 @param TrbNum The number of TRB in the ring.
1301 @param TransferRing The created transfer ring.
1302
1303 **/
1304 VOID
1305 CreateTransferRing (
1306 IN USB_XHCI_INSTANCE *Xhc,
1307 IN UINTN TrbNum,
1308 OUT TRANSFER_RING *TransferRing
1309 );
1310
1311 /**
1312 Create XHCI event ring.
1313
1314 @param Xhc The XHCI Instance.
1315 @param EventRing The created event ring.
1316
1317 **/
1318 VOID
1319 CreateEventRing (
1320 IN USB_XHCI_INSTANCE *Xhc,
1321 OUT EVENT_RING *EventRing
1322 );
1323
1324 /**
1325 System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted
1326 condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint
1327 Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is
1328 reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the
1329 Stopped to the Running state.
1330
1331 @param Xhc The XHCI Instance.
1332 @param Urb The urb which makes the endpoint halted.
1333
1334 @retval EFI_SUCCESS The recovery is successful.
1335 @retval Others Failed to recovery halted endpoint.
1336
1337 **/
1338 EFI_STATUS
1339 EFIAPI
1340 XhcRecoverHaltedEndpoint (
1341 IN USB_XHCI_INSTANCE *Xhc,
1342 IN URB *Urb
1343 );
1344
1345 /**
1346 System software shall use a Stop Endpoint Command (section 4.6.9) and the Set TR Dequeue Pointer
1347 Command (section 4.6.10) to remove the timed-out TDs from the xHC transfer ring. The next write to
1348 the Doorbell of the Endpoint will transition the Endpoint Context from the Stopped to the Running
1349 state.
1350
1351 @param Xhc The XHCI Instance.
1352 @param Urb The urb which doesn't get completed in a specified timeout range.
1353
1354 @retval EFI_SUCCESS The dequeuing of the TDs is successful.
1355 @retval Others Failed to stop the endpoint and dequeue the TDs.
1356
1357 **/
1358 EFI_STATUS
1359 EFIAPI
1360 XhcDequeueTrbFromEndpoint (
1361 IN USB_XHCI_INSTANCE *Xhc,
1362 IN URB *Urb
1363 );
1364
1365 /**
1366 Stop endpoint through XHCI's Stop_Endpoint cmd.
1367
1368 @param Xhc The XHCI Instance.
1369 @param SlotId The slot id to be configured.
1370 @param Dci The device context index of endpoint.
1371 @param PendingUrb The pending URB to check completion status when stopping the end point.
1372
1373 @retval EFI_SUCCESS Stop endpoint successfully.
1374 @retval Others Failed to stop endpoint.
1375
1376 **/
1377 EFI_STATUS
1378 EFIAPI
1379 XhcStopEndpoint (
1380 IN USB_XHCI_INSTANCE *Xhc,
1381 IN UINT8 SlotId,
1382 IN UINT8 Dci,
1383 IN URB *PendingUrb OPTIONAL
1384 );
1385
1386 /**
1387 Reset endpoint through XHCI's Reset_Endpoint cmd.
1388
1389 @param Xhc The XHCI Instance.
1390 @param SlotId The slot id to be configured.
1391 @param Dci The device context index of endpoint.
1392
1393 @retval EFI_SUCCESS Reset endpoint successfully.
1394 @retval Others Failed to reset endpoint.
1395
1396 **/
1397 EFI_STATUS
1398 EFIAPI
1399 XhcResetEndpoint (
1400 IN USB_XHCI_INSTANCE *Xhc,
1401 IN UINT8 SlotId,
1402 IN UINT8 Dci
1403 );
1404
1405 /**
1406 Set transfer ring dequeue pointer through XHCI's Set_Tr_Dequeue_Pointer cmd.
1407
1408 @param Xhc The XHCI Instance.
1409 @param SlotId The slot id to be configured.
1410 @param Dci The device context index of endpoint.
1411 @param Urb The dequeue pointer of the transfer ring specified
1412 by the urb to be updated.
1413
1414 @retval EFI_SUCCESS Set transfer ring dequeue pointer succeeds.
1415 @retval Others Failed to set transfer ring dequeue pointer.
1416
1417 **/
1418 EFI_STATUS
1419 EFIAPI
1420 XhcSetTrDequeuePointer (
1421 IN USB_XHCI_INSTANCE *Xhc,
1422 IN UINT8 SlotId,
1423 IN UINT8 Dci,
1424 IN URB *Urb
1425 );
1426
1427 /**
1428 Create a new URB for a new transaction.
1429
1430 @param Xhc The XHCI Instance
1431 @param DevAddr The device address
1432 @param EpAddr Endpoint addrress
1433 @param DevSpeed The device speed
1434 @param MaxPacket The max packet length of the endpoint
1435 @param Type The transaction type
1436 @param Request The standard USB request for control transfer
1437 @param Data The user data to transfer
1438 @param DataLen The length of data buffer
1439 @param Callback The function to call when data is transferred
1440 @param Context The context to the callback
1441
1442 @return Created URB or NULL
1443
1444 **/
1445 URB*
1446 XhcCreateUrb (
1447 IN USB_XHCI_INSTANCE *Xhc,
1448 IN UINT8 DevAddr,
1449 IN UINT8 EpAddr,
1450 IN UINT8 DevSpeed,
1451 IN UINTN MaxPacket,
1452 IN UINTN Type,
1453 IN EFI_USB_DEVICE_REQUEST *Request,
1454 IN VOID *Data,
1455 IN UINTN DataLen,
1456 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
1457 IN VOID *Context
1458 );
1459
1460 /**
1461 Free an allocated URB.
1462
1463 @param Xhc The XHCI device.
1464 @param Urb The URB to free.
1465
1466 **/
1467 VOID
1468 XhcFreeUrb (
1469 IN USB_XHCI_INSTANCE *Xhc,
1470 IN URB *Urb
1471 );
1472
1473 /**
1474 Create a transfer TRB.
1475
1476 @param Xhc The XHCI Instance
1477 @param Urb The urb used to construct the transfer TRB.
1478
1479 @return Created TRB or NULL
1480
1481 **/
1482 EFI_STATUS
1483 XhcCreateTransferTrb (
1484 IN USB_XHCI_INSTANCE *Xhc,
1485 IN URB *Urb
1486 );
1487
1488 #endif