2 x64 Long Mode Virtual Memory Management Definitions
5 1) IA-32 Intel(R) Architecture Software Developer's Manual Volume 1:Basic Architecture, Intel
6 2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
7 3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
8 4) AMD64 Architecture Programmer's Manual Volume 2: System Programming
10 Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
11 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
13 This program and the accompanying materials
14 are licensed and made available under the terms and conditions of the BSD License
15 which accompanies this distribution. The full text of the license may be found at
16 http://opensource.org/licenses/bsd-license.php
18 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
19 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
22 #ifndef _VIRTUAL_MEMORY_H_
23 #define _VIRTUAL_MEMORY_H_
26 #define SYS_CODE64_SEL 0x38
43 UINT32 DefaultSize
: 1;
44 UINT32 Granularity
: 1;
51 IA32_IDT_GATE_DESCRIPTOR Ia32IdtEntry
;
54 } X64_IDT_GATE_DESCRIPTOR
;
57 // Page-Map Level-4 Offset (PML4) and
58 // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
63 UINT64 Present
:1; // 0 = Not present in memory, 1 = Present in memory
64 UINT64 ReadWrite
:1; // 0 = Read-Only, 1= Read/Write
65 UINT64 UserSupervisor
:1; // 0 = Supervisor, 1=User
66 UINT64 WriteThrough
:1; // 0 = Write-Back caching, 1=Write-Through caching
67 UINT64 CacheDisabled
:1; // 0 = Cached, 1=Non-Cached
68 UINT64 Accessed
:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
69 UINT64 Reserved
:1; // Reserved
70 UINT64 MustBeZero
:2; // Must Be Zero
71 UINT64 Available
:3; // Available for use by system software
72 UINT64 PageTableBaseAddress
:40; // Page Table Base Address
73 UINT64 AvabilableHigh
:11; // Available for use by system software
74 UINT64 Nx
:1; // No Execute bit
77 } PAGE_MAP_AND_DIRECTORY_POINTER
;
80 // Page Table Entry 4KB
84 UINT64 Present
:1; // 0 = Not present in memory, 1 = Present in memory
85 UINT64 ReadWrite
:1; // 0 = Read-Only, 1= Read/Write
86 UINT64 UserSupervisor
:1; // 0 = Supervisor, 1=User
87 UINT64 WriteThrough
:1; // 0 = Write-Back caching, 1=Write-Through caching
88 UINT64 CacheDisabled
:1; // 0 = Cached, 1=Non-Cached
89 UINT64 Accessed
:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
90 UINT64 Dirty
:1; // 0 = Not Dirty, 1 = written by processor on access to page
92 UINT64 Global
:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
93 UINT64 Available
:3; // Available for use by system software
94 UINT64 PageTableBaseAddress
:40; // Page Table Base Address
95 UINT64 AvabilableHigh
:11; // Available for use by system software
96 UINT64 Nx
:1; // 0 = Execute Code, 1 = No Code Execution
99 } PAGE_TABLE_4K_ENTRY
;
102 // Page Table Entry 2MB
106 UINT64 Present
:1; // 0 = Not present in memory, 1 = Present in memory
107 UINT64 ReadWrite
:1; // 0 = Read-Only, 1= Read/Write
108 UINT64 UserSupervisor
:1; // 0 = Supervisor, 1=User
109 UINT64 WriteThrough
:1; // 0 = Write-Back caching, 1=Write-Through caching
110 UINT64 CacheDisabled
:1; // 0 = Cached, 1=Non-Cached
111 UINT64 Accessed
:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
112 UINT64 Dirty
:1; // 0 = Not Dirty, 1 = written by processor on access to page
113 UINT64 MustBe1
:1; // Must be 1
114 UINT64 Global
:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
115 UINT64 Available
:3; // Available for use by system software
117 UINT64 MustBeZero
:8; // Must be zero;
118 UINT64 PageTableBaseAddress
:31; // Page Table Base Address
119 UINT64 AvabilableHigh
:11; // Available for use by system software
120 UINT64 Nx
:1; // 0 = Execute Code, 1 = No Code Execution
126 // Page Table Entry 1GB
130 UINT64 Present
:1; // 0 = Not present in memory, 1 = Present in memory
131 UINT64 ReadWrite
:1; // 0 = Read-Only, 1= Read/Write
132 UINT64 UserSupervisor
:1; // 0 = Supervisor, 1=User
133 UINT64 WriteThrough
:1; // 0 = Write-Back caching, 1=Write-Through caching
134 UINT64 CacheDisabled
:1; // 0 = Cached, 1=Non-Cached
135 UINT64 Accessed
:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
136 UINT64 Dirty
:1; // 0 = Not Dirty, 1 = written by processor on access to page
137 UINT64 MustBe1
:1; // Must be 1
138 UINT64 Global
:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
139 UINT64 Available
:3; // Available for use by system software
141 UINT64 MustBeZero
:17; // Must be zero;
142 UINT64 PageTableBaseAddress
:22; // Page Table Base Address
143 UINT64 AvabilableHigh
:11; // Available for use by system software
144 UINT64 Nx
:1; // 0 = Execute Code, 1 = No Code Execution
147 } PAGE_TABLE_1G_ENTRY
;
153 #define IA32_PG_P BIT0
154 #define IA32_PG_RW BIT1
155 #define IA32_PG_PS BIT7
157 #define PAGING_PAE_INDEX_MASK 0x1FF
159 #define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull
160 #define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull
161 #define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull
163 #define PAGING_L1_ADDRESS_SHIFT 12
164 #define PAGING_L2_ADDRESS_SHIFT 21
165 #define PAGING_L3_ADDRESS_SHIFT 30
166 #define PAGING_L4_ADDRESS_SHIFT 39
168 #define PAGING_PML4E_NUMBER 4
170 #define PAGE_TABLE_POOL_ALIGNMENT BASE_2MB
171 #define PAGE_TABLE_POOL_UNIT_SIZE SIZE_2MB
172 #define PAGE_TABLE_POOL_UNIT_PAGES EFI_SIZE_TO_PAGES (PAGE_TABLE_POOL_UNIT_SIZE)
173 #define PAGE_TABLE_POOL_ALIGN_MASK \
174 (~(EFI_PHYSICAL_ADDRESS)(PAGE_TABLE_POOL_ALIGNMENT - 1))
183 Enable Execute Disable Bit.
187 EnableExecuteDisableBit (
194 @param[in] PhysicalAddress Start physical address the 2M page covered.
195 @param[in, out] PageEntry2M Pointer to 2M page entry.
196 @param[in] StackBase Stack base address.
197 @param[in] StackSize Stack size.
202 IN EFI_PHYSICAL_ADDRESS PhysicalAddress
,
203 IN OUT UINT64
*PageEntry2M
,
204 IN EFI_PHYSICAL_ADDRESS StackBase
,
209 Allocates and fills in the Page Directory and Page Table Entries to
210 establish a 1:1 Virtual to Physical mapping.
212 @param[in] StackBase Stack base address.
213 @param[in] StackSize Stack size.
215 @return The address of 4 level page map.
219 CreateIdentityMappingPageTables (
220 IN EFI_PHYSICAL_ADDRESS StackBase
,
227 Fix up the vector number in the vector code.
229 @param VectorBase Base address of the vector handler.
230 @param VectorNum Index of vector.
243 Get the information of vector template.
245 @param TemplateBase Base address of the template code.
247 @return Size of the Template code.
252 AsmGetVectorTemplatInfo (
253 OUT VOID
**TemplateBase
257 Clear legacy memory located at the first 4K-page.
259 This function traverses the whole HOB list to check if memory from 0 to 4095
260 exists and has not been allocated, and then clear it if so.
262 @param HobStart The start of HobList passed to DxeCore.
271 Return configure status of NULL pointer detection feature.
273 @return TRUE NULL pointer detection feature is enabled
274 @return FALSE NULL pointer detection feature is disabled
277 IsNullDetectionEnabled (
282 Prevent the memory pages used for page table from been overwritten.
284 @param[in] PageTableBase Base address of page table (CR3).
285 @param[in] Level4Paging Level 4 paging flag.
289 EnablePageTableProtection (
290 IN UINTN PageTableBase
,
291 IN BOOLEAN Level4Paging
295 This API provides a way to allocate memory for page table.
297 This API can be called more than once to allocate memory for page tables.
299 Allocates the number of 4KB pages and returns a pointer to the allocated
300 buffer. The buffer returned is aligned on a 4KB boundary.
302 If Pages is 0, then NULL is returned.
303 If there is not enough memory remaining to satisfy the request, then NULL is
306 @param Pages The number of 4 KB pages to allocate.
308 @return A pointer to the allocated buffer or NULL if allocation fails.
312 AllocatePageTableMemory (